TWI611578B - 用以減少化合物半導體晶圓變形之改良結構 - Google Patents

用以減少化合物半導體晶圓變形之改良結構 Download PDF

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TWI611578B
TWI611578B TW106119867A TW106119867A TWI611578B TW I611578 B TWI611578 B TW I611578B TW 106119867 A TW106119867 A TW 106119867A TW 106119867 A TW106119867 A TW 106119867A TW I611578 B TWI611578 B TW I611578B
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compound semiconductor
semiconductor wafer
layer
stress
improved structure
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TW106119867A
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TW201906153A (zh
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花長煌
朱文慧
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穩懋半導體股份有限公司
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Priority to TW106119867A priority Critical patent/TWI611578B/zh
Priority to US15/684,408 priority patent/US20180366417A1/en
Priority to JP2017178674A priority patent/JP2019004128A/ja
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Publication of TWI611578B publication Critical patent/TWI611578B/zh
Publication of TW201906153A publication Critical patent/TW201906153A/zh

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Abstract

一種用以減少化合物半導體晶圓變形之改良結構,包括:一接觸金屬層、至少一應力平衡層、複數個應力平衡層通孔以及一晶粒黏著層。其中接觸金屬層係形成於一化合物半導體晶圓之一下表面;至少一應力平衡層係形成於接觸金屬層之一下表面,其中至少一應力平衡層係為非導電材料;其中每一複數個應力平衡層通孔係分別貫穿至少一應力平衡層;晶粒黏著層係形成於至少一應力平衡層之一下表面以及每一複數個應力平衡層通孔之一內表面,其中晶粒黏著層係為一導電材料,其中透過複數個應力平衡層通孔使得晶粒黏著層以及接觸金屬層電性接觸。藉由在接觸金屬層以及晶粒黏著層之間插入至少一應力平衡層,藉此平衡化合物半導體晶圓所受之應力,以減少化合物半導體晶圓之變形。

Description

用以減少化合物半導體晶圓變形之改良結構
本發明係有關一種用以減少化合物半導體晶圓變形之改良結構,尤指一種用以平衡化合物半導體晶圓應力之改良結構。
在一化合物半導體晶圓上形成積體電路之製程中,或多或少都會在累積應力,使得化合物半導體晶圓承受一應力。在一些狀況下,會使得化合物半導體晶圓承受較大之應力,例如,於化合物半導體晶圓之上形成一應力薄膜,或是於化合物半導體晶圓上成長具應力之磊晶結構。而這應力若無法妥善平衡,則會造成化合物半導體晶圓之弓翹(Bowing)變形,甚至在化合物半導體晶圓之邊緣處造成破碎。此外,在化合物半導體晶圓之薄化製程後,由於化合物半導體晶圓之厚度變薄,因而使得化合物半導體晶圓更無法平衡原先所承受之應力,進而造成化合物半導體晶圓之弓翹變形更為嚴重,或甚至在化合物半導體晶圓之邊緣處造成破碎。
以化合物半導體晶圓之尺寸來說,當化合物半導體晶圓之直徑小於3英吋時,應力造成化合物半導體晶圓之弓翹變形較不明顯。而當化合物半導體晶圓之直徑大於3英吋時,例如4英吋、5英吋、6英吋或更大者, 應力造成化合物半導體晶圓之弓翹變形就非常顯著。
一般而言,由於在化合物半導體晶圓上形成積體電路時,常需要有多層的磊晶結構,也因此,相對於在矽半導體晶圓上形成矽半導體積體電路之製程中,化合物半導體晶圓所承受的應力通常會比矽半導體晶圓所承受之應力相對大許多。在一習知技術中,揭露一改善結構,以平衡矽半導體晶圓所受之應力。請參見第3圖,係為一習知技術之矽半導體晶圓之改良結構之剖面示意圖。一積體電路11係形成於一矽半導體晶圓10之一上表面101。一應力平衡層12係形成於矽半導體晶圓10之一下表面102,以平衡矽半導體晶圓10於形成積體電路11之製程過中所累積之應力。然則習知技術並未揭露如何有效平衡化合物半導體晶圓所受應力之結構(化合物半導體晶圓所受之應力更大於矽半導體晶圓所受之應力)。
此外,若要應用習知技術之矽半導體晶圓之改良結構在化合物半導體晶圓時,當需要在一化合物半導體晶圓之一下表面形成一導電層以作為導電用途時,或是需要在化合物半導體晶圓之下表面形成一金屬層,使得金屬層與化合物半導體晶圓之下表面形成歐姆接觸,而金屬層得以形成一歐姆電極,則因習知技術應力平衡層12係直接形成於晶圓之下表面,而無法達成需求。
有鑑於此,發明人開發出簡便組裝的設計,能夠避免上述的缺點,安裝方便,又具有成本低廉的優點,以兼顧使用彈性與經濟性等考量,因此遂有本發明之產生。
本發明所欲解決之技術問題在於如何於一化合物半導體晶圓之一下表面形成一改良結構,使得改良結構包含至少一應力平衡層以及一金屬層,使得改良結構同時具有應力平衡以及導電之功能。
為解決前述問題,以達到所預期之功效,本發明提供一種用以減少化合物半導體晶圓變形之改良結構,包括:一接觸金屬層、至少一應力平衡層、複數個應力平衡層通孔以及一晶粒黏著層。其中接觸金屬層係形成於一化合物半導體晶圓之一下表面。其中至少一應力平衡層係形成於接觸金屬層之一下表面,其中至少一應力平衡層係為非導電材料。其中每一複數個應力平衡層通孔係分別貫穿至少一應力平衡層。其中晶粒黏著層係形成於至少一應力平衡層之一下表面以及每一複數個應力平衡層通孔之一內表面,其中晶粒黏著層係為一導電材料,其中透過複數個應力平衡層通孔使得晶粒黏著層以及接觸金屬層電性接觸。藉由在接觸金屬層以及晶粒黏著層之間插入至少一應力平衡層,藉此平衡化合物半導體晶圓所受之應力,以減少化合物半導體晶圓之變形。由於接觸金屬層以及晶粒黏著層皆為導電材料,且接觸金屬層以及晶粒黏著層透過複數個應力平衡層通孔而電性接觸,因此本發明之用以減少化合物半導體晶圓變形之改良結構同時具有應力平衡以及導電之功能。
於一實施例中,前述之用以減少化合物半導體晶圓變形之改良結構,其中接觸金屬層係與化合物半導體晶圓之下表面形成一歐姆接觸,使得接觸金屬層形成一歐姆電極。
於一實施例中,前述之用以減少化合物半導體晶圓變形之改良結構,其中歐姆電極係用於至少一二極體,其中至少一二極體係包括選 自以下群組之至少一者:一PN二極體、一蕭基二極體、一發光二極體、一雷射二極體、一垂直共振腔面射型雷射二極體、一光電二極體、一變容二極體、一變阻二極體、一恆流二極體以及一穩壓二極體。
於一實施例中,前述之用以減少化合物半導體晶圓變形之改良結構,其中每一至少一二極體包括複數個應力平衡層通孔之至少一者。
於一實施例中,前述之用以減少化合物半導體晶圓變形之改良結構,其中晶粒黏著層係填滿複數個應力平衡層通孔之每一者。
於一實施例中,前述之用以減少化合物半導體晶圓變形之改良結構,其中化合物半導體晶圓之一厚度係大於或等於25μm且小於或等於350μm。
於一實施例中,前述之用以減少化合物半導體晶圓變形之改良結構,其中化合物半導體晶圓之一直徑係大於或等於3英吋。
於一實施例中,前述之用以減少化合物半導體晶圓變形之改良結構,其中化合物半導體晶圓之材料係包括選自以下群組之一者:砷化鎵、藍寶石、磷化銦、磷化鎵、碳化矽、氮化鎵、氮化鋁、硒化鋅(ZnSe)、砷化銦(InAs)、銻化鎵(GaSb)。
於一實施例中,前述之用以減少化合物半導體晶圓變形之改良結構,其中接觸金屬層之材料係包括選自以下群組之至少一者:鈀、鍺、鎳、鈦、鉑、金以及銀。
於一實施例中,前述之用以減少化合物半導體晶圓變形之改良結構,其中至少一應力平衡層之材料係包括選自以下群組之至少一者:介電材料、玻璃以及聚合物。
於一實施例中,前述之用以減少化合物半導體晶圓變形之改良結構,其中至少一應力平衡層之材料係包括選自以下群組之至少一者:氮化矽、碳化矽以及二氧化矽。
於一實施例中,前述之用以減少化合物半導體晶圓變形之改良結構,其中至少一應力平衡層係以化學氣相沈積法或塗佈方式形成於接觸金屬層之下表面。
於一實施例中,前述之用以減少化合物半導體晶圓變形之改良結構,其中晶粒黏著層之材料係包括選自以下群組之至少一者:金、金合金、銀、銀合金、錫、錫合金、銀膠。
於一實施例中,前述之用以減少化合物半導體晶圓變形之改良結構,其中至少一應力平衡層之一厚度係大於或等於50nm且小於或等於5μm。
為進一步了解本發明,以下舉較佳之實施例,配合圖式、圖號,將本發明之具體構成內容及其所達成的功效詳細說明如下。
1‧‧‧改良結構
1’‧‧‧改良結構
10‧‧‧矽半導體晶圓
101‧‧‧矽半導體晶圓之上表面
102‧‧‧矽半導體晶圓之下表面
11‧‧‧積體電路
12‧‧‧應力平衡層
2‧‧‧垂直共振腔面射型雷射二極體
20‧‧‧化合物半導體晶圓
201‧‧‧化合物半導體晶圓之上表面
202‧‧‧化合物半導體晶圓之下表面
30‧‧‧接觸金屬層
302‧‧‧接觸金屬層之下表面
40‧‧‧應力平衡層
402‧‧‧應力平衡層之下表面
50‧‧‧晶粒黏著層
60‧‧‧n型分佈式布拉格反射器
62‧‧‧量子井結構
64‧‧‧氧化侷限層
66‧‧‧p型分佈式布拉格反射器
67‧‧‧平台結構
68‧‧‧p型歐姆電極
69‧‧‧凹槽
70‧‧‧虛線
72‧‧‧應力平衡層通孔
74‧‧‧應力平衡層通孔之內表面
76‧‧‧晶粒黏著層凹槽
第1A圖係為本發明一種用以減少化合物半導體晶圓變形之改良結構之一具體實施例之剖面示意圖。
第1B圖係為本發明一種用以減少化合物半導體晶圓變形之改良結構之另一具體實施例之剖面示意圖。
第2A圖係為應用本發明一種用以減少化合物半導體晶圓變形之改良結 構於垂直共振腔面射型雷射二極體之剖面示意圖。
第2B圖係為應用本發明一種用以減少化合物半導體晶圓變形之改良結構之一垂直共振腔面射型雷射二極體之剖面示意圖。
第3圖係為一習知技術之矽半導體晶圓之改良結構之剖面示意圖。
請參閱第1A圖,其係為本發明一種用以減少化合物半導體晶圓變形之改良結構之一具體實施例之剖面示意圖。本發明一種用以減少化合物半導體晶圓變形之改良結構1包括:一接觸金屬層30、至少一應力平衡層40、複數個應力平衡層通孔72以及一晶粒黏著層50。其中接觸金屬層30係形成於一化合物半導體晶圓20之一下表面202。其中化合物半導體晶圓20具有一上表面201以及下表面202。其中化合物半導體晶圓20之材料係包括選自以下群組之一者:砷化鎵、藍寶石、磷化銦、磷化鎵、碳化矽、氮化鎵、氮化鋁、硒化鋅(ZnSe)、砷化銦(InAs)、銻化鎵(GaSb)。其中化合物半導體晶圓20之一厚度係大於或等於25μm且小於或等於350μm。在一些較佳之實施例中,化合物半導體晶圓20之一直徑係大於或等於3英吋。由於化合物半導體晶圓20之直徑越大,化合物半導體晶圓20之變形會越明顯,因此本發明一種用以減少化合物半導體晶圓變形之改良結構1應用於直徑大於或等於3英吋之化合物半導體晶圓20時,改善化合物半導體晶圓20變形之效果更加顯著。其中接觸金屬層30之材料係包括選自以下群組之至少一者:鈀、鍺、鎳、鈦、鉑、金以及銀。其中至少一應力平衡層40係形成於接觸金屬層30之一下表面302。其中至少一應力平衡層40係為非導電材料。其中至少 一應力平衡層40係以化學氣相沈積法、塗佈、蒸鍍、離子鍍或濺鍍等方式形成於接觸金屬層30之下表面302。在一些較佳之實施例中,至少一應力平衡層40係以化學氣相沈積法或塗佈方式形成於接觸金屬層30之下表面302。其中至少一應力平衡層40之一厚度係大於或等於50nm且小於或等於5μm。在一些實施例中,至少一應力平衡層40之材料係包括選自以下群組之至少一者:介電材料、玻璃以及聚合物。在一些較佳之實施例中,至少一應力平衡層40之材料係包括選自以下群組之至少一者:氮化矽、碳化矽以及二氧化矽。其中每一個應力平衡層通孔72係貫穿至少一應力平衡層40。其中晶粒黏著層50係形成於至少一應力平衡層40之一下表面402以及每一個應力平衡層通孔72之一內表面72。其中晶粒黏著層50係為一導電材料,透過複數個應力平衡層通孔72使得晶粒黏著層50以及接觸金屬層30電性接觸。其中晶粒黏著層50之材料係包括選自以下群組之至少一者:金、金合金、銀、銀合金、錫、錫合金、銀膠。藉由在接觸金屬層30以及晶粒黏著層50之間插入至少一應力平衡層40,藉此平衡化合物半導體晶圓20所受之應力,以減少化合物半導體晶圓20之變形。由於接觸金屬層30以及晶粒黏著層50皆為導電材料,且接觸金屬層30以及晶粒黏著層50係透過複數個應力平衡層通孔72而電性接觸,因此本發明之一種用以減少化合物半導體晶圓變形之改良結構1,不僅能平衡化合物半導體晶圓20所受之應力以減少化合物半導體晶圓20之變形,此改良結構1更具有導電之功能,以符合一些特定應用之所需。本發明一種用以減少化合物半導體晶圓變形之改良結構1係可根據形成於化合物半導體晶圓20之上表面201之結構之應力大小,來選擇適當的改良結構1(包含接觸金屬層30、至少一應力平衡層40以及晶粒黏著層50)之材料以及 厚度,以平衡形成於化合物半導體晶圓20之上表面201之結構之應力。
在一些較佳之實施例中,化合物半導體晶圓20之材料係包括選自以下群組之一者:砷化鎵、藍寶石、磷化銦、磷化鎵、碳化矽、氮化鎵以及氮化鋁。在一些較佳之實施例中,接觸金屬層30之材料係包括選自以下群組之至少一者:鈀、鍺、鎳、鈦、鉑、金以及銀。在一些較佳之實施例中,晶粒黏著層50之材料係包括選自以下群組之至少一者:金以及金合金。
在一些較佳之實施例中,化合物半導體晶圓20之一厚度係大於或等於25μm且小於或等於350μm、大於或等於35μm且小於或等於350μm、大於或等於50μm且小於或等於350μm、大於或等於75μm且小於或等於350μm、大於或等於100μm且小於或等於350μm、大於或等於25μm且小於或等於300μm、大於或等於25μm且小於或等於250μm、大於或等於25μm且小於或等於200μm、大於或等於25μm且小於或等於150μm、或大於或等於25μm且小於或等於100μm。在一些較佳之實施例中,至少一應力平衡層40之一厚度係大於或等於50nm且小於或等於5μm、大於或等於75nm且小於或等於5μm、大於或等於100nm且小於或等於5μm、大於或等於150nm且小於或等於5μm、大於或等於200nm且小於或等於5μm、大於或等於250nm且小於或等於5μm、大於或等於50nm且小於或等於4.5μm、大於或等於50nm且小於或等於4μm、大於或等於50nm且小於或等於3.5μm、或大於或等於50nm且小於或等於3μm。
請參閱第1B圖,其係為本發明一種用以減少化合物半導體晶圓變形之改良結構之另一具體實施例之剖面示意圖。第1B圖之實施例之 主要結構係與第1A圖之實施例之主要結構大致相同,惟,其中晶粒黏著層50具有複數個晶粒黏著層凹槽76。在形成晶粒黏著層50時,晶粒黏著層凹槽76之一寬度以及一深度係會隨著應力平衡層通孔72之一寬度以及一深度、應力平衡層40之一厚度、以及晶粒黏著層50之一厚度所影響。在一些實施例中,晶粒黏著層凹槽76之深度小於或等於晶粒黏著層50之厚度,使得晶粒黏著層50填滿每一個應力平衡層通孔72。在另一些實施例中,晶粒黏著層凹槽76之深度大於晶粒黏著層50之厚度,使得應力平衡層通孔72並未被晶粒黏著層50所填滿。
請參閱第2A圖,其係為應用本發明一種用以減少化合物半導體晶圓變形之改良結構於垂直共振腔面射型雷射二極體之剖面示意圖。其中係應用本發明之用以減少化合物半導體晶圓變形之改良結構1’於形成複數個垂直共振腔面射型雷射二極體2(Vcsel)。在第2A圖之實施例中,本發明一種用以減少化合物半導體晶圓變形之改良結構1’包括:一接觸金屬層30、至少一應力平衡層40、複數個應力平衡層通孔72以及一晶粒黏著層50。其中接觸金屬層30係形成於一化合物半導體晶圓20之一下表面202。至少一應力平衡層40係形成於接觸金屬層30之一下表面302。每一個應力平衡層通孔72係貫穿至少一應力平衡層40。晶粒黏著層50係形成於至少一應力平衡層40之一下表面402以及每一個應力平衡層通孔72之一內表面74,其中透過複數個應力平衡層通孔72使得晶粒黏著層50以及接觸金屬層30電性接觸。第2A圖實施例中之本發明一種用以減少化合物半導體晶圓變形之改良結構1’係與第1A圖之實施例之改良結構1大致相同,惟,其中接觸金屬層30係與化合物半導體晶圓20之下表面202形成一歐姆接觸,使得接觸金屬層 30形成一n型歐姆電極。在第2A圖中,更包括以下結構:一n型分佈式布拉格反射器60、一量子井結構62、一氧化侷限層64、一p型分佈式布拉格反射器66、一p型歐姆電極68、複數個平台結構67以及複數個凹槽69。其中n型分佈式布拉格反射器60係形成於化合物半導體晶圓20之一上表面201。量子井結構62係形成於n型分佈式布拉格反射器60之上。氧化侷限層64係形成於量子井結構62之上。p型分佈式布拉格反射器66係形成於氧化侷限層64之上。p型歐姆電極68係形成於p型分佈式布拉格反射器66之上。其中每一個凹槽69,係經由蝕刻移除在該凹槽69的區域內之p型歐姆電極68、p型分佈式布拉格反射器66以及氧化侷限層64,以形成複數個平台結構67。其中每一個平台結構67包括:p型歐姆電極68、p型分佈式布拉格反射器66以及氧化侷限層64。請同時參閱第2B圖,其係為應用本發明一種用以減少化合物半導體晶圓變形之改良結構1’之一垂直共振腔面射型雷射二極體2之剖面示意圖。在第2A圖中,係可沿著虛線70係可切割出複數個垂直共振腔面射型雷射二極體2,使得切割後之每一個垂直共振腔面射型雷射二極體2具有如第2B圖所示之結構。其中每一個垂直共振腔面射型雷射二極體2包括:晶粒黏著層50、至少一應力平衡層40、至少一應力平衡層通孔72、接觸金屬層30(n型歐姆電極)、化合物半導體晶圓20、n型分佈式布拉格反射器60、量子井結構62、氧化侷限層64、p型分佈式布拉格反射器66、p型歐姆電極68以及一個平台結構67。
在一些實施例中,前述如第2A圖之本發明之一種用以減少化合物半導體晶圓變形之改良結構1’(其中接觸金屬層30係與化合物半導體晶圓20之下表面202形成一歐姆接觸,使得接觸金屬層30形成一歐姆電 極),其中接觸金屬層30所形成之歐姆電極除了可以如第2A圖應用於垂直共振腔面射型雷射二極體2之外,也可應用於選自以下群組之至少一二極體中:一PN二極體、一蕭基二極體、一發光二極體、一雷射二極體、一光電二極體、一變容二極體、一變阻二極體、一恆流二極體以及一穩壓二極體。
以上所述乃是本發明之具體實施例及所運用之技術手段,根據本文的揭露或教導可衍生推導出許多的變更與修正,仍可視為本發明之構想所作之等效改變,其所產生之作用仍未超出說明書及圖式所涵蓋之實質精神,均應視為在本發明之技術範疇之內,合先陳明。
綜上所述,依上文所揭示之內容,本發明確可達到發明之預期目的,提供一種用以減少化合物半導體晶圓變形之改良結構,極具產業上利用之價植,爰依法提出發明專利申請。
1‧‧‧改良結構
20‧‧‧化合物半導體晶圓
201‧‧‧化合物半導體晶圓之上表面
202‧‧‧化合物半導體晶圓之下表面
30‧‧‧接觸金屬層
302‧‧‧接觸金屬層之下表面
40‧‧‧應力平衡層
402‧‧‧應力平衡層之下表面
50‧‧‧晶粒黏著層
72‧‧‧應力平衡層通孔
74‧‧‧應力平衡層通孔之內表面

Claims (14)

  1. 一種用以減少化合物半導體晶圓變形之改良結構,包括:一接觸金屬層,係形成於一化合物半導體晶圓之一下表面;至少一應力平衡層,係形成於該接觸金屬層之一下表面,其中該至少一應力平衡層係為非導電材料;複數個應力平衡層通孔,其中每一該複數個應力平衡層通孔係分別貫穿該至少一應力平衡層;以及一晶粒黏著層,係形成於該至少一應力平衡層之一下表面以及每一該複數個應力平衡層通孔之一內表面,其中該晶粒黏著層係為一導電材料,其中透過該複數個應力平衡層通孔使得該晶粒黏著層以及該接觸金屬層電性接觸;藉由在該接觸金屬層以及該晶粒黏著層之間插入該至少一應力平衡層,藉此平衡該化合物半導體晶圓所受之應力,以減少該化合物半導體晶圓之變形。
  2. 如申請專利範圍第1項所述之用以減少化合物半導體晶圓變形之改良結構,其中該接觸金屬層係與該化合物半導體晶圓之該下表面形成一歐姆接觸,使得該接觸金屬層形成一歐姆電極。
  3. 如申請專利範圍第2項所述之用以減少化合物半導體晶圓變形之改良結構,其中該歐姆電極係用於至少一二極體,其中該至少一二極體係包括選自以下群組之至少一者:一PN二極體、一蕭基二極體、一發光二極體、一雷射二極體、一垂直共振腔面射型雷射二極體、一光電二極體、一變容二極體、一變阻二極體、一恆流二極體以及一穩壓二極體。
  4. 如申請專利範圍第3項所述之用以減少化合物半導體晶圓變形之改良結構,其中每一該至少一二極體包括該複數個應力平衡層通孔之至少一者。
  5. 如申請專利範圍第1項至第4項中任一項所述之用以減少化合物半導體晶圓變形之改良結構,其中該晶粒黏著層係填滿該複數個應力平衡層通孔之每一者。
  6. 如申請專利範圍第1項所述之用以減少化合物半導體晶圓變形之改良結構,其中該化合物半導體晶圓之一厚度係大於或等於25μm且小於或等於350μm。
  7. 如申請專利範圍第1項所述之用以減少化合物半導體晶圓變形之改良結構,其中該化合物半導體晶圓之一直徑係大於或等於3英吋。
  8. 如申請專利範圍第1項所述之用以減少化合物半導體晶圓變形之改良結構,其中該化合物半導體晶圓之材料係包括選自以下群組之一者:砷化鎵、藍寶石、磷化銦、磷化鎵、碳化矽、氮化鎵、氮化鋁、硒化鋅、砷化銦、銻化鎵。
  9. 如申請專利範圍第1項所述之用以減少化合物半導體晶圓變形之改良結構,其中該接觸金屬層之材料係包括選自以下群組之至少一者:鈀、鍺、鎳、鈦、鉑、金以及銀。
  10. 如申請專利範圍第1項所述之用以減少化合物半導體晶圓變形之改良結構,其中該至少一應力平衡層之材料係包括選自以下群組之至少一者:介電材料、玻璃以及聚合物。
  11. 如申請專利範圍第10項所述之用以減少化合物半導體晶圓變形之改良結構,其中該至少一應力平衡層之材料係包括選自以下群組之至少一 者:氮化矽、碳化矽以及二氧化矽。
  12. 如申請專利範圍第10項所述之用以減少化合物半導體晶圓變形之改良結構,其中該至少一應力平衡層係以化學氣相沈積法或塗佈方式形成於該接觸金屬層之該下表面。
  13. 如申請專利範圍第1項所述之用以減少化合物半導體晶圓變形之改良結構,其中該晶粒黏著層之材料係包括選自以下群組之至少一者:金、金合金、銀、銀合金、錫、錫合金、銀膠。
  14. 如申請專利範圍第1項所述之用以減少化合物半導體晶圓變形之改良結構,其中該至少一應力平衡層之一厚度係大於或等於50nm且小於或等於5μm。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010102943A1 (en) * 2009-03-12 2010-09-16 S.O.I. Tec Silicon On Insulator Technologies A method of fabricating a multilayer structure with circuit layer transfer
CN102479683A (zh) * 2010-11-30 2012-05-30 台湾积体电路制造股份有限公司 通过高热膨胀系数(cte)层降低晶圆变形
TW201318047A (zh) * 2011-10-21 2013-05-01 Win Semiconductors Corp 高抗折強度半導體晶元改良結構及其製程方法
TW201344869A (zh) * 2012-04-18 2013-11-01 Win Semiconductors Corp 半導體元件背面銅金屬之改良結構及其製程方法
TW201546230A (zh) * 2014-05-13 2015-12-16 Nitto Denko Corp 片狀樹脂組合物、積層片及半導體裝置之製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007184316A (ja) * 2006-01-04 2007-07-19 Toshiba Corp 半導体装置
JP5554126B2 (ja) * 2010-04-06 2014-07-23 三菱電機株式会社 SiC半導体素子の製造方法
JP2012129537A (ja) * 2012-02-03 2012-07-05 Fuji Electric Co Ltd 半導体装置
JP6399738B2 (ja) * 2013-09-25 2018-10-03 富士電機株式会社 半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010102943A1 (en) * 2009-03-12 2010-09-16 S.O.I. Tec Silicon On Insulator Technologies A method of fabricating a multilayer structure with circuit layer transfer
CN102479683A (zh) * 2010-11-30 2012-05-30 台湾积体电路制造股份有限公司 通过高热膨胀系数(cte)层降低晶圆变形
TW201318047A (zh) * 2011-10-21 2013-05-01 Win Semiconductors Corp 高抗折強度半導體晶元改良結構及其製程方法
TW201344869A (zh) * 2012-04-18 2013-11-01 Win Semiconductors Corp 半導體元件背面銅金屬之改良結構及其製程方法
TW201546230A (zh) * 2014-05-13 2015-12-16 Nitto Denko Corp 片狀樹脂組合物、積層片及半導體裝置之製造方法

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