JP6399738B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP6399738B2 JP6399738B2 JP2013199043A JP2013199043A JP6399738B2 JP 6399738 B2 JP6399738 B2 JP 6399738B2 JP 2013199043 A JP2013199043 A JP 2013199043A JP 2013199043 A JP2013199043 A JP 2013199043A JP 6399738 B2 JP6399738 B2 JP 6399738B2
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- JP
- Japan
- Prior art keywords
- semiconductor substrate
- compensation film
- semiconductor
- substrate
- semiconductor device
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
前記補償膜は、前記半導体基板の全面を被覆せず、開口された窓部を複数有し、
前記半導体基板を半導体チップに分割するための分割線上に該分割線と一致する格子状で凸状の前記補償膜の配置とし、さらに前記半導体基板の電極膜が前記補償膜および当該補償膜の開口を覆い前記はんだおよび前記半導体基板に接することを特徴とする。
本発明の実施の形態にかかる半導体装置について説明する。図1は、本発明の実施の形態にかかる半導体装置を示す断面図である。
12 半導体装置
13 カソード電極
14 補償膜
15 窓部
1P 半導体チップ
23 実装基板
δ 段差
D 分割線
Claims (5)
- 炭化ケイ素、窒化ガリウム、ダイアモンドのいずれかである半導体基板、前記半導体基板を実装基板にはんだで接合する側の当該半導体基板の面上に、当該半導体基板の反りを相殺する応力を発生させる凸状の補償膜を有し、
前記補償膜は、前記半導体基板の全面を被覆せず、開口された窓部を複数有し、
前記半導体基板を半導体チップに分割するための分割線上に該分割線と一致する格子状で凸状の前記補償膜の配置とし、さらに前記半導体基板の電極膜が前記補償膜および当該補償膜の開口を覆い前記はんだおよび前記半導体基板に接することを特徴とする半導体装置。 - 前記補償膜は、前記半導体基板の反りの方向に基づいて、前記半導体基板の線膨張係数に対し、大きいまたは小さい線膨張係数の材質を用いて前記半導体基板の反りを相殺することを特徴とする請求項1に記載の半導体装置。
- 前記補償膜は、前記半導体基板よりも線膨張係数が小さい酸化ケイ素または窒化ケイ素であることを特徴とする請求項2に記載の半導体装置。
- 前記補償膜は、前記半導体基板よりも線膨張係数が大きく絶縁性を有する、金属酸化物、金属窒化物、金属酸窒化物、もしくはセラミック、サーメットであることを特徴とする請求項2に記載の半導体装置。
- 前記補償膜は、アルミナ、ジルコニア、リチウム系酸化物であることを特徴とする請求項4に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013199043A JP6399738B2 (ja) | 2013-09-25 | 2013-09-25 | 半導体装置 |
Applications Claiming Priority (1)
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---|---|---|---|
JP2013199043A JP6399738B2 (ja) | 2013-09-25 | 2013-09-25 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2015065350A JP2015065350A (ja) | 2015-04-09 |
JP6399738B2 true JP6399738B2 (ja) | 2018-10-03 |
Family
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JP2013199043A Expired - Fee Related JP6399738B2 (ja) | 2013-09-25 | 2013-09-25 | 半導体装置 |
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JP (1) | JP6399738B2 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102455149B1 (ko) | 2015-05-06 | 2022-10-18 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
WO2018020640A1 (ja) * | 2016-07-28 | 2018-02-01 | 三菱電機株式会社 | 半導体装置 |
US9998109B1 (en) * | 2017-05-15 | 2018-06-12 | Cree, Inc. | Power module with improved reliability |
TWI611578B (zh) * | 2017-06-14 | 2018-01-11 | 穩懋半導體股份有限公司 | 用以減少化合物半導體晶圓變形之改良結構 |
US20220302309A1 (en) * | 2019-08-09 | 2022-09-22 | Hitachi Energy Switzerland Ag | Strain Enhanced SiC Power Semiconductor Device and Method of Manufacturing |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000114556A (ja) * | 1998-09-30 | 2000-04-21 | Sharp Corp | 太陽電池およびその製造方法 |
JP2008098529A (ja) * | 2006-10-13 | 2008-04-24 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2010118573A (ja) * | 2008-11-14 | 2010-05-27 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JP2012114388A (ja) * | 2010-11-29 | 2012-06-14 | Sharp Corp | 両面電極型太陽電池用基板、その一部から形成される両面電極型太陽電池セル、および、両面電極型太陽電池セルの製造方法 |
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2013
- 2013-09-25 JP JP2013199043A patent/JP6399738B2/ja not_active Expired - Fee Related
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JP2015065350A (ja) | 2015-04-09 |
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