JP7310571B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP7310571B2 JP7310571B2 JP2019215692A JP2019215692A JP7310571B2 JP 7310571 B2 JP7310571 B2 JP 7310571B2 JP 2019215692 A JP2019215692 A JP 2019215692A JP 2019215692 A JP2019215692 A JP 2019215692A JP 7310571 B2 JP7310571 B2 JP 7310571B2
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- JP
- Japan
- Prior art keywords
- region
- semiconductor element
- electrode
- conductor plate
- solder layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
12:半導体素子
12a:上面
12b、12c:素子電極
14:導体スペーサ
14a:上面
14b:下面
16、18:導体板
20:封止体
22、24、26:はんだ層
A1:第1領域
A2:第2領域
Ab:接合領域
Ae:電極領域
d1:第1方向
d2:第2方向
W1:第1領域の幅寸法
W2:第2領域の幅寸法
Claims (1)
- 上面に電極を有する半導体素子と、
下面が前記電極にはんだ層を介して接合された導体板と、
を備え、
前記半導体素子の前記上面は、前記電極が露出する電極領域と、前記電極領域を分断しながら第1方向に沿って延びる第1領域とを有し、前記第1領域は前記電極領域よりもはんだ濡れ性が低く、
前記導体板の前記下面は、金属めっき膜で被覆されているとともに、前記電極領域に前記はんだ層を介して接合された接合領域と、前記金属めっき膜を構成する金属の酸化膜で被覆されているとともに、前記接合領域を分断しながら前記第1方向に沿って延びる第2領域とを有し、前記第2領域は前記接合領域よりもはんだ濡れ性が低く、
前記第1領域と前記第2領域とは互いに対向し、それらの間で前記はんだ層が分断されており、
前記第1方向に垂直な第2方向において、前記第2領域の寸法は、前記第1領域の寸法よりも大きい、
半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019215692A JP7310571B2 (ja) | 2019-11-28 | 2019-11-28 | 半導体装置 |
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JP2019215692A JP7310571B2 (ja) | 2019-11-28 | 2019-11-28 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2021086958A JP2021086958A (ja) | 2021-06-03 |
JP7310571B2 true JP7310571B2 (ja) | 2023-07-19 |
Family
ID=76088424
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2019215692A Active JP7310571B2 (ja) | 2019-11-28 | 2019-11-28 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP7310571B2 (ja) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006203096A (ja) | 2005-01-24 | 2006-08-03 | Matsushita Electric Ind Co Ltd | 実装体およびその製造方法 |
JP2009200250A (ja) | 2008-02-21 | 2009-09-03 | Nec Corp | 半導体素子の実装構造 |
JP2014212265A (ja) | 2013-04-19 | 2014-11-13 | 新電元工業株式会社 | 半導体装置およびその製造方法 |
JP2015176871A (ja) | 2014-03-12 | 2015-10-05 | 株式会社東芝 | 半導体装置及びその製造方法 |
-
2019
- 2019-11-28 JP JP2019215692A patent/JP7310571B2/ja active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006203096A (ja) | 2005-01-24 | 2006-08-03 | Matsushita Electric Ind Co Ltd | 実装体およびその製造方法 |
JP2009200250A (ja) | 2008-02-21 | 2009-09-03 | Nec Corp | 半導体素子の実装構造 |
JP2014212265A (ja) | 2013-04-19 | 2014-11-13 | 新電元工業株式会社 | 半導体装置およびその製造方法 |
JP2015176871A (ja) | 2014-03-12 | 2015-10-05 | 株式会社東芝 | 半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
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JP2021086958A (ja) | 2021-06-03 |
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