FR2978864B1 - Procede de correction de desalignement de positions sur une premiere plaque collee sur une deuxieme plaque - Google Patents

Procede de correction de desalignement de positions sur une premiere plaque collee sur une deuxieme plaque

Info

Publication number
FR2978864B1
FR2978864B1 FR1157069A FR1157069A FR2978864B1 FR 2978864 B1 FR2978864 B1 FR 2978864B1 FR 1157069 A FR1157069 A FR 1157069A FR 1157069 A FR1157069 A FR 1157069A FR 2978864 B1 FR2978864 B1 FR 2978864B1
Authority
FR
France
Prior art keywords
plate
desalignment
glue
correcting positions
correcting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1157069A
Other languages
English (en)
Other versions
FR2978864A1 (fr
Inventor
Arnaud Castex
Alexandre Barthelemy
Marcel Broekaart
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR1157069A priority Critical patent/FR2978864B1/fr
Priority to PCT/IB2012/001404 priority patent/WO2013017924A2/fr
Priority to TW101127822A priority patent/TW201316389A/zh
Publication of FR2978864A1 publication Critical patent/FR2978864A1/fr
Application granted granted Critical
Publication of FR2978864B1 publication Critical patent/FR2978864B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7003—Alignment type or strategy, e.g. leveling, global alignment
    • G03F9/7007—Alignment other than original with workpiece
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7003—Alignment type or strategy, e.g. leveling, global alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
FR1157069A 2011-08-02 2011-08-02 Procede de correction de desalignement de positions sur une premiere plaque collee sur une deuxieme plaque Expired - Fee Related FR2978864B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR1157069A FR2978864B1 (fr) 2011-08-02 2011-08-02 Procede de correction de desalignement de positions sur une premiere plaque collee sur une deuxieme plaque
PCT/IB2012/001404 WO2013017924A2 (fr) 2011-08-02 2012-07-18 Procédé pour corriger un mauvais alignement de positions sur une première tranche liée à une seconde tranche
TW101127822A TW201316389A (zh) 2011-08-02 2012-08-01 用以校正結合至第二晶圓之第一晶圓上之位置偏差之方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1157069A FR2978864B1 (fr) 2011-08-02 2011-08-02 Procede de correction de desalignement de positions sur une premiere plaque collee sur une deuxieme plaque

Publications (2)

Publication Number Publication Date
FR2978864A1 FR2978864A1 (fr) 2013-02-08
FR2978864B1 true FR2978864B1 (fr) 2014-02-07

Family

ID=46614560

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1157069A Expired - Fee Related FR2978864B1 (fr) 2011-08-02 2011-08-02 Procede de correction de desalignement de positions sur une premiere plaque collee sur une deuxieme plaque

Country Status (3)

Country Link
FR (1) FR2978864B1 (fr)
TW (1) TW201316389A (fr)
WO (1) WO2013017924A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5763116B2 (ja) * 2013-03-25 2015-08-12 株式会社東芝 半導体装置の製造方法
WO2016091529A1 (fr) * 2014-12-12 2016-06-16 Asml Netherlands B.V. Procédés et appareil pour calculer des paramètres de modèle de substrat et commander un traitement lithographique

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100601120B1 (ko) * 2001-05-25 2006-07-19 캘리포니아 인스티튜트 오브 테크놀로지 체적력의 효과를 포함하도록 적층형 및 경사형 구조의대변형 및 응력을 결정하는 방법 및 시스템
US20080182344A1 (en) * 2007-01-30 2008-07-31 Steffen Mueller Method and system for determining deformations on a substrate
NL2003118A1 (nl) * 2008-07-14 2010-01-18 Asml Netherlands Bv Alignment system, lithographic system and method.
FR2943177B1 (fr) * 2009-03-12 2011-05-06 Soitec Silicon On Insulator Procede de fabrication d'une structure multicouche avec report de couche circuit
FR2955654B1 (fr) * 2010-01-25 2012-03-30 Soitec Silicon Insulator Technologies Systeme et procede d'evaluation de deformations inhomogenes dans des plaques multicouches

Also Published As

Publication number Publication date
WO2013017924A3 (fr) 2013-05-23
TW201316389A (zh) 2013-04-16
FR2978864A1 (fr) 2013-02-08
WO2013017924A2 (fr) 2013-02-07

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20150430