JP5627835B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP5627835B2 JP5627835B2 JP2007298361A JP2007298361A JP5627835B2 JP 5627835 B2 JP5627835 B2 JP 5627835B2 JP 2007298361 A JP2007298361 A JP 2007298361A JP 2007298361 A JP2007298361 A JP 2007298361A JP 5627835 B2 JP5627835 B2 JP 5627835B2
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Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007298361A JP5627835B2 (ja) | 2007-11-16 | 2007-11-16 | 半導体装置および半導体装置の製造方法 |
| US12/272,001 US9035455B2 (en) | 2007-11-16 | 2008-11-17 | Semiconductor device |
| US14/690,982 US9437544B2 (en) | 2007-11-16 | 2015-04-20 | Semiconductor device |
| US15/236,016 US9607957B2 (en) | 2007-11-16 | 2016-08-12 | Semiconductor device |
| US15/451,770 US9941231B2 (en) | 2007-11-16 | 2017-03-07 | Semiconductor device |
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| JP2007298361A JP5627835B2 (ja) | 2007-11-16 | 2007-11-16 | 半導体装置および半導体装置の製造方法 |
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| JP2013183162A Division JP5891211B2 (ja) | 2013-09-04 | 2013-09-04 | 半導体装置 |
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| JP5627835B2 (ja) * | 2007-11-16 | 2014-11-19 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
| US8592995B2 (en) * | 2009-07-02 | 2013-11-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for adhesion of intermetallic compound (IMC) on Cu pillar bump |
| JP2011222738A (ja) * | 2010-04-09 | 2011-11-04 | Renesas Electronics Corp | 半導体装置の製造方法 |
| US9219044B2 (en) * | 2013-11-18 | 2015-12-22 | Applied Materials, Inc. | Patterned photoresist to attach a carrier wafer to a silicon device wafer |
| KR102410018B1 (ko) * | 2015-09-18 | 2022-06-16 | 삼성전자주식회사 | 반도체 패키지 |
| US10903151B2 (en) * | 2018-05-23 | 2021-01-26 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
| JP7319808B2 (ja) * | 2019-03-29 | 2023-08-02 | ローム株式会社 | 半導体装置および半導体パッケージ |
| US11393780B2 (en) | 2019-07-26 | 2022-07-19 | Sandisk Technologies Llc | Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same |
| US11515273B2 (en) | 2019-07-26 | 2022-11-29 | Sandisk Technologies Llc | Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same |
| US11139272B2 (en) | 2019-07-26 | 2021-10-05 | Sandisk Technologies Llc | Bonded assembly containing oxidation barriers and/or adhesion enhancers and methods of forming the same |
Family Cites Families (46)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54111761A (en) * | 1978-02-22 | 1979-09-01 | Hitachi Ltd | Electrode construction of semiconductor device |
| JPH01278751A (ja) * | 1988-05-02 | 1989-11-09 | Matsushita Electron Corp | 半導体装置 |
| KR100199258B1 (ko) * | 1990-02-09 | 1999-06-15 | 가나이 쓰도무 | 반도체집적회로장치 |
| US5508561A (en) * | 1993-11-15 | 1996-04-16 | Nec Corporation | Apparatus for forming a double-bump structure used for flip-chip mounting |
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| US6111317A (en) * | 1996-01-18 | 2000-08-29 | Kabushiki Kaisha Toshiba | Flip-chip connection type semiconductor integrated circuit device |
| JP3321351B2 (ja) * | 1996-01-18 | 2002-09-03 | 東芝マイクロエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
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| US6436300B2 (en) * | 1998-07-30 | 2002-08-20 | Motorola, Inc. | Method of manufacturing electronic components |
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| US6479900B1 (en) * | 1998-12-22 | 2002-11-12 | Sanyo Electric Co., Ltd. | Semiconductor device and method of manufacturing the same |
| JP4024958B2 (ja) * | 1999-03-15 | 2007-12-19 | 株式会社ルネサステクノロジ | 半導体装置および半導体実装構造体 |
| US6133136A (en) * | 1999-05-19 | 2000-10-17 | International Business Machines Corporation | Robust interconnect structure |
| US6362087B1 (en) * | 2000-05-05 | 2002-03-26 | Aptos Corporation | Method for fabricating a microelectronic fabrication having formed therein a redistribution structure |
| US6293457B1 (en) * | 2000-06-08 | 2001-09-25 | International Business Machines Corporation | Integrated method for etching of BLM titanium-tungsten alloys for CMOS devices with copper metallization |
| TW517334B (en) * | 2000-12-08 | 2003-01-11 | Nec Corp | Method of forming barrier layers for solder bumps |
| US6426556B1 (en) * | 2001-01-16 | 2002-07-30 | Megic Corporation | Reliable metal bumps on top of I/O pads with test probe marks |
| CN100382262C (zh) * | 2002-06-21 | 2008-04-16 | 富士通株式会社 | 半导体装置及其制造方法 |
| US7547623B2 (en) * | 2002-06-25 | 2009-06-16 | Unitive International Limited | Methods of forming lead free solder bumps |
| JP2004031651A (ja) * | 2002-06-26 | 2004-01-29 | Sony Corp | 素子実装基板及びその製造方法 |
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| TWI281718B (en) * | 2002-09-10 | 2007-05-21 | Advanced Semiconductor Eng | Bump and process thereof |
| JP2004152953A (ja) * | 2002-10-30 | 2004-05-27 | Citizen Watch Co Ltd | 半導体装置及びその製造方法 |
| JP2004281491A (ja) * | 2003-03-13 | 2004-10-07 | Toshiba Corp | 半導体装置及びその製造方法 |
| JP2005085857A (ja) * | 2003-09-05 | 2005-03-31 | Denso Corp | バンプを用いた電極構造 |
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| US20050092611A1 (en) * | 2003-11-03 | 2005-05-05 | Semitool, Inc. | Bath and method for high rate copper deposition |
| DE10355953B4 (de) * | 2003-11-29 | 2005-10-20 | Infineon Technologies Ag | Verfahren zum Galvanisieren und Kontaktvorsprungsanordnung |
| JP2005166959A (ja) * | 2003-12-03 | 2005-06-23 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
| JP2005175128A (ja) | 2003-12-10 | 2005-06-30 | Fujitsu Ltd | 半導体装置及びその製造方法 |
| JP4049127B2 (ja) | 2004-06-11 | 2008-02-20 | ヤマハ株式会社 | 半導体装置の製造方法 |
| US7830011B2 (en) | 2004-03-15 | 2010-11-09 | Yamaha Corporation | Semiconductor element and wafer level chip size package therefor |
| JP2006100552A (ja) * | 2004-09-29 | 2006-04-13 | Rohm Co Ltd | 配線基板および半導体装置 |
| JP2006278551A (ja) | 2005-03-28 | 2006-10-12 | Fujitsu Ltd | 半導体装置及びその製造方法 |
| TWI288447B (en) * | 2005-04-12 | 2007-10-11 | Siliconware Precision Industries Co Ltd | Conductive bump structure for semiconductor device and fabrication method thereof |
| JP2007019473A (ja) * | 2005-06-10 | 2007-01-25 | Nec Electronics Corp | 半導体装置 |
| US7622309B2 (en) * | 2005-06-28 | 2009-11-24 | Freescale Semiconductor, Inc. | Mechanical integrity evaluation of low-k devices with bump shear |
| US7947978B2 (en) * | 2005-12-05 | 2011-05-24 | Megica Corporation | Semiconductor chip with bond area |
| JP4247690B2 (ja) * | 2006-06-15 | 2009-04-02 | ソニー株式会社 | 電子部品及その製造方法 |
| JP4354469B2 (ja) * | 2006-08-11 | 2009-10-28 | シャープ株式会社 | 半導体装置および半導体装置の製造方法 |
| JP5627835B2 (ja) * | 2007-11-16 | 2014-11-19 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
| US7985671B2 (en) * | 2008-12-29 | 2011-07-26 | International Business Machines Corporation | Structures and methods for improving solder bump connections in semiconductor devices |
| US7989356B2 (en) * | 2009-03-24 | 2011-08-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming enhanced UBM structure for improving solder joint reliability |
| US8669137B2 (en) * | 2011-04-01 | 2014-03-11 | International Business Machines Corporation | Copper post solder bumps on substrate |
| US9087701B2 (en) * | 2011-04-30 | 2015-07-21 | Stats Chippac, Ltd. | Semiconductor device and method of embedding TSV semiconductor die within substrate for vertical interconnect in POP |
| US8643150B1 (en) * | 2012-02-15 | 2014-02-04 | Maxim Integrated Products, Inc. | Wafer-level package device having solder bump assemblies that include an inner pillar structure |
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| JP2009124042A (ja) | 2009-06-04 |
| US20090127709A1 (en) | 2009-05-21 |
| US9607957B2 (en) | 2017-03-28 |
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