JP5608605B2 - 配線基板の製造方法 - Google Patents

配線基板の製造方法 Download PDF

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Publication number
JP5608605B2
JP5608605B2 JP2011117724A JP2011117724A JP5608605B2 JP 5608605 B2 JP5608605 B2 JP 5608605B2 JP 2011117724 A JP2011117724 A JP 2011117724A JP 2011117724 A JP2011117724 A JP 2011117724A JP 5608605 B2 JP5608605 B2 JP 5608605B2
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JP
Japan
Prior art keywords
hole
layer
substrate
wiring board
seed layer
Prior art date
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Expired - Fee Related
Application number
JP2011117724A
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English (en)
Japanese (ja)
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JP2012114400A5 (enExample
JP2012114400A (ja
Inventor
秀明 坂口
健 宮入
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2011117724A priority Critical patent/JP5608605B2/ja
Publication of JP2012114400A publication Critical patent/JP2012114400A/ja
Publication of JP2012114400A5 publication Critical patent/JP2012114400A5/ja
Application granted granted Critical
Publication of JP5608605B2 publication Critical patent/JP5608605B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
JP2011117724A 2010-11-05 2011-05-26 配線基板の製造方法 Expired - Fee Related JP5608605B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2011117724A JP5608605B2 (ja) 2010-11-05 2011-05-26 配線基板の製造方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2010248328 2010-11-05
JP2010248328 2010-11-05
JP2011117724A JP5608605B2 (ja) 2010-11-05 2011-05-26 配線基板の製造方法

Publications (3)

Publication Number Publication Date
JP2012114400A JP2012114400A (ja) 2012-06-14
JP2012114400A5 JP2012114400A5 (enExample) 2014-04-10
JP5608605B2 true JP5608605B2 (ja) 2014-10-15

Family

ID=46498251

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011117724A Expired - Fee Related JP5608605B2 (ja) 2010-11-05 2011-05-26 配線基板の製造方法

Country Status (1)

Country Link
JP (1) JP5608605B2 (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12087679B2 (en) 2019-11-27 2024-09-10 Applied Materials, Inc. Package core assembly and fabrication methods
TWI872964B (zh) * 2019-05-10 2025-02-11 美商應用材料股份有限公司 用於異質封裝整合的重構基板結構與製造方法
US12388049B2 (en) 2020-03-10 2025-08-12 Applied Materials, Inc. High connectivity device stacking

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014069662A1 (ja) 2012-11-05 2014-05-08 大日本印刷株式会社 配線構造体
JP2014236102A (ja) * 2013-05-31 2014-12-15 凸版印刷株式会社 貫通電極付き配線基板、その製造方法及び半導体装置
KR20150049515A (ko) * 2013-10-30 2015-05-08 삼성전기주식회사 인쇄회로기판 및 그 제조 방법
JP2015198093A (ja) * 2014-03-31 2015-11-09 凸版印刷株式会社 インターポーザー、半導体装置、インターポーザーの製造方法、半導体装置の製造方法
TWI670803B (zh) * 2014-03-31 2019-09-01 日商凸版印刷股份有限公司 中介層、半導體裝置、中介層的製造方法及半導體裝置的製造方法
JP6539992B2 (ja) * 2014-11-14 2019-07-10 凸版印刷株式会社 配線回路基板、半導体装置、配線回路基板の製造方法、半導体装置の製造方法
CN105657987B (zh) * 2014-12-03 2019-05-21 北大方正集团有限公司 板材塞孔方法和电路板
JP2017107934A (ja) * 2015-12-08 2017-06-15 富士通株式会社 回路基板、電子機器、及び回路基板の製造方法
KR102039887B1 (ko) * 2017-12-13 2019-12-05 엘비세미콘 주식회사 양면 도금 공정을 이용한 반도체 패키지의 제조방법
JP6828733B2 (ja) * 2018-12-25 2021-02-10 凸版印刷株式会社 インターポーザー、半導体装置、インターポーザーの製造方法、半導体装置の製造方法
KR102442256B1 (ko) * 2020-11-05 2022-09-08 성균관대학교산학협력단 보이드가 없는 실리콘 관통전극의 제조방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63232487A (ja) * 1987-03-20 1988-09-28 日本電気株式会社 印刷配線板の製造方法
JPH0423488A (ja) * 1990-05-18 1992-01-27 Hitachi Ltd プリント基板の製造方法
JPH06260757A (ja) * 1993-03-05 1994-09-16 Meikoo:Kk プリント回路板の製造方法
JP2006237431A (ja) * 2005-02-28 2006-09-07 New Japan Radio Co Ltd セラミック基板の製造方法
JP2007095743A (ja) * 2005-09-27 2007-04-12 Matsushita Electric Works Ltd 貫通孔配線及びその製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI872964B (zh) * 2019-05-10 2025-02-11 美商應用材料股份有限公司 用於異質封裝整合的重構基板結構與製造方法
US12354968B2 (en) 2019-05-10 2025-07-08 Applied Materials, Inc. Reconstituted substrate structure and fabrication methods for heterogeneous packaging integration
TWI895066B (zh) * 2019-05-10 2025-08-21 美商應用材料股份有限公司 封裝結構及製作方法
US12087679B2 (en) 2019-11-27 2024-09-10 Applied Materials, Inc. Package core assembly and fabrication methods
US12374611B2 (en) 2019-11-27 2025-07-29 Applied Materials, Inc. Package core assembly and fabrication methods
US12388049B2 (en) 2020-03-10 2025-08-12 Applied Materials, Inc. High connectivity device stacking

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Publication number Publication date
JP2012114400A (ja) 2012-06-14

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