JP5580933B2 - ダイ間ボンディングをテストするための集積回路および方法 - Google Patents
ダイ間ボンディングをテストするための集積回路および方法 Download PDFInfo
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Description
この明細書の中で開示される1以上の実施の形態は、集積回路(IC)に関する。より特定的には、1以上の実施の形態は、複数のダイを含むICをテストすることに関する。
集積回路(IC)を製造するときに、欠陥がダイに生じるであろう確率は、一般的に、そのICを実現するために用いられるダイのサイズが増大するに従って増大する。IC内の製造欠陥の発生は、「フォールト(故障)」とも呼ばれるが、結果として、ICの動作可能性の減少、あるいは完全な故障をもたらし得る。このような理由により、単一のモノリシックダイとは対照的に、マルチダイICの形態でICを実現することがコスト的により効率的であり得る。
この明細書の中で開示される1以上の実施の形態は、集積回路(IC)に関し、より特定的には、複数のダイを含むICをテストすることに関する。1つの実施の形態に従うと、集積回路は、第1のダイと、第2のダイとを備え、第1のダイは、第2のダイの上部に積層される。集積回路は、複数のダイ間接続部と、第2のダイの上部に配置された第1のプローブパッドと、第2のダイの上部に配置された第2のプローブパッドとをさらに備える。各々のダイ間接続部は、第1のダイと第2のダイとの間に配置された、第1のダイを第2のダイに結合するマイクロバンプを含む。第1のプローブパッドは、第1のマイクロバンプに結合され、第2のプローブパッドは、第2のマイクロバンプに結合され、第1のダイは、第1のマイクロバンプを第2のマイクロバンプに結合する内部接続を確立するように構成される。
明細書は新規であるとみなされる1以上の実施の形態の特徴を定義する請求項で結論づけられるが、1以上の実施の形態は図面とともに明細書を考慮するためのより良い理解となるであろう。求められるように、1以上の実施の形態はこの明細書の中で開示される。しかしながら、請求項は、発明の範囲を提供するということが理解されるべきである。
Claims (13)
- 集積回路であって、
コンフィグレーションメモリセルを含む第1のダイと、
第2のダイとを備え、前記第1のダイは、前記第2のダイに積層され、
前記第2のダイは、複数のダイ間ワイヤを含むシリコンインターポーザを含み、
前記集積回路は、
前記第2のダイに積層された第3のダイをさらに備え、前記第3のダイは、コンフィグレーションメモリセルを含み、
前記第1のダイと前記第3のダイとは、前記第2のダイに半永久的に結合され、
前記集積回路は、
複数のダイ間接続部をさらに備え、各々のダイ間接続部は、前記第1のダイと前記第2のダイとの間に配置されたバンプ、または、前記第3のダイと前記第2のダイとの間に配置されたバンプを含み、前記複数のダイ間接続部は、前記第1のダイを前記第2のダイに結合するとともに、前記第3のダイを前記第2のダイに結合し、
選択されたダイ間ワイヤは、前記第1のダイと前記第2のダイとの間にある第1のダイ間接続部を、前記第3のダイと前記第2のダイとの間にある第2のダイ間接続部に結合させ、
前記集積回路は、
前記第2のダイに配置された第1のプローブパッドをさらに備え、前記第1のプローブパッドは、前記第1のダイと前記第2のダイとの間にある第1のバンプに結合され、
前記集積回路は、
前記第2のダイに配置された第2のプローブパッドをさらに備え、前記第2のプローブパッドは、前記第3のダイと前記第2のダイとの間にある第2のバンプに結合され、
前記第1のダイと前記第3のダイとの各々は、プログラム可能に前記ダイ間接続部に結合された内部接続部を含み、前記第1のダイの前記コンフィグレーションメモリセルおよび前記第3のダイの前記コンフィグレーションメモリセルは、前記第1のバンプを前記第2のバンプに結合する、前記第1のダイの中の内部接続部および前記第3のダイの中の内部接続部を確立するように、コンフィグレーションデータにより構成され、
前記プログラム可能な前記内部接続部は、前記第1のダイと前記第3のダイとにおいて、ユーザ設計での動作をプログラム可能であり、
前記第1のバンプへの前記第1のプローブパッドの前記結合部と、前記第2のバンプへの前記第2のプローブパッドの前記結合部と、前記第1のダイの中の前記内部接続部と、前記第3のダイの中の前記内部接続部とは、前記第1のプローブパッドから前記第2のプローブパッドへと信号を伝搬するように構成される、集積回路。 - 前記第2のダイは、前記第1のダイを前記第1のプローブパッドまたは前記第2のプローブパッドのうちの少なくとも1つに結合する、少なくとも1つの受動金属層からなる、請求項1に記載の集積回路。
- 前記第2のダイは、前記第1のダイを前記第1のプローブパッドまたは前記第2のプローブパッドのうちの少なくとも1つに選択的に結合する、1以上のスイッチを含む能動構造体である、請求項1に記載の集積回路。
- 前記複数のダイ間接続部のうちの少なくとも1つは、前記第2のダイ内にスルーシリコンビアを備え、
前記スルーシリコンビアの第1の端部は、前記第1のバンプに結合されて、前記スルーシリコンビアの第2の端部は、前記第2のダイを通って、前記第1および第2のプローブパッドがその上に配置されている面とは反対側にある前記第2のダイの表面へと延在し、
前記第1のプローブパッドは、前記スルーシリコンビアを用いて前記第1のバンプへと結合される、請求項1から3のいずれか1項に記載の集積回路。 - 請求項1から4のいずれか1項に記載の集積回路をテストする方法であって、
前記複数のダイ間接続部のうちの1つをテストするステップと、
前記ダイ間接続部の前記テストするステップの間に故障が生じるか否かを検出するステップと、
故障が生じたことを検出したことに応答して、前記集積回路を、故障のあるダイ間接続部を含むとして指定するステップとを備える、方法。 - 前記方法は、
前記集積回路が、故障のあるダイ間接続部を含むとして指定された場合に、前記ダイ間接続部を再処理するステップをさらに備える、請求項5に記載の方法。 - 請求項1から4のいずれか1項に記載の集積回路をテストする方法であって、
前記複数のダイ間接続部の各々をテストするステップと、
前記ダイ間接続部の前記テストするステップの間に故障が生じるか否かを検出するステップと、
故障が生じていないことを検出したことに応答して、前記第1のダイを、前記第2のダイに永久的に結合させるステップとを備える、方法。 - 故障が生じるか否かを検出するステップは、
テスト信号が前記第1のプローブパッドから前記第2のプローブパッドへと伝搬するか否かを判断するステップを備える、請求項5から7のいずれか1項に記載の方法。 - 前記第2のダイは、前記第2のダイを通って延在する第1のスルーシリコンビアを備え、前記第1のスルーシリコンビアは、第1の端部において前記第1のバンプに結合されるとともに、第2の端部において第1のパッケージバンプに結合されて、
前記第2のダイは、さらに、前記第2のダイを通って延在する第2のスルーシリコンビアを備え、前記第2のスルーシリコンビアは、第1の端部において前記第2のバンプに結合されるとともに、第2の端部において第2のパッケージバンプに結合される、請求項1から4のいずれか1項に記載の集積回路。 - 請求項9に記載の集積回路をテストする方法であって、
前記複数のダイ間接続部のうちの1つをテストするステップと、
前記ダイ間接続部の前記テストするステップの間に故障が生じるか否かを検出するステップと、
故障が生じたことを検出したことに応答して、前記集積回路を、故障のあるダイ間接続部を含むとして指定するステップとを備える、方法。 - 前記方法は、
前記集積回路が、故障のあるダイ間接続部を含むとして指定された場合に、前記ダイ間接続部を再処理するステップをさらに備える、請求項10に記載の方法。 - 請求項9に記載の集積回路をテストする方法であって、
前記複数のダイ間接続部の各々をテストするステップと、
前記ダイ間接続部の前記テストするステップの間に故障が生じるか否かを検出するステップと、
故障が生じていないことを検出したことに応答して、前記第1のダイを、前記第2のダイに永久的に結合させるステップとを備える、方法。 - 故障が生じるか否かを検出するステップは、
前記第1のパッケージバンプに与えられたテスト信号が、前記第2のパッケージバンプへと伝搬するか否かを判断するステップを備える、請求項10から12のいずれか1項に記載の方法。
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