JP5566540B2 - 電力用半導体装置 - Google Patents
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Description
<構成>
実施の形態1では、電流検出素子(電流センサ)を内蔵した電力用半導体装置の一例として、縦型のn型チャネル炭化珪素MOSFETを用いて説明する。また半導体の導電型について、第1導電型をn型、第2導電型をp型として説明するが、その逆であっても構わない。
次に、図4〜図8を用いて、実施の形態1の電力用半導体装置の製造方法を説明する。図4〜図8は、実施の形態1の電力用半導体装置の製造工程における電力用半導体装置の一部を模式的に表した断面図である。
次に、本実施の形態の電力用半導体装置の構成を電気回路的に説明する。図9は、実施の形態1の電力用半導体装置の等価回路図である。図2で説明したように、センスパッド13にMOSFET1が繋がる他、センスパッド13とゲートパッド11との間にキャパシタ2が繋がり、センスパッド13とドレイン電極14との間にpnダイオード3が繋がる構成となる。
実施の形態1の電力用半導体装置は、第1導電型の半導体基板20と、半導体基板20の第1主面に形成された第1導電型のドリフト層21と、ドリフト層21の表面に選択的に形成された、第2導電型の複数のメインセルウェル及び第2導電型の複数のセンスウェル41と、ドリフト層21の表面において、複数のセンスウェル41を囲んで形成された第2導電型のセンス外周ウェル42と、メインセルウェルの表面に選択的に形成された第1導電型のメインセルソース領域と、メインセルソース領域とドリフト層21との間のメインセルウェル表面に形成された第1のチャネル領域と、センスウェル41の表面に選択的に形成された第1導電型のセンスソース領域81と、センスソース領域81とドリフト層21との間のセンスウェル41表面に形成された第2のチャネル領域と、センス外周ウェル42の表面に選択的に形成された第1導電型のキャパシタ下部電極領域82と、第1、第2のチャネル領域上及びセンス外周ウェル42上に形成されたゲート絶縁膜30と、ゲート絶縁膜30上に形成されたゲート電極50と、メインセルウェル及びメインセルソース領域に電気的に接続するソースパッド10と、センスウェル41及びセンスソース領域81、並びにセンス外周ウェル42及びキャパシタ下部電極領域82に電気的に接続するセンスパッド13と、半導体基板20の第2主面に形成されたドレイン電極14とを備える。センス外周ウェル42、キャパシタ下部電極領域82、ゲート絶縁膜30、ゲート電極50がAC的に見て入力抵抗の低いキャパシタ2として動作するので、セル数を調整してキャパシタ2の容量を大きくすることによって、静電気が加わった際のゲート絶縁膜30における電界を緩和し、絶縁破壊を抑制することが出来る。
図10は、実施の形態2の電力用半導体装置の構成を示す断面図である。
実施の形態2の電力用半導体装置において、MOSFET1を構成するセンスウェル41を囲むセンス外周ウェルは、ドリフト層21の表面から所定の深さの領域で連続的に形成されたセンス外周ウェル44(第1センス外周ウェル)と、センス外周ウェル44からドリフト層21表面にかけて、コンタクト領域93及びキャパシタ下部電極領域82に対応して島状に形成されたセンスウェル41(第2センス外周ウェル)とを備える。これにより、キャパシタ2とMOSFET1とは、ドリフト層21とセンス外周ウェル領域44の深さ方向の境界からゲート絶縁膜下にかけての構造が同じになるため、静電気がゲート電極50に印加した場合、MOSFET1、キャパシタ6のゲート電極50の電位上昇は同じものとなる。よって、キャパシタ2の容量を調整することによってゲート電界を緩和し、ゲート絶縁膜30の破壊を抑制することができる。
実施の形態1の電力用半導体装置ではキャパシタ下部電極領域82を複数形成したが、実施の形態3の電力用半導体装置では、センスパッド13とのコンタクト数はそのままに、複数のキャパシタ下部電極領域82を全て繋げた一続きのキャパシタ下部電極領域83を形成する。
実施の形態3の電力用半導体装置は、キャパシタ下部電極領域83上に選択的に形成された、ゲート絶縁膜30よりも厚いフィールド絶縁膜31をさらに備え、ゲート電極50はフィールド絶縁膜31上にも形成されるので、ゲート電極50、フィールド絶縁膜31、キャパシタ下部電極領域83、センス外周ウェル42により構成されるキャパシタ7の入力抵抗値は極めて低い値となる。よって、ゲート電極50に静電気が印加した際にMOSFET1のゲート絶縁膜30にかかる電界を緩和し、絶縁破壊を抑制することが出来る。
Claims (4)
- 第1導電型の炭化珪素半導体基板(20)の第1主面に形成された第1導電型のドリフト層(21)と、
前記ドリフト層(21)の表面に選択的に形成された、第2導電型の複数のメインセルウェル及び第2導電型の複数のセンスウェル(41)と、
前記ドリフト層(21)の表面において、前記複数のセンスウェル(41)を囲んで形成された第2導電型のセンス外周ウェル(42)と、
前記メインセルウェルの表面に選択的に形成された第1導電型のメインセルソース領域と、
前記メインセルソース領域と前記ドリフト層(21)との間の前記メインセルウェル表面に形成された第1のチャネル領域と、
前記センスウェル(41)の表面に選択的に形成された第1導電型のセンスソース領域(81)と、
前記センスソース領域(81)の内部に、前記センスソース領域(81)の表面から前記センスウェル(41)まで貫通する第2導電型の第1コンタクト領域(91)と、
前記センスソース領域(81)と前記ドリフト層(21)との間の前記センスウェル(41)表面に形成された第2のチャネル領域と、
前記センス外周ウェル(42)の表面かつ外周縁及び内周縁に選択的に形成され、前記センスパッド(13)と電気的に接続する複数の第2導電型の第2コンタクト領域(93)と、
前記センス外周ウェル(42)の表面かつ外周縁及び内周縁に囲まれた領域に選択的に形成された第1導電型のキャパシタ下部電極領域(82)と、
前記キャパシタ下部電極領域(82)の内部に、前記キャパシタ下部電極領域(82)の表面から前記センス外周ウェル(41)まで貫通する第2導電型の第3コンタクト領域(92)と、
前記第1及び第2のチャネル領域上及び前記センス外周ウェル(42)上に形成されたゲート絶縁膜(30)と、
前記ゲート絶縁膜(30)上に形成されたゲート電極(50)と、
前記メインセルウェル及び前記メインセルソース領域に電気的に接続するソースパッド(10)と、
前記センスウェル及び前記センスソース領域、並びに前記センス外周ウェル(42)及び前記キャパシタ下部電極領域(82)に電気的に接続するセンスパッド(13)と、
前記半導体基板の第2主面に形成されたドレイン電極(14)とを備える、
電力用半導体装置。 - 前記センスウェル(41)と前記センスソース領域(81)と第2のチャネル領域とゲート電極(50)と前記第1コンタクト領域(91)とで構成されるMOSFET(1)と、
前記センス外周ウェル(42)と前記キャパシタ下部電極領域(82)とゲート電極(50)と前記第3コンタクト領域(92)とで構成されるキャパシタ(2)とをさらに備え、
前記MOSFET(1)と前記キャパシタ(2)は、前記センスウェル(41)と前記センス外周ウェル(42)以外は同一の構成を有する、
請求項1に記載の電力用半導体装置。 - 前記センスウェル(41)と前記センス外周ウェル(42)は、同時に形成されることを特徴とする、
請求項1又は2に記載の電力用半導体装置。 - 前記センス外周ウェル(42)は、
前記ドリフト層(21)の表面から所定の深さの領域で連続的に形成された第1センス外周ウェル(44)と、
前記第1センス外周ウェル(44)から前記ドリフト層(21)表面にかけて、前記コンタクト領域(93)及び前記キャパシタ下部電極領域(82)に対応して島状に形成された前記センスウェル(41)と同一の形状を有する第2センス外周ウェル(41)とで構成される、
請求項1〜3のいずれかに記載の電力用半導体装置。
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