JP2021044275A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2021044275A JP2021044275A JP2019162543A JP2019162543A JP2021044275A JP 2021044275 A JP2021044275 A JP 2021044275A JP 2019162543 A JP2019162543 A JP 2019162543A JP 2019162543 A JP2019162543 A JP 2019162543A JP 2021044275 A JP2021044275 A JP 2021044275A
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Abstract
Description
実施の形態1にかかる半導体装置は、シリコン(Si)よりもバンドギャップが広い半導体(ワイドバンドギャップ半導体とする)を用いて構成される。この実施の形態1にかかる半導体装置の構造について、ワイドバンドギャップ半導体として例えば炭化珪素(SiC)を用いた場合を例に説明する。図1は、実施の形態1にかかる炭化珪素半導体装置の構造を示す上面図である。図1には、半導体基板(半導体チップ)に配置された各素子の電極パッドおよび各領域のレイアウトを示す。
次に、実施の形態1にかかる炭化珪素半導体装置の製造方法について説明する。図3〜図8は、実施の形態にかかる炭化珪素半導体装置の製造途中の状態を示す断面図である。
次に、実施の形態2にかかる炭化珪素半導体装置の構造について説明する。図9は、実施の形態2にかかる炭化珪素半導体装置の構造を示す上面図である。実施の形態2にかかる炭化珪素半導体装置が実施の形態1にかかる炭化珪素半導体装置と異なる点は、活性領域150の第1ソース電極12aとソースリング領域170の第2ソース電極12bを接続する短絡電極500が設けられている点である。
次に、実施の形態3にかかる炭化珪素半導体装置の構造について説明する。図11は、実施の形態3にかかる炭化珪素半導体装置の構造を示す上面図である。実施の形態3にかかる炭化珪素半導体装置が実施の形態2にかかる炭化珪素半導体装置と異なる点は、活性領域150の第1ソース電極12aとソースリング領域170の第2ソース電極12bを接続する短絡電極500を、分断領域550を設けることなく設けている点である。
次に、実施の形態4にかかる炭化珪素半導体装置の構造について説明する。図13は、実施の形態4にかかる炭化珪素半導体装置の構造を示す上面図である。実施の形態4にかかる炭化珪素半導体装置が実施の形態2にかかる炭化珪素半導体装置と異なる点は、活性領域150の第1ソース電極12aとソースリング領域170の第2ソース電極12bを接続する短絡電極500を第1外部電極ピン26aおよび第2外部電極ピン26b上に設けている点である。
次に、実施の形態5にかかる炭化珪素半導体装置の構造について説明する。図15は、実施の形態5にかかる炭化珪素半導体装置の構造を示す断面図である。上面図は、実施の形態1と同様であるため、記載を省略する。実施の形態5にかかる炭化珪素半導体装置が実施の形態1〜4にかかる炭化珪素半導体装置と異なる点は、ソースリング領域170のn型炭化珪素エピタキシャル層2において、第2ソース電極12bと深さ方向に対向する位置に第1p+型ベース領域3を深く形成している点である。この深く形成した部分を、p+型領域(第2導電型の第2半導体領域)30と称する。
次に、実施の形態6にかかる炭化珪素半導体装置の構造について説明する。図18は、実施の形態6にかかる炭化珪素半導体装置の構造を示す断面図である。上面図は、実施の形態1と同様であるため、記載を省略する。実施の形態6にかかる炭化珪素半導体装置が実施の形態5にかかる炭化珪素半導体装置と異なる点は、ソースリング領域170の第2ソース電極12bが、トレンチ16内に設けられている点である。以下、活性領域150のトレンチ16を第1トレンチ(第1のトレンチ)16aと、ソースリング領域170のトレンチ16を第2トレンチ(第2のトレンチ)16bと称する。
次に、実施の形態7にかかる炭化珪素半導体装置の構造について説明する。図20は、実施の形態7にかかる炭化珪素半導体装置の構造を示す断面図である。上面図は、実施の形態1と同様であるため、記載を省略する。実施の形態7にかかる炭化珪素半導体装置が実施の形態1〜4にかかる炭化珪素半導体装置と異なる点は、ソースリング領域170のn型炭化珪素エピタキシャル層2と第1p+型ベース領域3との界面において、第2ソース電極12bと深さ方向に対向する位置にライフタイムキラー領域32を設けている点である。
次に、実施の形態8にかかる炭化珪素半導体装置の構造について説明する。図21は、実施の形態8にかかる炭化珪素半導体装置の構造を示す断面図である。上面図は、実施の形態1と同様であるため、記載を省略する。実施の形態8にかかる炭化珪素半導体装置が実施の形態7にかかる炭化珪素半導体装置と異なる点は、ソースリング領域170の第2ソース電極12bが、第2トレンチ16b内に設けられている点である。
2、1002 n型炭化珪素エピタキシャル層
2a 第1n型炭化珪素エピタキシャル層
2b 第2n型炭化珪素エピタキシャル層
3、1003 第1p+型ベース領域
3a 下部第1p+型ベース領域
3b 上部第1p+型ベース領域
4、1004 第2p+型ベース領域
5、1005 n型高濃度領域
5a 下部n型高濃度領域
5b 上部n型高濃度領域
6、1006 p型ベース層
7、1007 n+型ソース領域
8、1008 p++型コンタクト領域
9、1009 ゲート絶縁膜
10、1010 ゲート電極
10a 第1ゲート電極
10b 第2ゲート電極
11、1011 層間絶縁膜
12、1012 ソース電極
12a 第1ソース電極
12b 第2ソース電極
13、1013 裏面電極
14、1014 めっき膜
14a 第1めっき膜
14b 第2めっき膜
15、1015 NiSi電極
16、1016 トレンチ
16a 第1トレンチ
16b 第2トレンチ
17、1017 ゲート配線電極
20、1020 第1TiN膜
21、1021 第1Ti膜
22、1022 第2TiN膜
23、1023 第1保護膜
24、1024 はんだ
24a 第1はんだ
24b 第2はんだ
25、1025 第2保護膜
25a 第1の第2保護膜
25b 第2の第2保護膜
26、1026 外部電極ピン
26a 第1外部電極ピン
26b 第2外部電極ピン
29、1029 Al合金膜
30 p+型領域
31 n+型領域
32 ライフタイムキラー領域
33、1033 第2Ti膜
34 p型領域
100、1100 ゲート電極パッド
104、1104 ソース電極パッド
150、1150 活性領域
150a 有効領域
160、1160 ゲートリング領域
163、1163 第1JTE領域
165、1165 第2JTE領域
167、1167 n+型ストッパー領域
168、1168 エッジ終端領域
170 ソースリング領域
202、1202 電流センス部の電極パッド
230、1230 電流センス部の活性領域
400、1400 高機能領域
500 短絡電極
530、1530 絶縁膜
532 第2絶縁膜
540 金属バー(短絡電極)
550 分断領域
600、1600 半導体チップ
Claims (10)
- 第1導電型の半導体基板と、
前記半導体基板のおもて面に設けられた、前記半導体基板より低不純物濃度の第1導電型の第1半導体層と、
前記第1半導体層の、前記半導体基板側に対して反対側の表面に設けられた第2導電型の第2半導体層と、
前記第2半導体層の、前記半導体基板側に対して反対側の表面層に選択的に設けられた第1導電型の第1半導体領域と、
前記第2半導体層に接触するゲート絶縁膜と、
前記ゲート絶縁膜の前記第2半導体層と接触する面と反対側の表面に設けられた第1のゲート電極と、
前記第1のゲート電極上に設けられた層間絶縁膜と、
前記第2半導体層および前記第1半導体領域の表面に設けられた第1の第1電極と、
前記半導体基板の裏面に設けられた第2電極と、
を有する、主電流が流れる活性領域と、
前記活性領域の周囲を囲むゲートリング領域と、
前記ゲートリング領域の周囲を囲むリング領域と、
前記リング領域の周囲を囲む終端領域と、
を備え、
前記リング領域は、
前記半導体基板と、
前記第1半導体層と、
前記第2半導体層と、
前記第2半導体層の表面に設けられた第2の第1電極と、
前記第2半導体層に接するように前記第1半導体層の表面に設けられ、前記第2半導体層よりも不純物濃度の高い第2導電型の第3半導体領域と、
を有し、
前記リング領域において、前記第3半導体領域の底面の、前記第2の第1電極と対向する位置に第1導電型または第2導電型の第2半導体領域が設けられていることを特徴とする半導体装置。 - 前記リング領域は、
前記第1半導体領域および前記第2半導体層を貫通し、前記第3半導体領域に達する第2のトレンチをさらに有し、
前記第2の第1電極は、前記第2のトレンチの内部に設けられることを特徴とする請求項1に記載の半導体装置。 - 前記第2半導体領域は平面視で四角形状であり、辺の部分にも角部が設けられていることを特徴とする請求項1に記載の半導体装置。
- 第1導電型の半導体基板と、
前記半導体基板のおもて面に設けられた、前記半導体基板より低不純物濃度の第1導電型の第1半導体層と、
前記第1半導体層の、前記半導体基板側に対して反対側の表面に設けられた第2導電型の第2半導体層と、
前記第2半導体層の、前記半導体基板側に対して反対側の表面層に選択的に設けられた第1導電型の第1半導体領域と、
前記第2半導体層に接触するゲート絶縁膜と、
前記ゲート絶縁膜の前記第2半導体層と接触する面と反対側の表面に設けられた第1のゲート電極と、
前記第1のゲート電極上に設けられた層間絶縁膜と、
前記第2半導体層および前記第1半導体領域の表面に設けられた第1の第1電極と、
前記半導体基板の裏面に設けられた第2電極と、
を有する、主電流が流れる活性領域と、
前記活性領域の周囲を囲むゲートリング領域と、
前記ゲートリング領域の周囲を囲むリング領域と、
前記リング領域の周囲を囲む終端領域と、
を備え、
前記リング領域は、
前記半導体基板と、
前記第1半導体層と、
前記第2半導体層と、
前記第2半導体層の表面に設けられた第2の第1電極と、
前記第2半導体層に接するように前記第1半導体層の表面に設けられ、前記第2半導体層よりも不純物濃度の高い第2導電型の第3半導体領域と、
を有し、
前記リング領域において、前記第2の第1電極と対向する位置の、前記第1半導体層と前記第3半導体領域とからなるpn接合にライフタイムキラー領域が設けられていることを特徴とする半導体装置。 - 前記ライフタイムキラー領域の前記第2電極側の面は、前記半導体基板に達していることを特徴とする請求項4に記載の半導体装置。
- 前記リング領域は、
前記第1半導体領域および前記第2半導体層を貫通し、前記第3半導体領域に達する第2のトレンチをさらに有し、
前記第2の第1電極は、前記第2のトレンチの内部に設けられることを特徴とする請求項4に記載の半導体装置。 - 前記活性領域は、
前記第1半導体領域および前記第2半導体層を貫通し、前記第1半導体層に達する第1のトレンチと、
前記第1半導体層の内部の、前記第1のトレンチの底部と深さ方向に対向する位置に選択的に設けられた第2導電型の第4半導体領域と、
をさらに有し、
隣り合う前記第1のトレンチ間には前記第3半導体領域が設けられており、
前記第1のゲート電極は、前記第1のトレンチの内部に前記ゲート絶縁膜を介して設けられることを特徴とする請求項1〜6のいずれか一つに記載の半導体装置。 - 前記リング領域は、
前記第2の第1電極上に選択的に設けられためっき膜をさらに有することを特徴とする請求項1〜7のいずれか一つに記載の半導体装置。 - 前記第2半導体領域の底部は、前記第4半導体領域の底部よりも深いことを特徴とする請求項7に記載の半導体装置。
- 前記ゲートリング領域は、
前記半導体基板と、
前記第1半導体層と、
前記第2半導体層と、
前記第3半導体領域と、
前記第2半導体層に接触する第1の絶縁膜と、
前記第1の絶縁膜の前記第2半導体層と接触する面と反対側の表面に設けられた第2のゲート電極と、
前記第2のゲート電極上に設けられたゲート配線電極と、
を有することを特徴とする請求項1〜6のいずれか一つに記載の半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019162543A JP7404722B2 (ja) | 2019-09-06 | 2019-09-06 | 半導体装置 |
CN202010720748.4A CN112466922A (zh) | 2019-09-06 | 2020-07-24 | 半导体装置 |
US16/984,136 US11404566B2 (en) | 2019-09-06 | 2020-08-03 | Semiconductor device |
JP2023208081A JP2024019464A (ja) | 2019-09-06 | 2023-12-08 | 半導体装置 |
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JP7340726B1 (ja) | 2022-03-11 | 2023-09-07 | ヌヴォトンテクノロジージャパン株式会社 | 半導体装置 |
WO2023171137A1 (ja) * | 2022-03-11 | 2023-09-14 | ヌヴォトンテクノロジージャパン株式会社 | 半導体装置 |
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JP4830285B2 (ja) * | 2004-11-08 | 2011-12-07 | 株式会社デンソー | 炭化珪素半導体装置の製造方法 |
JP6164636B2 (ja) | 2013-03-05 | 2017-07-19 | ローム株式会社 | 半導体装置 |
CN105103284B (zh) | 2013-09-11 | 2017-11-14 | 富士电机株式会社 | 半导体装置 |
WO2016039071A1 (ja) | 2014-09-08 | 2016-03-17 | 富士電機株式会社 | 半導体装置及びその製造方法 |
WO2016039072A1 (ja) | 2014-09-08 | 2016-03-17 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP6409681B2 (ja) | 2015-05-29 | 2018-10-24 | 株式会社デンソー | 半導体装置およびその製造方法 |
JP6828449B2 (ja) | 2017-01-17 | 2021-02-10 | 株式会社デンソー | 半導体装置およびその製造方法 |
JP6835241B2 (ja) | 2017-10-05 | 2021-02-24 | 富士電機株式会社 | 半導体装置 |
JP7091693B2 (ja) * | 2018-02-19 | 2022-06-28 | 富士電機株式会社 | 半導体装置 |
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JP7340726B1 (ja) | 2022-03-11 | 2023-09-07 | ヌヴォトンテクノロジージャパン株式会社 | 半導体装置 |
WO2023171137A1 (ja) * | 2022-03-11 | 2023-09-14 | ヌヴォトンテクノロジージャパン株式会社 | 半導体装置 |
KR20230148272A (ko) * | 2022-03-11 | 2023-10-24 | 누보톤 테크놀로지 재팬 가부시키가이샤 | 반도체 장치 |
TWI829510B (zh) * | 2022-03-11 | 2024-01-11 | 日商新唐科技日本股份有限公司 | 半導體裝置 |
KR102630457B1 (ko) | 2022-03-11 | 2024-01-29 | 누보톤 테크놀로지 재팬 가부시키가이샤 | 반도체 장치 |
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