JP6863464B2 - 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 - Google Patents
炭化珪素半導体装置および炭化珪素半導体装置の製造方法 Download PDFInfo
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- JP6863464B2 JP6863464B2 JP2019540832A JP2019540832A JP6863464B2 JP 6863464 B2 JP6863464 B2 JP 6863464B2 JP 2019540832 A JP2019540832 A JP 2019540832A JP 2019540832 A JP2019540832 A JP 2019540832A JP 6863464 B2 JP6863464 B2 JP 6863464B2
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- 239000004065 semiconductor Substances 0.000 title claims description 366
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims description 221
- 229910010271 silicon carbide Inorganic materials 0.000 title claims description 219
- 238000004519 manufacturing process Methods 0.000 title claims description 34
- 238000000034 method Methods 0.000 title claims description 29
- 239000010410 layer Substances 0.000 claims description 176
- 239000000758 substrate Substances 0.000 claims description 114
- 239000011229 interlayer Substances 0.000 claims description 90
- 229910000679 solder Inorganic materials 0.000 claims description 76
- 238000007747 plating Methods 0.000 claims description 73
- 239000012535 impurity Substances 0.000 claims description 35
- 230000004888 barrier function Effects 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 239000002344 surface layer Substances 0.000 claims description 14
- 239000010408 film Substances 0.000 description 175
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 17
- 238000000206 photolithography Methods 0.000 description 14
- 238000010438 heat treatment Methods 0.000 description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 10
- 238000005468 ion implantation Methods 0.000 description 9
- 239000010936 titanium Substances 0.000 description 9
- 229910052782 aluminium Inorganic materials 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 229910052698 phosphorus Inorganic materials 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 238000000059 patterning Methods 0.000 description 7
- 230000035882 stress Effects 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 125000004437 phosphorous atom Chemical group 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 230000001788 irregular Effects 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H01L21/02524—Group 14 semiconducting materials
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- H01L23/3157—Partial encapsulation or coating
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Description
前記第4工程では、前記ゲート電極を、前記トレンチの内部に前記ゲート絶縁膜を介して形成することを特徴とする。
本発明にかかる半導体装置は、ワイドバンドギャップ半導体を用いて構成される。実施の形態1においては、ワイドバンドギャップ半導体として例えば炭化珪素(SiC)を用いて作製された炭化珪素半導体装置について、MOSFETを例に説明する。図1は、実施の形態1にかかる炭化珪素半導体装置の図3、図4のC−C’部分の構造を示す断面図である。図2は、実施の形態1にかかる炭化珪素半導体装置の図3、図4のD−D’部分の構造を示す断面図である。
次に、実施の形態1にかかる炭化珪素半導体装置の製造方法について説明する。図8〜図14は、実施の形態1にかかる炭化珪素半導体装置の製造途中の状態を模式的に示す断面図である。
図15は、実施の形態2にかかる炭化珪素半導体装置の図16のD−D’部分の構造を示す断面図である。また、図16は、実施の形態2にかかる炭化珪素半導体装置の構造の一部を示す斜視図である。図16のC−C’部分の構造は、実施の形態1の図1と同様であるために省略する。
次に、実施の形態2にかかる炭化珪素半導体装置の製造方法について説明する。まず、実施の形態1と同様に、n型炭化珪素エピタキシャル層2を形成する工程から、トレンチ18を形成する工程までを順に行う。
図17は、実施の形態3にかかる炭化珪素半導体装置の図19のC−C’部分の構造を示す断面図である。図18は、実施の形態3にかかる炭化珪素半導体装置の図19のD−D’部分の構造を示す断面図である。また、図19は、実施の形態3にかかる炭化珪素半導体装置の構造の一部を示す斜視図である。
次に、実施の形態3にかかる炭化珪素半導体装置の製造方法について説明する。まず、実施の形態1と同様に、n型炭化珪素エピタキシャル層2を形成する工程から、ゲート絶縁膜9を形成する工程までを順に行う。
図20は、実施の形態4にかかる炭化珪素半導体装置の構造を示す上面図である。また、図21は、実施の形態4にかかる炭化珪素半導体装置の他の構造を示す上面図である。図20、図21において右図は、左図の点線の部分を拡大したものである。実施の形態4にかかる炭化珪素半導体装置の構造を示す断面図は従来の炭化珪素半導体装置(図22参照)と同様であるために省略する。
次に、実施の形態4にかかる炭化珪素半導体装置の製造方法について説明する。まず、実施の形態1と同様に、n型炭化珪素エピタキシャル層2を形成する工程から、第1p+型ベース領域4、第2p+型ベース領域5、n+型ソース領域7、p++型コンタクト領域8の活性化処理を実施する工程までを順に行う。
2 n型炭化珪素エピタキシャル層
2a 第1n型炭化珪素エピタキシャル層
2b 第2n型炭化珪素エピタキシャル層
3 p型炭化珪素エピタキシャル層
4 第1p+型ベース領域
4a 下部第1p+型ベース領域
4b 上部第1p+型ベース領域
5 第2p+型ベース領域
6 n型高濃度領域
6a 下部n型高濃度領域
6b 上部n型高濃度領域
7 n+型ソース領域
8 p++型コンタクト領域
9 ゲート絶縁膜
10 ゲート電極
11 層間絶縁膜
13 ソース電極
14 裏面電極
15 ソース電極パッド
16 めっき膜
17 はんだ
18 トレンチ
19 ピン状電極
20 保護膜
22 Ti膜
23 TiN膜
100 ゲートパッド領域
110 ソースパッド領域
120 めっき領域
130 ソースパッド領域中でめっき領域が設けられていない領域
140 ソースパッド領域中でめっき領域が設けられている領域
Claims (10)
- 第1導電型の半導体基板と、
前記半導体基板のおもて面に設けられた、前記半導体基板より低不純物濃度の第1導電型の第1半導体層と、
前記第1半導体層の、前記半導体基板側に対して反対側の表面に選択的に設けられた第2導電型の第2半導体層と、
前記第2半導体層の、前記半導体基板側に対して反対側の表面層に選択的に設けられた第1導電型の第1半導体領域と、
前記第2半導体層の、前記半導体基板側に対して反対側にゲート絶縁膜を介して設けられたゲート電極と、
前記ゲート電極上に設けられた層間絶縁膜と、
前記第2半導体層および前記第1半導体領域を露出するように前記層間絶縁膜に設けられたストライプ形状のコンタクトホールと、
前記コンタクトホール内に露出した前記第2半導体層と前記第1半導体領域の表面、および前記層間絶縁膜の表面に設けられた第1電極と、
前記第1電極上に、選択的に設けられためっき膜と、
前記めっき膜上のはんだと、
前記半導体基板の裏面に設けられた第2電極と、
を備え、
前記めっき膜の下部では、前記コンタクトホールの各々に、前記ストライプ形状の長手方向と交わる方向に延在する凸部分が少なくとも1つずつ設けられており、
前記層間絶縁膜と前記第1電極との間にバリアメタルがさらに設けられ、前記凸部分は前記バリアメタルからなることを特徴とする炭化珪素半導体装置。 - 第1導電型の半導体基板と、
前記半導体基板のおもて面に設けられた、前記半導体基板より低不純物濃度の第1導電型の第1半導体層と、
前記第1半導体層の、前記半導体基板側に対して反対側の表面に選択的に設けられた第2導電型の第2半導体層と、
前記第2半導体層の、前記半導体基板側に対して反対側の表面層に選択的に設けられた第1導電型の第1半導体領域と、
前記第2半導体層の、前記半導体基板側に対して反対側にゲート絶縁膜を介して設けられたゲート電極と、
前記ゲート電極上に設けられた層間絶縁膜と、
前記第2半導体層および前記第1半導体領域を露出するように前記層間絶縁膜に設けられたストライプ形状のコンタクトホールと、
前記コンタクトホール内に露出した前記第2半導体層と前記第1半導体領域の表面、および前記層間絶縁膜の表面に設けられた第1電極と、
前記第1電極上に、選択的に設けられためっき膜と、
前記めっき膜上のはんだと、
前記半導体基板の裏面に設けられた第2電極と、
を備え、
前記めっき膜の下部では、前記層間絶縁膜には前記コンタクトホールが設けられていないことを特徴とする炭化珪素半導体装置。 - 第1導電型の半導体基板と、
前記半導体基板のおもて面に設けられた、前記半導体基板より低不純物濃度の第1導電型の第1半導体層と、
前記第1半導体層の、前記半導体基板側に対して反対側の表面に選択的に設けられた第2導電型の第2半導体層と、
前記第2半導体層の、前記半導体基板側に対して反対側の表面層に選択的に設けられた第1導電型の第1半導体領域と、
前記第2半導体層の、前記半導体基板側に対して反対側にゲート絶縁膜を介して設けられたゲート電極と、
前記ゲート電極上に設けられた層間絶縁膜と、
前記第2半導体層および前記第1半導体領域を露出するように前記層間絶縁膜に設けられたストライプ形状のコンタクトホールと、
前記コンタクトホール内に露出した前記第2半導体層と前記第1半導体領域の表面、および前記層間絶縁膜の表面に設けられた第1電極と、
前記第1電極上に、選択的に設けられためっき膜と、
前記めっき膜上のはんだと、
前記半導体基板の裏面に設けられた第2電極と、
を備え、
前記ゲート電極は、前記めっき膜のない領域ではストライプ形状であり、前記めっき膜の下部では前記ストライプ形状と方向が異なるストライプ形状であることを特徴とする炭化珪素半導体装置。 - 複数の前記凸部分は、上面から見た際に六角形の形状に配置されていることを特徴とする請求項1に記載の炭化珪素半導体装置。
- 前記第2半導体層を貫通して、前記第1半導体層に達するトレンチをさらに備え、
前記ゲート電極は、前記トレンチの内部に前記ゲート絶縁膜を介して設けられていることを特徴とする請求項1〜4のいずれか一つに記載の炭化珪素半導体装置。 - 第1導電型の半導体基板のおもて面に、前記半導体基板より低不純物濃度の第1導電型の第1半導体層を形成する第1工程と、
前記第1半導体層の、前記半導体基板側に対して反対側の表面に選択的に第2導電型の第2半導体層を形成する第2工程と、
前記第2半導体層の、前記半導体基板側に対して反対側の表面層に選択的に第1導電型の第1半導体領域を形成する第3工程と、
前記第2半導体層の、前記半導体基板側に対して反対側にゲート絶縁膜を介してゲート電極を形成する第4工程と、
前記ゲート電極上に層間絶縁膜を形成する第5工程と、
前記第2半導体層および前記第1半導体領域を露出するように前記層間絶縁膜にストライプ形状のコンタクトホールを形成する第6工程と、
前記コンタクトホール内に露出した前記第2半導体層と前記第1半導体領域の表面、および前記層間絶縁膜の表面に第1電極を形成する第7工程と、
前記第1電極上に、選択的にめっき膜を形成する第8工程と、
前記めっき膜上にはんだを形成する第9工程と、
前記半導体基板の裏面に第2電極を形成する第10工程と、
を含み、
前記めっき膜の下部では、前記コンタクトホールの各々に、前記ストライプ形状の長手方向と交わる方向に延在する凸部分が少なくとも1つずつ設けられるように形成し、
前記層間絶縁膜と前記第1電極との間にバリアメタルがさらに設けられ、前記凸部分は前記バリアメタルにより形成されていることを特徴とする炭化珪素半導体装置の製造方法。 - 第1導電型の半導体基板のおもて面に、前記半導体基板より低不純物濃度の第1導電型の第1半導体層を形成する第1工程と、
前記第1半導体層の、前記半導体基板側に対して反対側の表面に選択的に第2導電型の第2半導体層を形成する第2工程と、
前記第2半導体層の、前記半導体基板側に対して反対側の表面層に選択的に第1導電型の第1半導体領域を形成する第3工程と、
前記第2半導体層の、前記半導体基板側に対して反対側にゲート絶縁膜を介してゲート電極を形成する第4工程と、
前記ゲート電極上に層間絶縁膜を形成する第5工程と、
前記第2半導体層および前記第1半導体領域を露出するように前記層間絶縁膜にストライプ形状のコンタクトホールを形成する第6工程と、
前記コンタクトホール内に露出した前記第2半導体層と前記第1半導体領域の表面、および前記層間絶縁膜の表面に第1電極を形成する第7工程と、
前記第1電極上に、選択的にめっき膜を形成する第8工程と、
前記めっき膜上にはんだを形成する第9工程と、
前記半導体基板の裏面に第2電極を形成する第10工程と、
を含み、
前記めっき膜の下部では、前記層間絶縁膜には前記コンタクトホールを形成しないことを特徴とする炭化珪素半導体装置の製造方法。 - 第1導電型の半導体基板のおもて面に、前記半導体基板より低不純物濃度の第1導電型の第1半導体層を形成する第1工程と、
前記第1半導体層の、前記半導体基板側に対して反対側の表面に選択的に第2導電型の第2半導体層を形成する第2工程と、
前記第2半導体層の、前記半導体基板側に対して反対側の表面層に選択的に第1導電型の第1半導体領域を形成する第3工程と、
前記第2半導体層の、前記半導体基板側に対して反対側にゲート絶縁膜を介してゲート電極を形成する第4工程と、
前記ゲート電極上に層間絶縁膜を形成する第5工程と、
前記第2半導体層および前記第1半導体領域を露出するように前記層間絶縁膜にストライプ形状のコンタクトホールを形成する第6工程と、
前記コンタクトホール内に露出した前記第2半導体層と前記第1半導体領域の表面、および前記層間絶縁膜の表面に第1電極を形成する第7工程と、
前記第1電極上に、選択的にめっき膜を形成する第8工程と、
前記めっき膜上にはんだを形成する第9工程と、
前記半導体基板の裏面に第2電極を形成する第10工程と、
を含み、
前記第4工程では、前記ゲート電極を、前記めっき膜のない領域ではストライプ形状に、前記めっき膜の下部では前記ストライプ形状と方向が異なるストライプ形状に形成することを特徴とする炭化珪素半導体装置の製造方法。 - 複数の前記凸部分は、上面から見た際に六角形の形状に配置されるように形成されることを特徴とする請求項6に記載の炭化珪素半導体装置の製造方法。
- 前記第2半導体層を貫通して、前記第1半導体層に達するトレンチ形成する工程をさらに含み、
前記第4工程では、前記ゲート電極を、前記トレンチの内部に前記ゲート絶縁膜を介して形成することを特徴とする請求項6〜8のいずれか一つに記載の炭化珪素半導体装置の製造方法。
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JP6729003B2 (ja) * | 2015-10-19 | 2020-07-22 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
CN106601710B (zh) | 2015-10-19 | 2021-01-29 | 富士电机株式会社 | 半导体装置以及半导体装置的制造方法 |
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