JP5547615B2 - 配線基板、半導体装置及び配線基板の製造方法 - Google Patents

配線基板、半導体装置及び配線基板の製造方法 Download PDF

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Publication number
JP5547615B2
JP5547615B2 JP2010254494A JP2010254494A JP5547615B2 JP 5547615 B2 JP5547615 B2 JP 5547615B2 JP 2010254494 A JP2010254494 A JP 2010254494A JP 2010254494 A JP2010254494 A JP 2010254494A JP 5547615 B2 JP5547615 B2 JP 5547615B2
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JP
Japan
Prior art keywords
layer
wiring
insulating layer
wiring layer
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2010254494A
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English (en)
Japanese (ja)
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JP2012104774A (ja
JP2012104774A5 (enExample
Inventor
茂次 村松
規貴 片桐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2010254494A priority Critical patent/JP5547615B2/ja
Priority to US13/293,857 priority patent/US9741647B2/en
Publication of JP2012104774A publication Critical patent/JP2012104774A/ja
Publication of JP2012104774A5 publication Critical patent/JP2012104774A5/ja
Application granted granted Critical
Publication of JP5547615B2 publication Critical patent/JP5547615B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
JP2010254494A 2010-11-15 2010-11-15 配線基板、半導体装置及び配線基板の製造方法 Active JP5547615B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2010254494A JP5547615B2 (ja) 2010-11-15 2010-11-15 配線基板、半導体装置及び配線基板の製造方法
US13/293,857 US9741647B2 (en) 2010-11-15 2011-11-10 Wiring substrate, semiconductor device, and method of manufacturing wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010254494A JP5547615B2 (ja) 2010-11-15 2010-11-15 配線基板、半導体装置及び配線基板の製造方法

Publications (3)

Publication Number Publication Date
JP2012104774A JP2012104774A (ja) 2012-05-31
JP2012104774A5 JP2012104774A5 (enExample) 2013-07-25
JP5547615B2 true JP5547615B2 (ja) 2014-07-16

Family

ID=46047057

Family Applications (1)

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JP2010254494A Active JP5547615B2 (ja) 2010-11-15 2010-11-15 配線基板、半導体装置及び配線基板の製造方法

Country Status (2)

Country Link
US (1) US9741647B2 (enExample)
JP (1) JP5547615B2 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9275925B2 (en) * 2013-03-12 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for an improved interconnect structure
JP6169955B2 (ja) * 2013-04-17 2017-07-26 新光電気工業株式会社 配線基板及びその製造方法
JP6269661B2 (ja) 2013-05-08 2018-01-31 株式会社村田製作所 多層配線基板
KR102163041B1 (ko) * 2013-11-19 2020-10-08 삼성전기주식회사 회로기판, 회로기판 제조방법 및 2단 비아 구조
JP5662551B1 (ja) 2013-12-20 2015-01-28 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
TWI504320B (zh) * 2014-06-17 2015-10-11 矽品精密工業股份有限公司 線路結構及其製法
JP7112877B2 (ja) * 2018-04-20 2022-08-04 新光電気工業株式会社 センサモジュール
US10643943B2 (en) * 2018-06-25 2020-05-05 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure, package-on-package structure and manufacturing method thereof
JP2021125643A (ja) * 2020-02-07 2021-08-30 キオクシア株式会社 半導体装置およびその製造方法
TWI781049B (zh) * 2022-01-24 2022-10-11 欣興電子股份有限公司 電路板結構及其製作方法
US20250038093A1 (en) * 2023-07-27 2025-01-30 Taiwan Semiconductor Manufacturing Company Limited Interposers including line-on-via and line-in-via interconnect structures and methods of forming the same

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2720865B2 (ja) 1996-01-22 1998-03-04 日立エーアイシー株式会社 多層印刷配線板およびその製造方法
US6492719B2 (en) * 1999-07-30 2002-12-10 Hitachi, Ltd. Semiconductor device
JP4869488B2 (ja) 2000-12-15 2012-02-08 イビデン株式会社 多層プリント配線板の製造方法
JP2004273575A (ja) 2003-03-05 2004-09-30 Sony Corp 多層プリント配線基板及びその製造方法
US7211289B2 (en) * 2003-12-18 2007-05-01 Endicott Interconnect Technologies, Inc. Method of making multilayered printed circuit board with filled conductive holes
KR100688701B1 (ko) 2005-12-14 2007-03-02 삼성전기주식회사 랜드리스 비아홀을 구비한 인쇄회로기판의 제조방법
JP5324051B2 (ja) * 2007-03-29 2013-10-23 新光電気工業株式会社 配線基板の製造方法及び半導体装置の製造方法及び配線基板
JP2008283140A (ja) * 2007-05-14 2008-11-20 Shinko Electric Ind Co Ltd 配線基板の製造方法及び配線基板
KR100990618B1 (ko) 2008-04-15 2010-10-29 삼성전기주식회사 랜드리스 비아홀을 갖는 인쇄회로기판 및 그 제조방법
JP2010103435A (ja) 2008-10-27 2010-05-06 Shinko Electric Ind Co Ltd 配線基板及びその製造方法
JP2011165741A (ja) * 2010-02-05 2011-08-25 Renesas Electronics Corp 半導体装置およびその製造方法
US8541693B2 (en) * 2010-03-31 2013-09-24 Ibiden Co., Ltd. Wiring board and method for manufacturing the same

Also Published As

Publication number Publication date
US20120119377A1 (en) 2012-05-17
US9741647B2 (en) 2017-08-22
JP2012104774A (ja) 2012-05-31

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