JP5522917B2 - Ｓｏｉ基板の製造方法 - Google Patents

Ｓｏｉ基板の製造方法 Download PDF

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Publication number
JP5522917B2
JP5522917B2 JP2008257001A JP2008257001A JP5522917B2 JP 5522917 B2 JP5522917 B2 JP 5522917B2 JP 2008257001 A JP2008257001 A JP 2008257001A JP 2008257001 A JP2008257001 A JP 2008257001A JP 5522917 B2 JP5522917 B2 JP 5522917B2
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layer
substrate
semiconductor wafer
wafer
insulating layer
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JP2008257001A
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Japanese (ja)
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JP2009111362A5 (https=
JP2009111362A (ja
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英人 大沼
舜平 山崎
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2008257001A priority Critical patent/JP5522917B2/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Thin Film Transistor (AREA)
  • Electroluminescent Light Sources (AREA)
  • Recrystallisation Techniques (AREA)
JP2008257001A 2007-10-10 2008-10-02 Ｓｏｉ基板の製造方法 Expired - Fee Related JP5522917B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008257001A JP5522917B2 (ja) 2007-10-10 2008-10-02 Ｓｏｉ基板の製造方法

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Application Number Priority Date Filing Date Title
JP2007264998 2007-10-10
JP2007264998 2007-10-10
JP2008257001A JP5522917B2 (ja) 2007-10-10 2008-10-02 Ｓｏｉ基板の製造方法

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JP2009111362A JP2009111362A (ja) 2009-05-21
JP2009111362A5 JP2009111362A5 (https=) 2011-10-27
JP5522917B2 true JP5522917B2 (ja) 2014-06-18

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JP2008257001A Expired - Fee Related JP5522917B2 (ja) 2007-10-10 2008-10-02 Ｓｏｉ基板の製造方法

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US (2) US7989305B2 (https=)
JP (1) JP5522917B2 (https=)
CN (1) CN101409222B (https=)

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CN106683980B (zh) * 2016-12-27 2019-12-13 上海新傲科技股份有限公司 带有载流子俘获中心的衬底的制备方法
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CN110767773A (zh) * 2019-09-29 2020-02-07 南通苏民新能源科技有限公司 一种提高半片太阳能电池组件光电转换效率的方法
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Also Published As

Publication number Publication date
US20090098704A1 (en) 2009-04-16
CN101409222B (zh) 2013-01-02
US8409966B2 (en) 2013-04-02
US20110263096A1 (en) 2011-10-27
CN101409222A (zh) 2009-04-15
US7989305B2 (en) 2011-08-02
JP2009111362A (ja) 2009-05-21

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