CN106601663B - Soi衬底及其制备方法 - Google Patents

Soi衬底及其制备方法 Download PDF

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CN106601663B
CN106601663B CN201510683914.7A CN201510683914A CN106601663B CN 106601663 B CN106601663 B CN 106601663B CN 201510683914 A CN201510683914 A CN 201510683914A CN 106601663 B CN106601663 B CN 106601663B
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heavy hydrogen
dielectric layer
soi substrate
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CN106601663A (zh
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肖德元
张汝京
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Zing Semiconductor Corp
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Priority to US15/166,015 priority patent/US20170110362A1/en
Priority to JP2016108526A priority patent/JP6174756B2/ja
Priority to KR1020160123796A priority patent/KR101903239B1/ko
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Abstract

本发明提供一种SOI衬底及其制备方法，包括：提供第一衬底，所述第一衬底上形成有第一介质层；对所述第一衬底进行重氢离子注入，预定深度的所述第一衬底中形成重氢掺杂层；提供第二衬底，所述第二衬底上形成有第二介质层，将所述第一介质层与所述第二介质层相键合；进行热退火，所述重氢掺杂层中形成微气泡；从所述重氢掺杂层处切割所述第一衬底，形成SOI衬底。本发明的SOI衬底的上层硅中存在重氢离子，在后续器件形成栅氧化层或界面时，重氢能够扩散出，与界面处的悬空键结合，形成较为稳定的结构。并且，重氢离子可以消除器件中存在的缺陷，避免热载流子的穿透。从而不需要进行氢气退火以消除缺陷，简化器件的工艺流程，提高器件的性能及可靠性。

Description

SOI衬底及其制备方法
技术领域
本发明涉及半导体制造技术领域，尤其涉及一种SOI衬底及其制备方法。
背景技术
绝缘体上硅(Silicon On Insulator，SOI)衬底是一种用于集成电路制造的衬底。与目前大量应用的体硅衬底相比，SOI衬底具有很多优势：采用SOI衬底制成的集成电路的寄生电容小、集成密度高、短沟道效应小、速度快，并且还可以实现集成电路中元器件的介质隔离，消除了体硅集成电路中的寄生闩锁效应。
目前较为成熟的SOI衬底的形成工艺主要有三种，具体为注氧隔离(Separationby Implanted Oxygen，SIMOX)工艺、硅片键合工艺和智能剥离(Smart Cut)工艺。然而，现有技术中制备的SOI衬底中存在缺陷，影响器件的性能。
发明内容
本发明的目的在于，提供一种SOI衬底及其制备方法，使得在SOI衬底上形成的器件不需要进行氢气退火过程，即可消除器件中的缺陷。
为解决上述技术问题，本发明一种SOI衬底的制备方法，包括：
提供第一衬底，所述第一衬底上形成有第一介质层；
对所述第一衬底进行重氢离子注入，预定深度的所述第一衬底中形成重氢掺杂层；
提供第二衬底，所述第二衬底上形成有第二介质层，将所述第一介质层与所述第二介质层相键合；
进行热退火，所述重氢掺杂层中形成微气泡；
从所述重氢掺杂层处切割所述第一衬底，形成SOI衬底。
可选的，所述第二衬底为所述SOI衬底的硅衬底，所述第一介质层与所述第二介质层为所述SOI衬底的绝缘层，所述重氢掺杂层与所述第一介质层之间的部分所述第一衬底为所述SOI衬底的上层硅。
可选的，所述上层硅中具有重氢离子。
可选的，所述SOI衬底的制备方法还包括：对所述上层硅进行化学机械抛光。
可选的，所述预定深度为50nm～200nm。
可选的，所述第一介质层为氧化硅、氮化硅或氮化铝，所述第一介质层的厚度为0.1nm～200nm。
可选的，采用重氢离子对所述第一衬底进行离子注入时，所述重氢离子的注入能量为1KeV～500KeV，所述重氢离子的掺杂浓度为1.0×1014～1.0×1018/cm3。
可选的，采用重氢等离子体浸没离子注入对所述第一衬底进行离子注入时，所述重氢等离子体浸没离子注入的注入能量为500eV～5KeV，所述重氢等离子体的掺杂浓度为1.0×1014～1.0×1018/cm3。
可选的，所述第二介质层为氧化硅、氮化硅或氮化铝，所述第二介质层的厚度为0.05nm～10nm。
可选的，在300℃～400℃的温度下，将所述第一介质层与所述第二介质层相键合。
可选的，在600℃～800℃的温度下，对所述重氢掺杂层进行热退火。
相应的，本发明还提供一种SOI衬底，所述SOI衬底包括硅衬底、位于所述硅衬底上的绝缘层以及位于所述绝缘层上的上层硅，所述SOI衬底采用上述的SOI衬底的制备方法形成，其中，所述上层硅中具有重氢离子。
本发明提供的SOI衬底及其制备方法中，对所述第一衬底进行重氢离子注入，由于重氢离子的质量大，热退火过程后，重氢离子还存在于第一衬底中，使得形成的SOI衬底的上层硅中存在重氢离子。在本发明的SOI衬底上形成的器件中，在后续器件形成栅氧化层或界面时，重氢能够扩散出，与界面处的悬空键结合，形成较为稳定的结构。并且，重氢离子可以消除器件中存在的缺陷，避免热载流子的穿透。从而不需要进行氢气退火消除缺陷，简化器件的工艺流程，提高器件的性能及可靠性。
附图说明
图1为本发明一实施例中制备SOI衬底的方法的流程图；
图2为本发明一实施例中第一衬底的剖面结构示意图；
图3为本发明一实施例中进行重氢离子注入的剖面结构示意图；
图4为本发明一实施例中第一介质层与第二介质层键合的剖面结构示意图；
图5为本发明一实施例中重氢掺杂层中形成微气泡的剖面结构示意图；
图6为本发明一实施例中切割所述第一衬底的剖面结构示意图。
具体实施方式
下面将结合示意图对本发明的SOI衬底及其制备方法进行更详细的描述，其中表示了本发明的优选实施例，应该理解本领域技术人员可以修改在此描述的本发明，而仍然实现本发明的有利效果。因此，下列描述应当被理解为对于本领域技术人员的广泛知道，而并不作为对本发明的限制。
本发明的核心思想在于，提供一种SOI衬底及其制备方法，对所述第一衬底进行重氢离子注入，由于重氢离子的质量大，热退火过程后，重氢离子还存在第一衬底中，使得形成的SOI衬底的上层硅中存在重氢离子。在本发明的SOI衬底形成的器件中，在后续器件形成栅氧化层或界面时，重氢能够扩散出，与界面处的悬空键结合，形成较为稳定的结构。并且，重氢离子可以消除器件中存在的缺陷，避免热载流子的穿透。从而不需要进行氢气退火消除缺陷，简化器件的工艺流程，提高器件的性能及可靠性。
下文结合附图对本发明的SOI衬底及其制备方法进行描述，图1为SOI衬底的制备流程图，图2～图6为各步骤中的结构示意图，其制备过程包括如下步骤：
执行步骤S1，参考图2所示，提供第一衬底100，所述第一衬底为单晶硅衬底。在所述第一衬底100上形成第一介质层110，在本实施例中，可以采用化学气相沉积形成所述第一介质层110，所述第一介质层110为氧化硅、氮化硅或氮化铝，所述第一介质层110的厚度为0.1nm～200nm，例如为10nm、50nm、100nm、150nm等。
执行步骤S2，参考图3所示，对所述第一衬底100进行重氢离子(D+)注入，可以理解的是，重氢D(或称氘)是氢的同位素，质量数比氢大。本实施例中，所述第一衬底100中预定深度H处形成重氢掺杂层120，所述预定深度H为50nm～200nm。并且，采用重氢离子D+对所述第一衬底100进行离子注入时，所述重氢离子D+的注入能量为1KeV～500KeV，例如，注入能量为10KeV、50KeV、100KeV、200KeV、350KeV、450KeV等，所述重氢离体D+掺杂的浓度为1.0×1014～1.0×1018/cm3。例如，1.2×1014/cm3、2.02×1015/cm3、3.5×1017/cm3等。此外，还可以采用重氢等离子体浸没离子注入对所述第一衬底100进行离子注入，所述重氢等离子体浸没离子注入的注入能量为500eV～5KeV，所述重氢等离子体的掺杂浓度为1.0×1014～1.0×1018/cm3。需要说明的是，重氢掺杂层120与第一介质层110中的第一衬底100中同时存在微量的重氢离子。
执行步骤S3，参考图4所示，提供第二衬底200，第二衬底200为单晶硅衬底。在所述第二衬底200上形成第二介质层210，在本实施例中，采用化学气相沉积方法形成第二介质层210，所述第二介质层210为氧化硅、氮化硅或氮化铝，所述第二介质层210的厚度为0.05nm～10nm。接着，将所述第一介质层110面向所述第二介质层210，并与所述第二介质层210相键合，本实施例中，在300℃～400℃的温度下，将所述第一介质层110与所述第二介质层210键合，使得第一介质层110与第二介质层210之间键合更加紧密。在本实施例中，第一介质层110与第二介质层210作为后续SOI衬底的绝缘层，其材料可以相同，也可以不同，本发明对此不予限定。
执行步骤S4，参考图5所示，将第一介质层110与第二介质层210键合后的结构进行热退火，重氢掺杂层120中的重氢离子D+经过热退火，在所述重氢掺杂层120中形成微气泡121，从而使得重氢掺杂层120中形成多孔的疏松结构，便于后续对第一衬底100进行切割分离。在本实施例中，在600℃～800℃的温度下，对所述重氢掺杂层120进行热退火。此外，由于重氢离子相对氢离子大，经过退火过程，重氢离子仍存在与第一衬底100中。
执行步骤S5，参考图6所示，采用切割刀从所述重氢掺杂层120处切割第一衬底100，将所述第一衬底100从所述第二衬底200上剥离，形成SOI衬底300.。可以理解的是，形成的SOI衬底300中，所述第二衬底200为所述SOI衬底300的硅衬底，所述第一介质层110与所述第二介质层210为所述SOI衬底的绝缘层320，所述重氢掺杂层120与所述第一介质层110之间的部分所述第一衬底100为所述SOI衬底的上层硅310。在本实施例中，在切割所述第一衬底100之后，由于切割过程造成的上层硅310表面的不平坦，所述SOI衬底的制备方法还包括：对所述上层硅310进行化学机械抛光，以消除上层硅310表面的不平坦。此外，经过切割之后的第一衬底100’可以继续用于后续SOI衬底的制备，从而循环利用。
相应的，参考图6所示，本发明还提供一种SOI衬底300，所述SOI衬底300包括硅衬底200、位于所述硅衬底200上的绝缘层320以及位于所述绝缘层320上的上层硅310，所述SOI衬底300采用上述的SOI衬底的制备方法形成。本实施例中，所述硅衬底200即为第二衬底，所述绝缘层320包括第一介质层110和第二介质层210，其中，第一介质层110和第二介质层210为氧化层、氮化硅或氮化铝，上层硅310为第一衬底100中的一部分，并且，上层硅310中具有重氢离子。从而在本发明的SOI衬底300上形成的器件中，在器件中形成栅氧化层或界面时，氘能够扩散出，并与界面处等悬空键进行结合，形成较为稳定的结构。并且，重氢离子可以消除器件中存在的缺陷，避免热载流子的穿透。从而不需要进行氢气退火以消除缺陷，简化器件的工艺流程，提高器件的性能及可靠性。
综上所述，本发明中，对所述第一衬底进行重氢离子注入，由于重氢离子的质量大，热退火过程后，重氢离子还存在第一衬底中，使得形成的SOI衬底的上层硅中存在重氢离子。在本发明的SOI衬底形成的器件中，在器件中形成栅氧化层或界面时，重氢能够扩散出，与界面处的悬空键结合，形成较为稳定的结构。并且，重氢离子可以消除器件中存在的缺陷，避免热载流子的穿透。从而不需要进行氢气退火消除缺陷，简化器件的工艺流程，提高器件的性能及可靠性。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (8)

1.一种SOI衬底的制备方法，其特征在于，包括：
提供第一衬底，所述第一衬底上形成有第一介质层；
对所述第一衬底进行重氢离子注入，预定深度的所述第一衬底中形成重氢掺杂层，其中，采用重氢离子对所述第一衬底进行离子注入时，所述重氢离子的注入能量为1KeV～500KeV，所述重氢离子的掺杂浓度为1.0×1014～1.0×1018/cm3；或者，采用重氢等离子体浸没离子注入对所述第一衬底进行离子注入时，所述重氢等离子体浸没离子注入的注入能量为500eV～5KeV，所述重氢等离子体的掺杂浓度为1.0×1014～1.0×1018/cm3；
提供第二衬底，所述第二衬底上形成有第二介质层，将所述第一介质层与所述第二介质层相键合；
进行热退火，所述重氢掺杂层中形成微气泡；
从所述重氢掺杂层处切割所述第一衬底，形成SOI衬底；
其中，所述第二衬底为所述SOI衬底的硅衬底，所述第一介质层与所述第二介质层为所述SOI衬底的绝缘层，所述重氢掺杂层与所述第一介质层之间的部分所述第一衬底为所述SOI衬底的上层硅，此时，所述上层硅中具有重氢离子。
2.如权利要求1所述的SOI衬底的制备方法，其特征在于，所述SOI衬底的制备方法还包括：对所述上层硅进行化学机械抛光。
3.如权利要求1所述的SOI衬底的制备方法，其特征在于，所述预定深度为50nm～200nm。
4.如权利要求1所述的SOI衬底的制备方法，其特征在于，所述第一介质层为氧化硅、氮化硅或氮化铝，所述第一介质层的厚度为0.1nm～200nm。
5.如权利要求1所述的SOI衬底的制备方法，其特征在于，所述第二介质层为氧化硅、氮化硅或氮化铝，所述第二介质层的厚度为0.05nm～10nm。
6.如权利要求1所述的SOI衬底的制备方法，其特征在于，在300℃～400℃的温度下，将所述第一介质层与所述第二介质层相键合。
7.如权利要求1所述的SOI衬底的制备方法，其特征在于，在600℃～800℃的温度下，对所述重氢掺杂层进行热退火。
8.一种SOI衬底，其特征在于，所述SOI衬底包括硅衬底、位于所述硅衬底上的绝缘层以及位于所述绝缘层上的上层硅，所述SOI衬底采用如权利要求1～7中任意一项所述的SOI衬底的制备方法形成，其中，所述上层硅具有重氢离子。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11330438A (ja) * 1998-05-08 1999-11-30 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
US6150239A (en) * 1997-05-31 2000-11-21 Max Planck Society Method for the transfer of thin layers monocrystalline material onto a desirable substrate
CN1340862A (zh) * 2000-09-01 2002-03-20 三菱电机株式会社 半导体装置和“绝缘体上的半导体”衬底
US6544862B1 (en) * 2000-01-14 2003-04-08 Silicon Genesis Corporation Particle distribution method and resulting structure for a layer transfer process
CN1870243A (zh) * 2005-05-24 2006-11-29 国际商业机器公司 具有氘化掩埋层的半导体衬底和器件

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5909627A (en) * 1998-05-18 1999-06-01 Philips Electronics North America Corporation Process for production of thin layers of semiconductor material
FR2811807B1 (fr) * 2000-07-12 2003-07-04 Commissariat Energie Atomique Procede de decoupage d'un bloc de materiau et de formation d'un film mince
DE10224160A1 (de) * 2002-05-31 2003-12-18 Advanced Micro Devices Inc Eine Diffusionsbarrierenschicht in Halbleitersubstraten zur Reduzierung der Kupferkontamination von der Rückseite her
EP1993127B1 (en) * 2007-05-18 2013-04-24 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate
US7781306B2 (en) * 2007-06-20 2010-08-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor substrate and method for manufacturing the same
JP5463017B2 (ja) * 2007-09-21 2014-04-09 株式会社半導体エネルギー研究所 基板の作製方法
US7989305B2 (en) * 2007-10-10 2011-08-02 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate using cluster ion

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6150239A (en) * 1997-05-31 2000-11-21 Max Planck Society Method for the transfer of thin layers monocrystalline material onto a desirable substrate
JPH11330438A (ja) * 1998-05-08 1999-11-30 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
US6544862B1 (en) * 2000-01-14 2003-04-08 Silicon Genesis Corporation Particle distribution method and resulting structure for a layer transfer process
CN1340862A (zh) * 2000-09-01 2002-03-20 三菱电机株式会社 半导体装置和“绝缘体上的半导体”衬底
CN1870243A (zh) * 2005-05-24 2006-11-29 国际商业机器公司 具有氘化掩埋层的半导体衬底和器件

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