TWI587446B - Soi基底及其製備方法 - Google Patents
Soi基底及其製備方法 Download PDFInfo
- Publication number
- TWI587446B TWI587446B TW105107812A TW105107812A TWI587446B TW I587446 B TWI587446 B TW I587446B TW 105107812 A TW105107812 A TW 105107812A TW 105107812 A TW105107812 A TW 105107812A TW I587446 B TWI587446 B TW I587446B
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- dielectric layer
- heavy hydrogen
- soi substrate
- layer
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims description 119
- 238000000034 method Methods 0.000 title claims description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- -1 heavy hydrogen ions Chemical class 0.000 claims description 28
- 238000005468 ion implantation Methods 0.000 claims description 17
- 229910052732 germanium Inorganic materials 0.000 claims description 15
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 15
- 229910052739 hydrogen Inorganic materials 0.000 claims description 13
- 239000001257 hydrogen Substances 0.000 claims description 13
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 11
- 238000002513 implantation Methods 0.000 claims description 7
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 7
- 238000007654 immersion Methods 0.000 claims description 6
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- UFHFLCQGNIYNRP-VVKOMZTBSA-N Dideuterium Chemical compound [2H][2H] UFHFLCQGNIYNRP-VVKOMZTBSA-N 0.000 claims 7
- 229910000449 hafnium oxide Inorganic materials 0.000 claims 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical group [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims 2
- 239000012535 impurity Substances 0.000 claims 1
- YZCKVEUIGOORGS-OUBTZVSYSA-N Deuterium Chemical compound [2H] YZCKVEUIGOORGS-OUBTZVSYSA-N 0.000 description 28
- 230000007547 defect Effects 0.000 description 10
- 238000002360 preparation method Methods 0.000 description 8
- 239000000969 carrier Substances 0.000 description 4
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical group [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 4
- 230000035515 penetration Effects 0.000 description 4
- 229910001936 tantalum oxide Inorganic materials 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006356 dehydrogenation reaction Methods 0.000 description 1
- 229910052805 deuterium Inorganic materials 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/3003—Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Ceramic Engineering (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Plasma & Fusion (AREA)
- Element Separation (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Description
本發明涉及半導體製造技術領域,尤其涉及一種SOI基底及其製備方法。
絕緣層覆矽(Silicon On Insulator,SOI)基底是一種用於積體電路製造的基底。與目前大量應用的體矽基底相比,SOI基底具有很多優勢:採用SOI基底製成的積體電路的寄生電容小、積體密度高、短通道效應小、速度快,並且還可以實現積體電路中元件的介電隔離,消除了體矽積體電路中的寄生閂鎖效應。
目前較為成熟的SOI基底的形成製程主要有三種,具體為注氧隔離(Separation by Implanted Oxygen,SIMOX)製程、矽片鍵合製程和智能剝離(Smart Cut)製程。然而,現有技術中製備的SOI基底中存在缺陷,影響元件的性能。
本發明的目的在於,提供一種SOI基底及其製備方法,使得在SOI基底上形成的元件不需要進行氫氣退火過
程,即可消除元件中的缺陷。
為解決上述技術問題,本發明一種SOI基底的製備方法,包括:提供第一基底,所述第一基底上形成有第一介電層;對所述第一基底進行重氫離子注入,預定深度的所述第一基底中形成重氫摻雜層;提供第二基底,所述第二基底上形成有第二介電層,將所述第一介電層與所述第二介電層相鍵合;進行熱退火,所述重氫摻雜層中形成微氣泡;從所述重氫摻雜層處切割所述第一基底,形成SOI基底。
根據一實施例,所述第二基底為所述SOI基底的矽基底,所述第一介電層與所述第二介電層為所述SOI基底的絕緣層,所述重氫摻雜層與所述第一介電層之間的部分所述第一基底為所述SOI基底的上層矽。
根據一實施例,所述上層矽中具有重氫離子。
根據一實施例,所述SOI基底的製備方法還包括:對所述上層矽進行化學機械拋光。
根據一實施例,所述預定深度為50nm~200nm。
根據一實施例,所述第一介電層為氧化矽、氮化矽或氮化鋁,所述第一介電層的厚度為0.1nm~200nm。
根據一實施例,採用重氫離子對所述第一基底進行離子注入時,所述重氫離子的注入能量為1KeV~500KeV,所述重氫離子的摻雜濃度為1.0×1014~1.0×1018/cm3。
根據一實施例,採用重氫電漿浸沒離子注入對所述第一基底進行離子注入時,所述重氫電漿浸沒離子注入的注入能量為500eV~5KeV,所述重氫電漿的摻雜濃度為1.0×1014~1.0×1018/cm3。
根據一實施例,所述第二介電層為氧化矽、氮化矽或氮化鋁,所述第二介電層的厚度為0.05nm~10nm。
根據一實施例,在300℃~400℃的溫度下,將所述第一介電層與所述第二介電層相鍵合。
根據一實施例,在600℃~800℃的溫度下,對所述重氫摻雜層進行熱退火。
相應的,本發明還提供一種SOI基底,所述SOI基底包括矽基底、位於所述矽基底上的絕緣層以及位於所述絕緣層上的上層矽,所述SOI基底採用上述的SOI基底的製備方法形成,其中,所述上層矽中具有重氫離子。
本發明提供的SOI基底及其製備方法中,對所述第一基底進行重氫離子注入,由於重氫離子的質量大,熱退火過程後,重氫離子還存在於第一基底中,使得形成的SOI基底的上層矽中存在重氫離子。在本發明的SOI基底上形成的元件中,在後續元件形成閘極氧化層或界面時,重氫能夠擴散
出,與界面處的懸鍵結合,形成較為穩定的結構。並且,重氫離子可以消除元件中存在的缺陷,避免熱載子的穿透。從而不需要進行氫氣退火消除缺陷,簡化元件的製造流程,提高元件的性能及可靠性。
100、100’‧‧‧第一基底
110‧‧‧第一介電層
120‧‧‧重氫摻雜層
200‧‧‧第二基底
210‧‧‧第二介電層
300‧‧‧SOI基底
310‧‧‧上層矽
320‧‧‧絕緣層
D+‧‧‧重氫
第1圖為本發明一實施例中製備SOI基底的方法的流程圖;第2圖為本發明一實施例中第一基底的剖面結構示意圖;第3圖為本發明一實施例中進行重氫離子注入的剖面結構示意圖;第4圖為本發明一實施例中第一介電層與第二介電層鍵合的剖面結構示意圖;第5圖為本發明一實施例中重氫摻雜層中形成微氣泡的剖面結構示意圖;第6圖為本發明一實施例中切割所述第一基底的剖面結構示意圖。
下面將結合示意圖對本發明的SOI基底及其製備方法進行更詳細的描述,其中表示了本發明的較佳實施例,應該理解本領域技術人員可以修改在此描述的本發明,而仍
然實現本發明的有利效果。因此,下列描述應當被理解為對於本領域技術人員的廣泛知道,而並不作為對本發明的限制。
本發明的核心思想在於,提供一種SOI基底及其製備方法,對所述第一基底進行重氫離子注入,由於重氫離子的質量大,熱退火過程後,重氫離子還存在第一基底中,使得形成的SOI基底的上層矽中存在重氫離子。在本發明的SOI基底形成的元件中,在後續元件形成閘極氧化層或界面時,重氫能夠擴散出,與界面處的懸鍵結合,形成較為穩定的結構。並且,重氫離子可以消除元件中存在的缺陷,避免熱載子的穿透。從而不需要進行氫氣退火消除缺陷,簡化元件的製造流程,提高元件的性能及可靠性。
下文結合附圖對本發明的SOI基底及其製備方法進行描述,第1圖為SOI基底的製備流程圖,第2圖~第6圖為各步驟中的結構示意圖,其製備過程包括如下步驟:
執行步驟S1,參考第2圖所示,提供第一基底100,所述第一基底為單晶矽基底。在第一基底100上形成第一介電層110,在本實施例中,可以採用化學氣相沉積形成第一介電層110,第一介電層110為氧化矽、氮化矽或氮化鋁,第一介電層110的厚度為0.1nm~200nm,例如為10nm、50nm、100nm、150nm等。
執行步驟S2,參考第3圖所示,對第一基底100進行重氫離子(D+)注入,可以理解的是,重氫D+(或稱氘)
是氫的同位素,質量數比氫大。本實施例中,第一基底100中預定深度H處形成重氫摻雜層120,預定深度H為50nm~200nm。並且,採用重氫離子D+對第一基底100進行離子注入時,重氫離子D+的注入能量為1KeV~500KeV,例如,注入能量為10KeV、50KeV、100KeV、200KeV、350KeV、450KeV等,重氫離體D+摻雜的濃度為1.0×1014~1.0×1018/cm3。例如,1.2×1014/cm3、2.02×1015/cm3、3.5×1017/cm3等。此外,還可以採用重氫電漿浸沒離子注入對第一基底100進行離子注入,重氫電漿浸沒離子注入的注入能量為500eV~5KeV,重氫電漿的摻雜濃度為1.0×1014~1.0×1018/cm3。需要說明的是,重氫摻雜層120與第一介電層110中的第一基底100中同時存在微量的重氫離子。
執行步驟S3,參考第4圖所示,提供第二基底200,第二基底200為單晶矽基底。在第二基底200上形成第二介電層210,在本實施例中,採用化學氣相沉積方法形成第二介電層210,第二介電層210為氧化矽、氮化矽或氮化鋁,第二介電層210的厚度為0.05nm~10nm。接著,將第一介電層110面向第二介電層210,並與第二介電層210相鍵合,本實施例中,在300℃~400℃的溫度下,將第一介電層110與第二介電層210鍵合,使得第一介電層110與第二介電層210之間鍵合更加緊密。在本實施例中,第一介電層110與第二介電層210作為後續SOI基底的絕緣層,其材料可以相同,也可以不同,本發明對
此不予限定。
執行步驟S4,參考第5圖所示,將第一介電層110與第二介電層210鍵合後的結構進行熱退火,重氫摻雜層120中的重氫離子D+經過熱退火,在重氫摻雜層120中形成微氣泡121,從而使得重氫摻雜層120中形成多孔的疏鬆結構,便於後續對第一基底100進行切割分離。在本實施例中,在600℃~800℃的溫度下,對重氫摻雜層120進行熱退火。此外,由於重氫離子相對氫離子大,經過退火過程,重氫離子仍存在與第一基底100中。
執行步驟S5,參考第6圖所示,採用切割刀從重氫摻雜層120處切割第一基底100,將第一基底100從第二基底200上剝離,形成SOI基底300。可以理解的是,形成的SOI基底300中,第二基底200為SOI基底300的矽基底,第一介電層110與第二介電層210為SOI基底的絕緣層320,重氫摻雜層120與第一介電層110之間的部分第一基底100為SOI基底的上層矽310。在本實施例中,在切割第一基底100之後,由於切割過程造成的上層矽310表面的不平坦,SOI基底的製備方法還包括:對上層矽310進行化學機械拋光,以消除上層矽310表面的不平坦。此外,經過切割之後的第一基底100’可以繼續用於後續SOI基底的製備,從而循環利用。
相應的,參考第6圖所示,本發明還提供一種SOI基底300,SOI基底300包括矽基底200、位於矽基底200上的絕
緣層320以及位於絕緣層320上的上層矽310,SOI基底300採用上述的SOI基底的製備方法形成。本實施例中,矽基底200即為第二基底,絕緣層320包括第一介電層110和第二介電層210,其中,第一介電層110和第二介電層210為氧化層、氮化矽或氮化鋁,上層矽310為第一基底100中的一部分,並且,上層矽310中具有重氫離子。從而在本發明的SOI基底300上形成的元件中,在元件中形成閘極氧化層或界面時,氘能夠擴散出,並與界面處等懸鍵進行結合,形成較為穩定的結構。並且,重氫離子可以消除元件中存在的缺陷,避免熱載子的穿透。從而不需要進行氫氣退火以消除缺陷,簡化元件的製造流程,提高元件的性能及可靠性。
綜上,本發明中,對第一基底進行重氫離子注入,由於重氫離子的質量大,熱退火過程後,重氫離子還存在第一基底中,使得形成的SOI基底的上層矽中存在重氫離子。在本發明的SOI基底形成的元件中,在元件中形成閘極氧化層或界面時,重氫能夠擴散出,與界面處的懸鍵結合,形成較為穩定的結構。並且,重氫離子可以消除元件中存在的缺陷,避免熱載子的穿透。從而不需要進行氫氣退火消除缺陷,簡化元件的製造流程,提高元件的性能及可靠性。
顯然,本領域的技術人員可以對本發明進行各種改動和變型而不脫離本發明的精神和範圍。這樣,倘若本發明的這些修改和變型屬於本發明申請專利範圍及其等同技術
的範圍之內,則本發明也意圖包含這些改動和變型在內。
S1~S5‧‧‧SOI基底的備製方法流程步驟
Claims (9)
- 一種SOI基底的製備方法,包括:提供第一基底,該第一基底上形成有第一介電層;對該第一基底進行重氫離子注入,於預定深度的該第一基底中形成重氫摻雜層;提供第二基底,在該第二基底上形成有第二介電層;在300℃~400℃的溫度下,將該第一介電層與該第二介電層相鍵合;在600℃~800℃的溫度下進行熱退火,於該重氫摻雜層中形成微氣泡;從該重氫摻雜層處切割該第一基底,形成SOI基底。
- 如申請專利範圍第1項所述的SOI基底的製備方法,其中,該第二基底為該SOI基底的矽基底,該第一介電層與該第二介電層為該SOI基底的絕緣層,該重氫摻雜層與該第一介電層之間的部分該第一基底為該SOI基底的上層矽。
- 如申請專利範圍第2項所述的SOI基底的製備方法,其中,該上層矽中具有重氫離子。
- 如申請專利範圍第2項所述的SOI基底的製備方法,其中,該SOI基底的製備方法還包括:對該上層矽進行化學機械拋光。
- 如申請專利範圍第1項所述的SOI基底的製備方法,其中,該預定深度為50nm~200nm。
- 如申請專利範圍第1項所述的SOI基底的製備方法,其中,該第一介電層為氧化矽、氮化矽或氮化鋁,該第一介電層的厚度為0.1nm~200nm。
- 如申請專利範圍第1項所述的SOI基底的製備方法,其中,採用重氫離子對該第一基底進行離子注入時,該重氫離子的注入能量為1KeV~500KeV,該重氫離子的摻雜濃度為1.0×1014~1.0×1018/cm3。
- 如申請專利範圍第1項所述的SOI基底的製備方法,其中,採用重氫電漿浸沒離子注入對該第一基底進行離子注入時,該重氫電漿浸沒離子注入的注入能量為500eV~5KeV,該重氫電漿的摻雜濃度為1.0×1014~1.0×1018/cm3。
- 如申請專利範圍第1項所述的SOI基底的製備方法,其中,該第二介電層為氧化矽、氮化矽或氮化鋁,該第二介電層的厚度為0.05nm~10nm。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510683914.7A CN106601663B (zh) | 2015-10-20 | 2015-10-20 | Soi衬底及其制备方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201715644A TW201715644A (zh) | 2017-05-01 |
TWI587446B true TWI587446B (zh) | 2017-06-11 |
Family
ID=58456640
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW105107812A TWI587446B (zh) | 2015-10-20 | 2016-03-14 | Soi基底及其製備方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US20170110362A1 (zh) |
JP (1) | JP6174756B2 (zh) |
KR (1) | KR101903239B1 (zh) |
CN (1) | CN106601663B (zh) |
DE (1) | DE102016118509A1 (zh) |
TW (1) | TWI587446B (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107154378B (zh) * | 2016-03-03 | 2020-11-20 | 上海新昇半导体科技有限公司 | 绝缘层上顶层硅衬底及其制造方法 |
CN107845635A (zh) * | 2017-10-31 | 2018-03-27 | 长江存储科技有限责任公司 | 一种存储结构及其形成方法 |
CN111435637A (zh) * | 2019-01-11 | 2020-07-21 | 中国科学院上海微系统与信息技术研究所 | 图形化结构的soi衬底的制备方法 |
CN115881618A (zh) * | 2021-09-28 | 2023-03-31 | 苏州华太电子技术股份有限公司 | 半导体结构的制作方法以及半导体结构 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW518759B (en) * | 2000-09-01 | 2003-01-21 | Mitsubishi Electric Corp | Semiconductor device and SOI substrate |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6150239A (en) * | 1997-05-31 | 2000-11-21 | Max Planck Society | Method for the transfer of thin layers monocrystalline material onto a desirable substrate |
JPH11330438A (ja) * | 1998-05-08 | 1999-11-30 | Shin Etsu Handotai Co Ltd | Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ |
US5909627A (en) * | 1998-05-18 | 1999-06-01 | Philips Electronics North America Corporation | Process for production of thin layers of semiconductor material |
US6544862B1 (en) * | 2000-01-14 | 2003-04-08 | Silicon Genesis Corporation | Particle distribution method and resulting structure for a layer transfer process |
FR2811807B1 (fr) * | 2000-07-12 | 2003-07-04 | Commissariat Energie Atomique | Procede de decoupage d'un bloc de materiau et de formation d'un film mince |
DE10224160A1 (de) * | 2002-05-31 | 2003-12-18 | Advanced Micro Devices Inc | Eine Diffusionsbarrierenschicht in Halbleitersubstraten zur Reduzierung der Kupferkontamination von der Rückseite her |
US20060270192A1 (en) * | 2005-05-24 | 2006-11-30 | International Business Machines Corporation | Semiconductor substrate and device with deuterated buried layer |
EP1993127B1 (en) * | 2007-05-18 | 2013-04-24 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of SOI substrate |
US7781306B2 (en) * | 2007-06-20 | 2010-08-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor substrate and method for manufacturing the same |
JP5463017B2 (ja) * | 2007-09-21 | 2014-04-09 | 株式会社半導体エネルギー研究所 | 基板の作製方法 |
US7989305B2 (en) * | 2007-10-10 | 2011-08-02 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate using cluster ion |
-
2015
- 2015-10-20 CN CN201510683914.7A patent/CN106601663B/zh active Active
-
2016
- 2016-03-14 TW TW105107812A patent/TWI587446B/zh active
- 2016-05-26 US US15/166,015 patent/US20170110362A1/en not_active Abandoned
- 2016-05-31 JP JP2016108526A patent/JP6174756B2/ja active Active
- 2016-09-27 KR KR1020160123796A patent/KR101903239B1/ko active IP Right Grant
- 2016-09-29 DE DE102016118509.4A patent/DE102016118509A1/de active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW518759B (en) * | 2000-09-01 | 2003-01-21 | Mitsubishi Electric Corp | Semiconductor device and SOI substrate |
Also Published As
Publication number | Publication date |
---|---|
CN106601663B (zh) | 2019-05-31 |
DE102016118509A1 (de) | 2017-04-20 |
JP2017079323A (ja) | 2017-04-27 |
KR101903239B1 (ko) | 2018-10-01 |
CN106601663A (zh) | 2017-04-26 |
KR20170046070A (ko) | 2017-04-28 |
JP6174756B2 (ja) | 2017-08-02 |
US20170110362A1 (en) | 2017-04-20 |
TW201715644A (zh) | 2017-05-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6707106B1 (en) | Semiconductor device with tensile strain silicon introduced by compressive material in a buried oxide layer | |
TWI587446B (zh) | Soi基底及其製備方法 | |
US20220102553A1 (en) | Damage implantation of cap layer | |
US8440550B2 (en) | Method for forming strained layer with high Ge content on substrate and semiconductor structure | |
TW201916251A (zh) | 形成絕緣體上矽基底的方法 | |
JP5194508B2 (ja) | Soiウエーハの製造方法 | |
WO2013155818A1 (zh) | 一种半导体结构的制造方法 | |
CN102237396B (zh) | 半导体器件及其制造方法 | |
CN103646909A (zh) | Goi结构的制备方法 | |
CN107154378B (zh) | 绝缘层上顶层硅衬底及其制造方法 | |
KR101869641B1 (ko) | Soi 기판 및 그 제조방법 | |
CN107154347B (zh) | 绝缘层上顶层硅衬底及其制造方法 | |
TW573328B (en) | Bipolar junction transistor and manufacturing method thereof | |
JP2023526902A (ja) | 高周波用途用のセミコンダクタオンインシュレータ基板を製造するための方法 | |
JP2022046971A (ja) | Soiウェーハの製造方法及びsoiウェーハ | |
KR20110123963A (ko) | 기판 제조 방법 | |
JP2012234874A (ja) | Soiウェーハおよびsoiウェーハの製造方法 |