JP5325736B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

Info

Publication number
JP5325736B2
JP5325736B2 JP2009232163A JP2009232163A JP5325736B2 JP 5325736 B2 JP5325736 B2 JP 5325736B2 JP 2009232163 A JP2009232163 A JP 2009232163A JP 2009232163 A JP2009232163 A JP 2009232163A JP 5325736 B2 JP5325736 B2 JP 5325736B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
insulating layer
resin
support
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2009232163A
Other languages
English (en)
Japanese (ja)
Other versions
JP2011082287A (ja
JP2011082287A5 (https=
Inventor
晃明 千野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2009232163A priority Critical patent/JP5325736B2/ja
Priority to US12/897,085 priority patent/US8293576B2/en
Publication of JP2011082287A publication Critical patent/JP2011082287A/ja
Priority to US13/584,115 priority patent/US8536715B2/en
Publication of JP2011082287A5 publication Critical patent/JP2011082287A5/ja
Application granted granted Critical
Publication of JP5325736B2 publication Critical patent/JP5325736B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/014—Manufacture or treatment using batch processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/743—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2009232163A 2009-10-06 2009-10-06 半導体装置及びその製造方法 Active JP5325736B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009232163A JP5325736B2 (ja) 2009-10-06 2009-10-06 半導体装置及びその製造方法
US12/897,085 US8293576B2 (en) 2009-10-06 2010-10-04 Semiconductor device and method of manufacturing the same
US13/584,115 US8536715B2 (en) 2009-10-06 2012-08-13 Semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009232163A JP5325736B2 (ja) 2009-10-06 2009-10-06 半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
JP2011082287A JP2011082287A (ja) 2011-04-21
JP2011082287A5 JP2011082287A5 (https=) 2012-08-16
JP5325736B2 true JP5325736B2 (ja) 2013-10-23

Family

ID=43822577

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009232163A Active JP5325736B2 (ja) 2009-10-06 2009-10-06 半導体装置及びその製造方法

Country Status (2)

Country Link
US (2) US8293576B2 (https=)
JP (1) JP5325736B2 (https=)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8653542B2 (en) * 2011-01-13 2014-02-18 Tsmc Solid State Lighting Ltd. Micro-interconnects for light-emitting diodes
FR2974942B1 (fr) * 2011-05-06 2016-07-29 3D Plus Procede de fabrication de plaques reconstituees avec maintien des puces pendant leur encapsulation
JP2013038300A (ja) * 2011-08-10 2013-02-21 Fujitsu Ltd 電子装置及びその製造方法
JP2013187434A (ja) * 2012-03-09 2013-09-19 Fujitsu Ltd 半導体装置、半導体装置の製造方法、電子装置及び基板
US8901435B2 (en) 2012-08-14 2014-12-02 Bridge Semiconductor Corporation Hybrid wiring board with built-in stopper, interposer and build-up circuitry
JP5987696B2 (ja) * 2013-01-09 2016-09-07 富士通株式会社 半導体装置の製造方法
JP5662551B1 (ja) * 2013-12-20 2015-01-28 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
US9171739B1 (en) * 2014-06-24 2015-10-27 Stats Chippac Ltd. Integrated circuit packaging system with coreless substrate and method of manufacture thereof
TWI557853B (zh) * 2014-11-12 2016-11-11 矽品精密工業股份有限公司 半導體封裝件及其製法
US10269722B2 (en) 2014-12-15 2019-04-23 Bridge Semiconductor Corp. Wiring board having component integrated with leadframe and method of making the same
US9947625B2 (en) 2014-12-15 2018-04-17 Bridge Semiconductor Corporation Wiring board with embedded component and integrated stiffener and method of making the same
US10217710B2 (en) 2014-12-15 2019-02-26 Bridge Semiconductor Corporation Wiring board with embedded component and integrated stiffener, method of making the same and face-to-face semiconductor assembly using the same
US10062663B2 (en) 2015-04-01 2018-08-28 Bridge Semiconductor Corporation Semiconductor assembly with built-in stiffener and integrated dual routing circuitries and method of making the same
US10177130B2 (en) 2015-04-01 2019-01-08 Bridge Semiconductor Corporation Semiconductor assembly having anti-warping controller and vertical connecting element in stiffener
US9913385B2 (en) 2015-07-28 2018-03-06 Bridge Semiconductor Corporation Methods of making stackable wiring board having electronic component in dielectric recess
US10177090B2 (en) 2015-07-28 2019-01-08 Bridge Semiconductor Corporation Package-on-package semiconductor assembly having bottom device confined by dielectric recess
US20170133334A1 (en) * 2015-11-09 2017-05-11 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
TWI756311B (zh) * 2016-11-29 2022-03-01 新加坡商Ｐｅｐ創新私人有限公司 晶片封裝方法及封裝結構
KR102216172B1 (ko) 2017-07-14 2021-02-15 주식회사 엘지화학 절연층 제조방법 및 반도체 패키지 제조방법
US11114315B2 (en) 2017-11-29 2021-09-07 Pep Innovation Pte. Ltd. Chip packaging method and package structure
US11233028B2 (en) 2017-11-29 2022-01-25 Pep Inovation Pte. Ltd. Chip packaging method and chip structure
US11610855B2 (en) 2017-11-29 2023-03-21 Pep Innovation Pte. Ltd. Chip packaging method and package structure
US11232957B2 (en) 2017-11-29 2022-01-25 Pep Inovation Pte. Ltd. Chip packaging method and package structure
US12506055B2 (en) 2017-11-29 2025-12-23 Pep Innovation Pte. Ltd. Chip packaging method and chip structure
IT201900005156A1 (it) * 2019-04-05 2020-10-05 St Microelectronics Srl Procedimento per fabbricare leadframe per dispositivi a semiconduttore
IT201900024292A1 (it) 2019-12-17 2021-06-17 St Microelectronics Srl Procedimento per fabbricare dispositivi a semiconduttore e dispositivo a semiconduttore corrispondente
WO2022024369A1 (ja) * 2020-07-31 2022-02-03 国立大学法人東北大学 半導体装置の製造方法、半導体装置を備えた装置の製造方法、半導体装置、半導体装置を備えた装置
WO2025253502A1 (ja) * 2024-06-04 2025-12-11 三井化学Ictマテリア株式会社 電子装置の製造方法
WO2025253617A1 (ja) * 2024-06-07 2025-12-11 三井化学Ictマテリア株式会社 電子装置の製造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6734534B1 (en) 2000-08-16 2004-05-11 Intel Corporation Microelectronic substrate with integrated devices
AU2001283257A1 (en) 2000-08-16 2002-02-25 Intel Corporation Direct build-up layer on an encapsulated die package
JP2002110717A (ja) * 2000-10-02 2002-04-12 Sanyo Electric Co Ltd 回路装置の製造方法
JP2005005632A (ja) * 2003-06-16 2005-01-06 Sony Corp チップ状電子部品及びその製造方法、並びにその実装構造
KR100519816B1 (ko) * 2003-09-29 2005-10-10 삼성전기주식회사 Ｆｂａｒ 듀플렉서 소자 및 그 제조 방법
JP4541753B2 (ja) * 2004-05-10 2010-09-08 新光電気工業株式会社 電子部品実装構造の製造方法
US7687895B2 (en) * 2007-04-30 2010-03-30 Infineon Technologies Ag Workpiece with semiconductor chips and molding, semiconductor device and method for producing a workpiece with semiconductors chips
US7759163B2 (en) * 2008-04-18 2010-07-20 Infineon Technologies Ag Semiconductor module
US8338936B2 (en) * 2008-07-24 2012-12-25 Infineon Technologies Ag Semiconductor device and manufacturing method

Also Published As

Publication number Publication date
US8293576B2 (en) 2012-10-23
JP2011082287A (ja) 2011-04-21
US20120306100A1 (en) 2012-12-06
US20110079913A1 (en) 2011-04-07
US8536715B2 (en) 2013-09-17

Similar Documents

Publication Publication Date Title
JP5325736B2 (ja) 半導体装置及びその製造方法
TWI384630B (zh) 製造電子部件封裝結構之方法
JP5808586B2 (ja) インターポーザの製造方法
KR100621438B1 (ko) 감광성 폴리머를 이용한 적층 칩 패키지 및 그의 제조 방법
US10269688B2 (en) Power overlay structure and method of making same
CN101192587B (zh) 半导体器件的制造方法
JP4708399B2 (ja) 電子装置の製造方法及び電子装置
JP5532744B2 (ja) マルチチップモジュール及びマルチチップモジュールの製造方法
JP2010118373A (ja) 半導体装置の製造方法
JP5942823B2 (ja) 電子部品装置の製造方法、電子部品装置及び電子装置
JP2014063974A (ja) チップ積層体、該チップ積層体を備えた半導体装置、及び半導体装置の製造方法
JP2011171614A (ja) 半導体装置及び半導体装置の製造方法
JP2004273604A (ja) 半導体装置と半導体電子部品との製造方法と半導体電子部品
CN101252092B (zh) 多芯片封装结构及其制作方法
JP2001127095A (ja) 半導体装置及びその製造方法
JP2004165277A (ja) 電子部品実装構造及びその製造方法
JP2012009655A (ja) 半導体パッケージおよび半導体パッケージの製造方法
TWI776164B (zh) 半導體裝置及其製造方法
JP5186741B2 (ja) 回路基板及び半導体装置
JP2011082404A (ja) 半導体装置の製造方法
JP3825370B2 (ja) 半導体装置の製造方法
JP2002252309A (ja) 半導体チップのパッケージ構造及びパッケージ方法
JP2004319656A (ja) ウエハーレベルｃｓｐの製造方法
JP2004193274A (ja) 電子部品実装構造及びその製造方法
JP5838312B2 (ja) インターポーザおよびその製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120629

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20120629

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20121102

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121113

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130104

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130702

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130722

R150 Certificate of patent or registration of utility model

Ref document number: 5325736

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150