JP5313626B2 - 電子部品内蔵基板及びその製造方法 - Google Patents
電子部品内蔵基板及びその製造方法 Download PDFInfo
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- JP5313626B2 JP5313626B2 JP2008275290A JP2008275290A JP5313626B2 JP 5313626 B2 JP5313626 B2 JP 5313626B2 JP 2008275290 A JP2008275290 A JP 2008275290A JP 2008275290 A JP2008275290 A JP 2008275290A JP 5313626 B2 JP5313626 B2 JP 5313626B2
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- layer
- electronic component
- wiring
- semiconductor chip
- insulating layer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008275290A JP5313626B2 (ja) | 2008-10-27 | 2008-10-27 | 電子部品内蔵基板及びその製造方法 |
| US12/605,736 US8309860B2 (en) | 2008-10-27 | 2009-10-26 | Electronic component built-in substrate and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008275290A JP5313626B2 (ja) | 2008-10-27 | 2008-10-27 | 電子部品内蔵基板及びその製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2010103398A JP2010103398A (ja) | 2010-05-06 |
| JP2010103398A5 JP2010103398A5 (enExample) | 2011-09-22 |
| JP5313626B2 true JP5313626B2 (ja) | 2013-10-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008275290A Active JP5313626B2 (ja) | 2008-10-27 | 2008-10-27 | 電子部品内蔵基板及びその製造方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US8309860B2 (enExample) |
| JP (1) | JP5313626B2 (enExample) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9219023B2 (en) * | 2010-01-19 | 2015-12-22 | Globalfoundries Inc. | 3D chip stack having encapsulated chip-in-chip |
| JP5692217B2 (ja) * | 2010-03-16 | 2015-04-01 | 日本電気株式会社 | 機能素子内蔵基板 |
| JP2012009586A (ja) * | 2010-06-24 | 2012-01-12 | Shinko Electric Ind Co Ltd | 配線基板、半導体装置及び配線基板の製造方法 |
| TWI508245B (zh) * | 2010-10-06 | 2015-11-11 | 矽品精密工業股份有限公司 | 嵌埋晶片之封裝件及其製法 |
| US8927388B2 (en) * | 2012-11-15 | 2015-01-06 | United Microelectronics Corp. | Method of fabricating dielectric layer and shallow trench isolation |
| US9992863B2 (en) * | 2013-08-23 | 2018-06-05 | Apple Inc. | Connector inserts and receptacle tongues formed using printed circuit boards |
| TWI525863B (zh) * | 2013-09-10 | 2016-03-11 | 菱生精密工業股份有限公司 | The wafer package structure is packaged using a wafer package structure A module, and a method of manufacturing the wafer package structure |
| EP3058586B1 (en) * | 2013-10-16 | 2020-11-11 | Intel Corporation | Integrated circuit package substrate |
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