JP5259978B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP5259978B2
JP5259978B2 JP2007119386A JP2007119386A JP5259978B2 JP 5259978 B2 JP5259978 B2 JP 5259978B2 JP 2007119386 A JP2007119386 A JP 2007119386A JP 2007119386 A JP2007119386 A JP 2007119386A JP 5259978 B2 JP5259978 B2 JP 5259978B2
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lead
semiconductor device
groove
manufacturing
protective member
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Japanese (ja)
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JP2008112961A5 (https=
JP2008112961A (ja
Inventor
尚司 安永
泰正 糟谷
基治 ▲芳▼我
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Rohm Co Ltd
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Rohm Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

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  • Lead Frames For Integrated Circuits (AREA)
JP2007119386A 2006-10-04 2007-04-27 半導体装置の製造方法 Active JP5259978B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007119386A JP5259978B2 (ja) 2006-10-04 2007-04-27 半導体装置の製造方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2006273257 2006-10-04
JP2006273257 2006-10-04
JP2007119386A JP5259978B2 (ja) 2006-10-04 2007-04-27 半導体装置の製造方法

Related Child Applications (1)

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JP2012253597A Division JP5702763B2 (ja) 2006-10-04 2012-11-19 半導体装置

Publications (3)

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JP2008112961A JP2008112961A (ja) 2008-05-15
JP2008112961A5 JP2008112961A5 (https=) 2010-05-13
JP5259978B2 true JP5259978B2 (ja) 2013-08-07

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JP2007119386A Active JP5259978B2 (ja) 2006-10-04 2007-04-27 半導体装置の製造方法

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Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009032253B4 (de) 2009-07-08 2022-11-17 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Elektronisches Bauteil
JP5534559B2 (ja) * 2010-03-15 2014-07-02 サンケン電気株式会社 モールドパッケージの製造方法
WO2012009848A1 (en) * 2010-07-20 2012-01-26 Mediatek (Shenzhen) Inc. Pre-solder method and rework method for multi-row qfn chip
US8841758B2 (en) * 2012-06-29 2014-09-23 Freescale Semiconductor, Inc. Semiconductor device package and method of manufacture
CN104241149B (zh) * 2013-06-18 2016-12-28 常州银河世纪微电子有限公司 一种半导体芯片的焊接方法
HK1208957A1 (en) 2014-03-27 2016-03-18 瑞萨电子株式会社 Manufacturing method of semiconductor device and semiconductor device
JP2016219520A (ja) * 2015-05-18 2016-12-22 Ｔｏｗａ株式会社 半導体装置及びその製造方法
JP2017147272A (ja) * 2016-02-15 2017-08-24 ローム株式会社 半導体装置およびその製造方法、ならびに、半導体装置の製造に使用されるリードフレーム中間体
JP6840466B2 (ja) 2016-03-08 2021-03-10 株式会社アムコー・テクノロジー・ジャパン 半導体パッケージ及び半導体パッケージの製造方法
US20170294367A1 (en) * 2016-04-07 2017-10-12 Microchip Technology Incorporated Flat No-Leads Package With Improved Contact Pins
JP6744149B2 (ja) * 2016-06-20 2020-08-19 ローム株式会社 半導体装置およびその製造方法
US10636729B2 (en) * 2017-06-19 2020-04-28 Texas Instruments Incorporated Integrated circuit package with pre-wetted contact sidewall surfaces
JP7037368B2 (ja) * 2018-01-09 2022-03-16 ローム株式会社 半導体装置および半導体装置の製造方法
KR101999594B1 (ko) 2018-02-23 2019-10-01 해성디에스 주식회사 반도체 패키지 기판 제조방법, 이를 이용하여 제조된 반도체 패키지 기판, 반도체 패키지 제조방법 및 이를 이용하여 제조된 반도체 패키지
JP7199214B2 (ja) * 2018-12-17 2023-01-05 ローム株式会社 半導体装置および電力変換装置
DE112020000826T5 (de) 2019-02-15 2021-10-28 Ase Japan Co., Ltd. Halbleiterbauteil und verfahren zum herstellen eines halbleiterbauteils
KR102119142B1 (ko) 2019-10-01 2020-06-05 해성디에스 주식회사 웨이퍼 레벨 패키지의 캐리어를 리드 프레임으로 제작하는 방법
CN112750796A (zh) * 2019-10-30 2021-05-04 新光电气工业株式会社 半导体装置以及半导体装置的制造方法
JP7121788B2 (ja) 2020-11-17 2022-08-18 Ｔｏｗａ株式会社 切断装置、及び、切断品の製造方法
JP7450575B2 (ja) * 2021-03-18 2024-03-15 株式会社東芝 半導体装置及びその製造方法
JPWO2023058487A1 (https=) 2021-10-04 2023-04-13
JP7798568B2 (ja) * 2021-12-29 2026-01-14 株式会社ディスコ パッケージ基板の加工方法
JPWO2024203110A1 (https=) * 2023-03-24 2024-10-03

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6396947A (ja) * 1986-10-13 1988-04-27 Mitsubishi Electric Corp 半導体装置用リ−ドフレ−ム
JPH0837265A (ja) * 1994-07-26 1996-02-06 Hitachi Ltd 樹脂封止型半導体装置の製法
JP3642911B2 (ja) * 1997-02-05 2005-04-27 大日本印刷株式会社 リードフレーム部材とその製造方法
JP3877409B2 (ja) * 1997-12-26 2007-02-07 三洋電機株式会社 半導体装置の製造方法
JP2000294715A (ja) * 1999-04-09 2000-10-20 Hitachi Ltd 半導体装置及び半導体装置の製造方法
JP2001320007A (ja) * 2000-05-09 2001-11-16 Dainippon Printing Co Ltd 樹脂封止型半導体装置用フレーム
JP2002289756A (ja) * 2001-03-26 2002-10-04 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP2004023007A (ja) * 2002-06-20 2004-01-22 Sony Corp 半導体パッケージ用リードフレーム及び半導体パッケージ並びに半導体パッケージの製造方法。
JP4159348B2 (ja) * 2002-12-20 2008-10-01 三洋電機株式会社 回路装置の製造方法
JP4187065B2 (ja) * 2003-01-17 2008-11-26 日東電工株式会社 粘着テープ貼付け方法およびその装置
JP3789443B2 (ja) * 2003-09-01 2006-06-21 Ｎｅｃエレクトロニクス株式会社 樹脂封止型半導体装置
JP4330980B2 (ja) * 2003-11-19 2009-09-16 ローム株式会社 リードフレームの製造方法およびそれを用いた半導体装置の製造方法、ならびにリードフレームおよびそれを用いた半導体装置
JP2005166943A (ja) * 2003-12-02 2005-06-23 Sony Corp リードフレーム、それを用いた半導体装置の製造におけるワイヤーボンディング方法及び樹脂封止型半導体装置
JP4125668B2 (ja) * 2003-12-19 2008-07-30 日東電工株式会社 半導体装置の製造方法
JP4522802B2 (ja) * 2004-09-15 2010-08-11 大日本印刷株式会社 Ｉｃモジュール

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