JP5241485B2 - Ｓｏｃ用途のための高密度トレンチ・ベース不揮発性ランダム・アクセスｓｏｎｏｓメモリ・セルの構造及びこれを製造する方法 - Google Patents

Ｓｏｃ用途のための高密度トレンチ・ベース不揮発性ランダム・アクセスｓｏｎｏｓメモリ・セルの構造及びこれを製造する方法 Download PDF

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JP5241485B2
JP5241485B2 JP2008506611A JP2008506611A JP5241485B2 JP 5241485 B2 JP5241485 B2 JP 5241485B2 JP 2008506611 A JP2008506611 A JP 2008506611A JP 2008506611 A JP2008506611 A JP 2008506611A JP 5241485 B2 JP5241485 B2 JP 5241485B2
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trench
select
transistor
gate
memory
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JP2008506611A
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JP2008536336A (ja
JP2008536336A5 (enExample
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マンデルマン、ジャック
ホー、ハーバート
ニン、ターク
オタニ、ヨーイチ
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/693—Vertical IGFETs having charge trapping gate insulators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts

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  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
JP2008506611A 2005-04-12 2006-04-12 Ｓｏｃ用途のための高密度トレンチ・ベース不揮発性ランダム・アクセスｓｏｎｏｓメモリ・セルの構造及びこれを製造する方法 Expired - Fee Related JP5241485B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/907,686 2005-04-12
US10/907,686 US7816728B2 (en) 2005-04-12 2005-04-12 Structure and method of fabricating high-density trench-based non-volatile random access SONOS memory cells for SOC applications
PCT/US2006/013561 WO2006110781A2 (en) 2005-04-12 2006-04-12 Structure and method of fabricating high-density, trench-based non-volatile random access sonos memory cells for soc applications

Publications (3)

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JP2008536336A JP2008536336A (ja) 2008-09-04
JP2008536336A5 JP2008536336A5 (enExample) 2009-02-19
JP5241485B2 true JP5241485B2 (ja) 2013-07-17

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US (2) US7816728B2 (enExample)
EP (1) EP1869709A4 (enExample)
JP (1) JP5241485B2 (enExample)
CN (1) CN101147263A (enExample)
TW (1) TW200707765A (enExample)
WO (1) WO2006110781A2 (enExample)

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Also Published As

Publication number Publication date
WO2006110781A3 (en) 2007-04-19
US20060226474A1 (en) 2006-10-12
WO2006110781A2 (en) 2006-10-19
TW200707765A (en) 2007-02-16
CN101147263A (zh) 2008-03-19
US20080057647A1 (en) 2008-03-06
EP1869709A4 (en) 2008-07-16
US7816728B2 (en) 2010-10-19
JP2008536336A (ja) 2008-09-04
EP1869709A2 (en) 2007-12-26
US7807526B2 (en) 2010-10-05

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