Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
  • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
  • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
  • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
  • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
  • H10D30/693—Vertical IGFETs having charge trapping gate insulators
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
  • H10D89/10—Integrated device layouts

Definitions

• a memory transistor comprising an oxide/nitride/oxide gate dielectric located on a surface of said semiconductor substrate and adjoining said selected trench structures.
• the present invention also provides a method of fabricating the same.
• the method used in forming the non-volatile random access memory cell described above comprises:
• a semiconductor substrate including at least one array region that contains a plurality of trench structures having a depth from about 1 to about 2 ⁇ m, each trench structure including a lower portion comprising a select transistor having a channel located on vertical sidewalls of said trench structure, and an upper portion comprising a memory transistor including an oxide/nitride/oxide gate dielectric;
• the lithographic step includes exposing the applied resist to a desired pattern (i.e., a trench pattern) of radiation and developing the exposed resist utilizing a conventional developer.
• a desired pattern i.e., a trench pattern
• the pattern is first transferred to the oxide hardmask utilizing an anisotropic etching process such as reactive ion etching, ion beam etching, plasma etching or laser ablation.
• the resist can be removed after the trench pattern has been transferred to the oxide hardmask or it can remain on the structure during the transfer of the pattern from the hardmask to the pad stack 14 and then to the semiconductor substrate 12 and thereafter removed, as described above.
• These later pattern transfer steps can be performed utilizing the same etching process as described above.
• a plurality of trench structure 18 (two of which are shown in FIG. 1) having a depth, as measured from the upper surface of the semiconductor substrate 12, from about 1 to about 2 ⁇ m, are formed into the semiconductor substrate 12 in the array region 100.
• the oxide hardmask used to define the trench structures 18 is removed utilizing a conventional stripping process that selectively removes oxide, stopping on the nitride surface of the pad stack 14.
• the order of the implants used in forming the source diffusion 20 and the select gate channel 22 is not critical to the present invention. Typically, however, the source diffusion implant occurs prior to the select channel implant.
• the conductive material 26 comprises a metal, a metal alloy, a metal suicide, polysilicon that is doped, or a combination thereof, including multilayers.
• the conductive material 26 is polysilicon that is doped with the same polarity as the source diffusion 20.
• the conductive material 26 acts as the gate of the select transistor 28.
• the conductive material 26 is formed utilizing a conventional deposition process. When doped polysilicon is used as the conductive material 26, it is preferred that an in-situ doping deposition process be employed.
• the recessing of the conductive material 26 is performed utilizing an anisotropic etching process such as reactive ion etching.
• trench isolation regions 30 are formed into the array region 100 and the periphery array region 102 using conventional processes well known in the art including, for example forming trenches within the substrate 12 by lithography and etching, and filling the trench with a trench dielectric such as an oxide. Note that typically the depth of the trenches used in forming the isolation trenches is shallower than the trench structure 18 including the select transistor 28. In the drawing, the trench isolation region 30 in the array region 100 separates two selected trench structures including select transistors 28.
• Vt of the memory device is negative (due to trapped holes in the ONO) and the device is on; therefore a "1 " has been written into the cell (i.e. a depletion mode planar memory device).

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• Non-Volatile Memory (AREA)
• Semiconductor Memories (AREA)

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• 2005
  • 2005-04-12 US US10/907,686 patent/US7816728B2/en not_active Expired - Lifetime
• 2006
  • 2006-04-10 TW TW095112633A patent/TW200707765A/zh unknown
  • 2006-04-12 JP JP2008506611A patent/JP5241485B2/ja not_active Expired - Fee Related
  • 2006-04-12 CN CNA2006800097797A patent/CN101147263A/zh active Pending
  • 2006-04-12 EP EP06749815A patent/EP1869709A4/en not_active Withdrawn
  • 2006-04-12 WO PCT/US2006/013561 patent/WO2006110781A2/en not_active Ceased
• 2007
  • 2007-10-30 US US11/928,615 patent/US7807526B2/en not_active Expired - Fee Related

Non-Patent Citations (1)

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