JP5232394B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP5232394B2
JP5232394B2 JP2007049654A JP2007049654A JP5232394B2 JP 5232394 B2 JP5232394 B2 JP 5232394B2 JP 2007049654 A JP2007049654 A JP 2007049654A JP 2007049654 A JP2007049654 A JP 2007049654A JP 5232394 B2 JP5232394 B2 JP 5232394B2
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JP
Japan
Prior art keywords
lead
die pad
support portion
sealing resin
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2007049654A
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English (en)
Japanese (ja)
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JP2008218469A (ja
JP2008218469A5 (enExample
Inventor
基治 ▲芳▼我
尚司 安永
泰正 糟谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP2007049654A priority Critical patent/JP5232394B2/ja
Publication of JP2008218469A publication Critical patent/JP2008218469A/ja
Publication of JP2008218469A5 publication Critical patent/JP2008218469A5/ja
Application granted granted Critical
Publication of JP5232394B2 publication Critical patent/JP5232394B2/ja
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Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP2007049654A 2007-02-28 2007-02-28 半導体装置の製造方法 Active JP5232394B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007049654A JP5232394B2 (ja) 2007-02-28 2007-02-28 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007049654A JP5232394B2 (ja) 2007-02-28 2007-02-28 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2008218469A JP2008218469A (ja) 2008-09-18
JP2008218469A5 JP2008218469A5 (enExample) 2010-03-18
JP5232394B2 true JP5232394B2 (ja) 2013-07-10

Family

ID=39838216

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007049654A Active JP5232394B2 (ja) 2007-02-28 2007-02-28 半導体装置の製造方法

Country Status (1)

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JP (1) JP5232394B2 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
MY155671A (en) 2010-01-29 2015-11-13 Toshiba Kk LED package and method for manufacturing same
JP5010693B2 (ja) 2010-01-29 2012-08-29 株式会社東芝 Ｌｅｄパッケージ
JP2011159767A (ja) 2010-01-29 2011-08-18 Toshiba Corp Ｌｅｄパッケージ及びその製造方法
JP5383611B2 (ja) 2010-01-29 2014-01-08 株式会社東芝 Ｌｅｄパッケージ
JP5010716B2 (ja) 2010-01-29 2012-08-29 株式会社東芝 Ｌｅｄパッケージ
JP4951090B2 (ja) 2010-01-29 2012-06-13 株式会社東芝 Ｌｅｄパッケージ
JP2011165833A (ja) 2010-02-08 2011-08-25 Toshiba Corp Ｌｅｄモジュール
JP2011216615A (ja) * 2010-03-31 2011-10-27 Renesas Electronics Corp 半導体装置の製造方法
KR101450216B1 (ko) * 2012-08-24 2014-10-14 주식회사 씨티랩 반도체 소자 구조물을 제조하는 방법
JP7144157B2 (ja) 2018-03-08 2022-09-29 エイブリック株式会社 半導体装置およびその製造方法
JP7089388B2 (ja) * 2018-03-29 2022-06-22 ローム株式会社 半導体装置および半導体装置の製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3304705B2 (ja) * 1995-09-19 2002-07-22 セイコーエプソン株式会社 チップキャリアの製造方法
JP2000294715A (ja) * 1999-04-09 2000-10-20 Hitachi Ltd 半導体装置及び半導体装置の製造方法
JP2001320007A (ja) * 2000-05-09 2001-11-16 Dainippon Printing Co Ltd 樹脂封止型半導体装置用フレーム
JP3679687B2 (ja) * 2000-06-08 2005-08-03 三洋電機株式会社 混成集積回路装置
JP2003023134A (ja) * 2001-07-09 2003-01-24 Hitachi Ltd 半導体装置およびその製造方法
JP4159348B2 (ja) * 2002-12-20 2008-10-01 三洋電機株式会社 回路装置の製造方法
US7553700B2 (en) * 2004-05-11 2009-06-30 Gem Services, Inc. Chemical-enhanced package singulation process

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Publication number Publication date
JP2008218469A (ja) 2008-09-18

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