JP5231382B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
JP5231382B2
JP5231382B2 JP2009269789A JP2009269789A JP5231382B2 JP 5231382 B2 JP5231382 B2 JP 5231382B2 JP 2009269789 A JP2009269789 A JP 2009269789A JP 2009269789 A JP2009269789 A JP 2009269789A JP 5231382 B2 JP5231382 B2 JP 5231382B2
Authority
JP
Japan
Prior art keywords
wiring
cap
package
cavity
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2009269789A
Other languages
English (en)
Japanese (ja)
Other versions
JP2011114192A5 (enExample
JP2011114192A (ja
Inventor
朋治 藤井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2009269789A priority Critical patent/JP5231382B2/ja
Priority to US12/953,808 priority patent/US8592959B2/en
Publication of JP2011114192A publication Critical patent/JP2011114192A/ja
Publication of JP2011114192A5 publication Critical patent/JP2011114192A5/ja
Application granted granted Critical
Publication of JP5231382B2 publication Critical patent/JP5231382B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
    • H10W40/228—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area the projecting parts being wire-shaped or pin-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H10W76/15—Containers comprising an insulating or insulated base
    • H10W76/153—Containers comprising an insulating or insulated base having interconnections in passages through the insulating or insulated base
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/60—Seals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2009269789A 2009-11-27 2009-11-27 半導体装置 Active JP5231382B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009269789A JP5231382B2 (ja) 2009-11-27 2009-11-27 半導体装置
US12/953,808 US8592959B2 (en) 2009-11-27 2010-11-24 Semiconductor device mounted on a wiring board having a cap

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009269789A JP5231382B2 (ja) 2009-11-27 2009-11-27 半導体装置

Publications (3)

Publication Number Publication Date
JP2011114192A JP2011114192A (ja) 2011-06-09
JP2011114192A5 JP2011114192A5 (enExample) 2012-09-20
JP5231382B2 true JP5231382B2 (ja) 2013-07-10

Family

ID=44068235

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009269789A Active JP5231382B2 (ja) 2009-11-27 2009-11-27 半導体装置

Country Status (2)

Country Link
US (1) US8592959B2 (enExample)
JP (1) JP5231382B2 (enExample)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011128140A (ja) * 2009-11-19 2011-06-30 Dainippon Printing Co Ltd センサデバイス及びその製造方法
JP5827476B2 (ja) * 2011-03-08 2015-12-02 株式会社東芝 半導体モジュール及びその製造方法
US9125311B2 (en) * 2011-09-26 2015-09-01 Nec Corporation Hollow sealing structure
KR20130041645A (ko) * 2011-10-17 2013-04-25 삼성전기주식회사 인쇄회로기판
FR2995721B1 (fr) 2012-09-17 2014-11-21 Commissariat Energie Atomique Capot pour dispositif a rainure et a puce, dispositif equipe du capot, assemblage du dispositif avec un element filaire et procede de fabrication
JP2014072346A (ja) * 2012-09-28 2014-04-21 Nec Corp 中空封止構造及び中空封止構造の製造方法
JP6383147B2 (ja) * 2013-12-10 2018-08-29 日本特殊陶業株式会社 パッケージ
JP6247106B2 (ja) * 2014-02-03 2017-12-13 新光電気工業株式会社 半導体装置
US9693445B2 (en) * 2015-01-30 2017-06-27 Avago Technologies General Ip (Singapore) Pte. Ltd. Printed circuit board with thermal via
US10916520B2 (en) 2015-06-10 2021-02-09 Mitsubishi Electric Corporation Semiconductor device, and method of manufacturing the same
JP2017038019A (ja) * 2015-08-13 2017-02-16 富士電機株式会社 半導体装置
JP6342591B2 (ja) 2015-11-25 2018-06-13 京セラ株式会社 電子部品収納用パッケージ、電子装置および電子モジュール
JP6680880B2 (ja) * 2015-11-30 2020-04-15 ダブリュ．エル．ゴア アンド アソシエイツ，インコーポレイティドＷ．Ｌ． Ｇｏｒｅ ＆ Ａｓｓｏｃｉａｔｅｓ， Ｉｎｃｏｒｐｏｒａｔｅｄ ダイのための保護環境バリアー
US9870967B2 (en) * 2016-03-10 2018-01-16 Analog Devices, Inc. Plurality of seals for integrated device package
US9887143B2 (en) * 2016-03-25 2018-02-06 Infineon Technologies Americas Corp. Surface mount device package having improved reliability
US10177064B2 (en) * 2016-08-26 2019-01-08 Qorvo Us, Inc. Air cavity package
US10269669B2 (en) * 2016-12-14 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of forming the same
US10629545B2 (en) * 2017-03-09 2020-04-21 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device
FR3069406A1 (fr) * 2017-07-18 2019-01-25 Stmicroelectronics (Grenoble 2) Sas Boitier electronique et procede de fabrication
WO2019093269A1 (ja) * 2017-11-09 2019-05-16 Ｎｇｋエレクトロデバイス株式会社 蓋体および電子装置
JP6929210B2 (ja) * 2017-12-11 2021-09-01 株式会社ブリヂストン タイヤ
US10867955B2 (en) * 2018-09-27 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure having adhesive layer surrounded dam structure
CN111193492B (zh) * 2018-11-14 2023-08-15 天津大学 封装结构、半导体器件、电子设备
WO2020218335A1 (ja) * 2019-04-22 2020-10-29 京セラ株式会社 電子部品収納用パッケージ、電子装置、および電子モジュール
US20200411407A1 (en) * 2019-06-26 2020-12-31 Intel Corporation Integrated circuit packages with solder thermal interface material
KR102430750B1 (ko) * 2019-08-22 2022-08-08 스템코 주식회사 회로 기판 및 그 제조 방법
CN115312549A (zh) * 2021-05-05 2022-11-08 胜丽国际股份有限公司 传感器封装结构
US11948893B2 (en) * 2021-12-21 2024-04-02 Qorvo Us, Inc. Electronic component with lid to manage radiation feedback

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58106947A (ja) 1981-12-21 1983-06-25 Fujitsu Ltd 光センサ
JPS58177946A (ja) 1982-04-13 1983-10-18 Mitsui Toatsu Chem Inc ３，３′−ジアミノベンゾフエノンの製造方法
JPS58106947U (ja) * 1982-01-14 1983-07-21 株式会社日立製作所 半導体の実装構造
JPS58177946U (ja) * 1982-05-21 1983-11-28 富士通株式会社 Ｉｃ収容「きよう」体
JPH0216758A (ja) * 1988-07-05 1990-01-19 Nec Corp 半導体装置用キャップ
JPH03114247A (ja) * 1989-09-28 1991-05-15 Nec Yamagata Ltd パッケージ型半導体装置
JP2906756B2 (ja) * 1991-08-06 1999-06-21 イビデン株式会社 電子部品搭載用基板
US5311402A (en) * 1992-02-14 1994-05-10 Nec Corporation Semiconductor device package having locating mechanism for properly positioning semiconductor device within package
JPH0746709A (ja) 1993-08-04 1995-02-14 Fuji Heavy Ind Ltd パラレルハイブリッド車のバッテリ充放電制御装置
JPH09232551A (ja) * 1996-02-26 1997-09-05 Toshiba Corp 光電変換装置
JP3859340B2 (ja) * 1998-01-06 2006-12-20 三菱電機株式会社 半導体装置
JP3733114B2 (ja) * 2000-07-25 2006-01-11 株式会社メヂアナ電子 プラスチックパッケージベース及びエアキャビティ型パッケージ
JP3533159B2 (ja) * 2000-08-31 2004-05-31 Ｎｅｃ化合物デバイス株式会社 半導体装置及びその製造方法
US7064048B2 (en) * 2003-10-17 2006-06-20 United Microelectronics Corp. Method of forming a semi-insulating region
DE102004021365A1 (de) * 2004-03-16 2005-10-06 Robert Bosch Gmbh Gehäuse für eine elektronische Schaltung und Verfahren zum Abdichten des Gehäuses
JP4511278B2 (ja) * 2004-08-11 2010-07-28 三洋電機株式会社 セラミックパッケージ
TWI299552B (en) * 2006-03-24 2008-08-01 Advanced Semiconductor Eng Package structure

Also Published As

Publication number Publication date
US8592959B2 (en) 2013-11-26
JP2011114192A (ja) 2011-06-09
US20110127655A1 (en) 2011-06-02

Similar Documents

Publication Publication Date Title
JP5231382B2 (ja) 半導体装置
US8373997B2 (en) Semiconductor device
CN109411423B (zh) 半导体封装件及包括半导体封装件的电子装置
US8497156B2 (en) Semiconductor device and manufacturing method of the same
KR100339044B1 (ko) 볼그리드어레이 반도체패키지 및 그 제조방법
US6400010B1 (en) Substrate including a metal portion and a resin portion
US7518250B2 (en) Semiconductor device and a method for manufacturing of the same
KR100374241B1 (ko) 반도체 장치 및 그 제조 방법
KR100698526B1 (ko) 방열층을 갖는 배선기판 및 그를 이용한 반도체 패키지
KR20080031119A (ko) 반도체 장치
TWI785515B (zh) 半導體封裝體及包含半導體封裝體之裝置
KR101301782B1 (ko) 반도체 패키지 및 그 제조 방법
US11296005B2 (en) Integrated device package including thermally conductive element and method of manufacturing same
CN114051770A (zh) 无线通信模块
CN112117262A (zh) 半导体封装件
JP2004071597A (ja) 半導体モジュール
JP4494249B2 (ja) 半導体装置
JP3912445B2 (ja) 半導体装置
JPH09330994A (ja) 半導体装置
JP2019050297A (ja) 半導体装置
JP2004153179A (ja) 半導体装置および電子装置
JPWO2006001087A1 (ja) 半導体装置
CN113964092B (zh) 封装结构及其制备方法
KR100473336B1 (ko) 반도체패키지
US20030057569A1 (en) Semiconductor device

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120803

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20120803

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130117

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130122

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130220

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130312

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130321

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20160329

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 5231382

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150