JP5205741B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5205741B2 JP5205741B2 JP2006308159A JP2006308159A JP5205741B2 JP 5205741 B2 JP5205741 B2 JP 5205741B2 JP 2006308159 A JP2006308159 A JP 2006308159A JP 2006308159 A JP2006308159 A JP 2006308159A JP 5205741 B2 JP5205741 B2 JP 5205741B2
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Images
Classifications
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/32051—Deposition of metallic or metal-silicide layers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
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Description
本発明の実施の形態について説明する前に、本発明に至るまでの経緯について説明する。
図6〜図17は、本実施形態に係る半導体装置の製造途中の断面図である。
図18〜図23は、本発明の第2実施形態に係る半導体装置の製造途中の断面図である。なお、これらの図において第1実施形態で説明した要素には第1実施形態と同じ符号を付し、以下ではその説明を省略する。
図24は、本実施形態に係る半導体装置の断面図である。
図25〜図32は、本実施形態に係る半導体装置の製造途中の断面図である。なお、これらの図において、第1実施形態で説明した要素には第1実施形態と同じ符号を付し、以下ではその説明を省略する。
前記半導体基板の上方に形成され、前記不純物拡散領域の上方にホールを備えた層間絶縁膜と、
前記ホール内に形成され、前記不純物拡散領域と電気的に接続された導電性プラグと、
前記導電性プラグ上とその周囲の前記層間絶縁膜上とに形成された導電性酸素バリア膜と、
前記導電性酸素バリア膜上に形成された導電性拡散防止膜と、
前記導電性拡散防止膜の上に形成され、プラチナ又はパラジウムが上面に表出する下部電極、強誘電体材料よりなるキャパシタ誘電体膜、及び上部電極を備えたキャパシタとを有し、
前記導電性拡散防止膜が、前記キャパシタ誘電体膜の構成元素の拡散を防止する酸化物以外の導電性材料よりなることを特徴とする半導体装置。
前記導電性拡散防止膜は、前記キャパシタ誘電体膜のAサイトの元素の拡散を防止することを特徴とする付記1に記載の半導体装置。
前記導電性拡散防止膜と前記導電性酸素バリア膜との界面に鉛が存在しないことを特徴とする付記2に記載の半導体装置。
前記半導体基板の上方に第1層間絶縁膜を形成する工程と、
前記第1不純物拡散領域の上方の前記第1層間絶縁膜に第1ホールを形成する工程と、
前記ホール内に、前記第1不純物拡散領域と電気的に接続された第1導電性プラグを形成する工程と、
前記第1層間絶縁膜と前記第1導電性プラグのそれぞれの上に導電性酸素バリア膜を形成する工程と、
前記導電性酸素バリア膜の上に導電性拡散防止膜を形成する工程と、
前記導電性拡散防止膜の上に、プラチナ又はパラジウムが上面に表出する第1導電膜を形成する工程と、
前記第1導電膜の上に強誘電体膜を形成する工程と、
前記強誘電体膜の上に第2導電膜を形成する工程と、
前記導電性拡散防止膜、前記第1導電膜、前記強誘電体膜、及び前記第2導電膜をパターニングすることにより、下部電極、キャパシタ誘電体膜、及び上部電極を備えたキャパシタを形成すると共に、前記導電性拡散防止膜を前記下部電極の下に島状に残す工程と、
前記下部電極で覆われていない領域の前記導電性酸素バリア膜を除去する工程とを有し、
前記導電性拡散防止膜として、前記キャパシタ誘電体膜の構成元素の拡散を防止する酸化物以外の導電性材料よりなる膜を形成することを特徴とする半導体装置の製造方法。
前記第1導電膜の上に、スパッタ法又はゾル・ゲル法により第1強誘電体膜を形成する工程と、
前記第1強誘電体膜をアニールして結晶化する工程と、
前記第1強誘電体膜の上にMOCVD法により第2強誘電体膜を形成し、該第2強誘電体膜と前記第1強誘電体膜とで前記強誘電体膜を構成する工程とを有することを特徴とする付記12に記載の半導体装置の製造方法。
前記導電性拡散防止膜として、前記キャパシタ誘電体膜のAサイトの元素の拡散を防止する膜を形成することを特徴とする付記12に記載の半導体装置の製造方法。
前記強誘電体膜の上に第1導電性酸化金属膜を形成する工程と、
前記第1導電性酸化金属膜に対してアニールを行う工程と、
前記アニールの後、前記第1導電性酸化金属膜の上に、該第1導電性酸化金属膜よりも酸素含有量が多い第2導電性酸化金属膜を形成する工程とを有することを特徴とする付記12に記載の半導体装置の製造方法。
前記第1導電性プラグの上の前記下地絶縁膜に第2ホールを形成する工程と、
前記第2ホールに、前記第1導電性プラグと電気的に接続された第2導電性プラグを形成する工程と、
前記第2導電性プラグと前記下地絶縁膜のそれぞれの上に平坦化用導電膜を形成する工程と、
前記平坦化用導電膜を平坦化する工程とを更に有し、
前記導電性酸素バリア膜を形成する工程において、前記平坦化された平坦化用導電膜の上に前記導電性酸素バリア膜を形成することを特徴とする付記12に記載の半導体装置の製造方法。
前記キャパシタを覆う第2層間絶縁膜を形成する工程と、
前記第2不純物拡散領域の上の前記第1層間絶縁膜及び前記第2層間絶縁膜に第3ホールを形成する工程と、
前記第3ホール内に、前記第2不純物拡散領域と電気的に接続された第3導電性プラグを形成する工程とを更に有することを特徴とする付記12に記載の半導体装置の製造方法。
Claims (4)
- 半導体基板に第1不純物拡散領域を形成する工程と、
前記半導体基板の上方に第1層間絶縁膜を形成する工程と、
前記第1不純物拡散領域の上方の前記第1層間絶縁膜に第1ホールを形成する工程と、
前記ホール内に、前記第1不純物拡散領域と電気的に接続された第1導電性プラグを形成する工程と、
前記第1層間絶縁膜と前記第1導電性プラグのそれぞれの上に、材料として窒化チタンアルミニウム、酸窒化チタンアルミニウム、窒化タンタルアルミニウム、又は酸窒化タンタルアルミニウムのいずれかを用いた導電性酸素バリア膜を形成する工程と、
前記導電性酸素バリア膜の上に導電性拡散防止膜を形成する工程と、
前記導電性拡散防止膜の上に、プラチナ又はパラジウムが上面に表出する第1導電膜を形成する工程と、
前記第1導電膜の上に、スパッタ法又はゾル・ゲル法により第1強誘電体膜を形成する工程と、
前記第1強誘電体膜をアニールして結晶化する工程と、
前記第1強誘電体膜の上にMOCVD法により第2強誘電体膜を形成する工程と、
前記第2強誘電体膜の上に第2導電膜を形成する工程と、
前記導電性拡散防止膜、前記第1導電膜、第1強誘電体膜、前記第2強誘電体膜、及び前記第2導電膜をパターニングすることにより、下部電極、キャパシタ誘電体膜、及び上部電極を備えたキャパシタを形成すると共に、前記導電性拡散防止膜を前記下部電極の下に島状に残す工程と、
前記下部電極で覆われていない領域の前記導電性酸素バリア膜を除去する工程とを有し、
前記導電性拡散防止膜として、前記キャパシタ誘電体膜の構成元素の拡散を防止する導電性材料よりなる膜を形成することを特徴とする半導体装置の製造方法。 - 前記第2強誘電体膜を形成する工程は、酸素含有雰囲気中で前記半導体基板を昇温した後、原料ガスの雰囲気中において前記第2強誘電体膜を形成することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記半導体基板を昇温した後であって、前記第2強誘電体膜を形成する前に、溶媒ガスの雰囲気中に前記第1強誘電体膜を曝すことを特徴とする請求項2に記載の半導体装置の製造方法。
- 前記導電性拡散防止膜を構成する前記導電性材料は、イリジウム又はルテニウムを含む合金、又は、窒化チタン、窒化ジルコニウム、窒化ハフニウム、窒化タンタル、窒化クロム、窒化ニオブのいずれかであることを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置の製造方法。
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JP2006308159A JP5205741B2 (ja) | 2006-11-14 | 2006-11-14 | 半導体装置の製造方法 |
US11/938,958 US7763921B2 (en) | 2006-11-14 | 2007-11-13 | Semiconductor device and manufacturing method thereof |
US12/818,279 US8110411B2 (en) | 2006-11-14 | 2010-06-18 | Semiconductor device and manufacturing method thereof |
US13/343,195 US8367428B2 (en) | 2006-11-14 | 2012-01-04 | Semiconductor device and manufacturing method thereof |
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KR100964834B1 (ko) * | 2005-09-01 | 2010-06-24 | 후지쯔 세미컨덕터 가부시키가이샤 | 강유전체 메모리 장치 및 그 제조 방법, 반도체장치의 제조방법 |
JP4320679B2 (ja) * | 2007-02-19 | 2009-08-26 | セイコーエプソン株式会社 | 強誘電体メモリ装置の製造方法 |
US8153348B2 (en) * | 2008-02-20 | 2012-04-10 | Applied Materials, Inc. | Process sequence for formation of patterned hard mask film (RFP) without need for photoresist or dry etch |
JP2009200154A (ja) * | 2008-02-20 | 2009-09-03 | Toshiba Corp | 半導体装置とその製造方法 |
JP5502302B2 (ja) | 2008-09-26 | 2014-05-28 | ローム株式会社 | 半導体装置およびその製造方法 |
JP5903578B2 (ja) | 2010-01-21 | 2016-04-13 | 株式会社ユーテック | Pbnzt強誘電体膜及び強誘電体膜の製造方法 |
KR101755643B1 (ko) | 2010-12-15 | 2017-07-10 | 삼성전자주식회사 | 3차원 반도체 장치 및 그 제조 방법 |
JP5834909B2 (ja) * | 2011-12-28 | 2015-12-24 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
JP2015133392A (ja) * | 2014-01-10 | 2015-07-23 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
JP6402528B2 (ja) * | 2014-08-07 | 2018-10-10 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
US10224238B2 (en) * | 2016-04-12 | 2019-03-05 | Apple Inc. | Electrical components having metal traces with protected sidewalls |
CN112928116B (zh) | 2019-12-06 | 2024-03-22 | 财团法人工业技术研究院 | 铁电记忆体 |
US11792996B2 (en) | 2021-04-13 | 2023-10-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bottom-electrode interface structure for memory |
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JP4299959B2 (ja) | 2000-08-14 | 2009-07-22 | 株式会社東芝 | 半導体装置の製造方法 |
JP2002368200A (ja) * | 2001-06-08 | 2002-12-20 | Sony Corp | 半導体記憶装置 |
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JP2003051582A (ja) | 2001-08-07 | 2003-02-21 | Hitachi Ltd | 半導体装置およびその製造方法 |
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JP3961399B2 (ja) | 2002-10-30 | 2007-08-22 | 富士通株式会社 | 半導体装置の製造方法 |
JP4421814B2 (ja) | 2002-10-30 | 2010-02-24 | 富士通マイクロエレクトロニクス株式会社 | 容量素子の製造方法 |
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JP4547238B2 (ja) | 2004-11-16 | 2010-09-22 | パナソニック株式会社 | 半導体記憶装置 |
JP2006253194A (ja) | 2005-03-08 | 2006-09-21 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2006278550A (ja) * | 2005-03-28 | 2006-10-12 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2006302975A (ja) * | 2005-04-15 | 2006-11-02 | Toshiba Corp | 半導体装置及びその製造方法 |
JP4761946B2 (ja) * | 2005-11-22 | 2011-08-31 | 株式会社東芝 | 不揮発性半導体記憶素子及びその製造方法並びに不揮発性半導体記憶素子を含む半導体集積回路装置 |
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2007
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2010
- 2010-06-18 US US12/818,279 patent/US8110411B2/en not_active Expired - Fee Related
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2012
- 2012-01-04 US US13/343,195 patent/US8367428B2/en not_active Expired - Fee Related
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US8367428B2 (en) | 2013-02-05 |
US20100255611A1 (en) | 2010-10-07 |
JP2008124329A (ja) | 2008-05-29 |
US8110411B2 (en) | 2012-02-07 |
US20120107963A1 (en) | 2012-05-03 |
US20080111241A1 (en) | 2008-05-15 |
US7763921B2 (en) | 2010-07-27 |
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