JP5190414B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5190414B2 JP5190414B2 JP2009127377A JP2009127377A JP5190414B2 JP 5190414 B2 JP5190414 B2 JP 5190414B2 JP 2009127377 A JP2009127377 A JP 2009127377A JP 2009127377 A JP2009127377 A JP 2009127377A JP 5190414 B2 JP5190414 B2 JP 5190414B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- semiconductor device
- blocks
- power supply
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009127377A JP5190414B2 (ja) | 2009-05-27 | 2009-05-27 | 半導体装置 |
| PCT/JP2009/007142 WO2010137098A1 (ja) | 2009-05-27 | 2009-12-22 | 半導体装置 |
| US13/289,683 US8710667B2 (en) | 2009-05-27 | 2011-11-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009127377A JP5190414B2 (ja) | 2009-05-27 | 2009-05-27 | 半導体装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2010278104A JP2010278104A (ja) | 2010-12-09 |
| JP2010278104A5 JP2010278104A5 (enExample) | 2011-07-21 |
| JP5190414B2 true JP5190414B2 (ja) | 2013-04-24 |
Family
ID=43222242
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009127377A Expired - Fee Related JP5190414B2 (ja) | 2009-05-27 | 2009-05-27 | 半導体装置 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US8710667B2 (enExample) |
| JP (1) | JP5190414B2 (enExample) |
| WO (1) | WO2010137098A1 (enExample) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102893397B (zh) * | 2011-05-17 | 2016-04-13 | 松下电器产业株式会社 | 三维集成电路、处理器、半导体芯片及三维集成电路的制造方法 |
| TWI475939B (zh) | 2013-10-15 | 2015-03-01 | Wistron Corp | 散熱式鏤空之形成方法及形成之散熱式鏤空結構 |
| JP2015207730A (ja) * | 2014-04-23 | 2015-11-19 | マイクロン テクノロジー, インク. | 半導体装置 |
| JP6295863B2 (ja) | 2014-07-16 | 2018-03-20 | 富士通株式会社 | 電子部品、電子装置及び電子装置の製造方法 |
| US9287208B1 (en) * | 2014-10-27 | 2016-03-15 | Intel Corporation | Architecture for on-die interconnect |
| CN113224047A (zh) * | 2020-01-21 | 2021-08-06 | 扬智科技股份有限公司 | 集成电路结构 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6308307B1 (en) * | 1998-01-29 | 2001-10-23 | Texas Instruments Incorporated | Method for power routing and distribution in an integrated circuit with multiple interconnect layers |
| JP3692254B2 (ja) | 1999-03-25 | 2005-09-07 | 京セラ株式会社 | 多層配線基板 |
| US6483714B1 (en) | 1999-02-24 | 2002-11-19 | Kyocera Corporation | Multilayered wiring board |
| JP4460227B2 (ja) | 2003-03-10 | 2010-05-12 | 富士通マイクロエレクトロニクス株式会社 | 半導体集積回路 |
| JP2005332903A (ja) | 2004-05-19 | 2005-12-02 | Matsushita Electric Ind Co Ltd | 半導体装置 |
| JP4539916B2 (ja) | 2005-01-19 | 2010-09-08 | ルネサスエレクトロニクス株式会社 | 半導体集積回路、半導体集積回路の設計方法、及び半導体集積回路の設計用プログラム |
| JP2008270319A (ja) * | 2007-04-17 | 2008-11-06 | Toshiba Corp | 半導体装置 |
| JP2009054702A (ja) | 2007-08-24 | 2009-03-12 | Panasonic Corp | 半導体集積回路 |
-
2009
- 2009-05-27 JP JP2009127377A patent/JP5190414B2/ja not_active Expired - Fee Related
- 2009-12-22 WO PCT/JP2009/007142 patent/WO2010137098A1/ja not_active Ceased
-
2011
- 2011-11-04 US US13/289,683 patent/US8710667B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| JP2010278104A (ja) | 2010-12-09 |
| US8710667B2 (en) | 2014-04-29 |
| US20120112354A1 (en) | 2012-05-10 |
| WO2010137098A1 (ja) | 2010-12-02 |
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