JP5164362B2 - 半導体内臓基板およびその製造方法 - Google Patents

半導体内臓基板およびその製造方法 Download PDF

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Publication number
JP5164362B2
JP5164362B2 JP2006291272A JP2006291272A JP5164362B2 JP 5164362 B2 JP5164362 B2 JP 5164362B2 JP 2006291272 A JP2006291272 A JP 2006291272A JP 2006291272 A JP2006291272 A JP 2006291272A JP 5164362 B2 JP5164362 B2 JP 5164362B2
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Prior art keywords
semiconductor element
semiconductor
layer
wiring pattern
connection wiring
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Expired - Fee Related
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JP2006291272A
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English (en)
Japanese (ja)
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JP2007150275A5 (https=
JP2007150275A (ja
Inventor
浩史 近藤
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Canon Inc
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Canon Inc
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Priority to JP2006291272A priority Critical patent/JP5164362B2/ja
Priority to US11/555,760 priority patent/US20070108610A1/en
Publication of JP2007150275A publication Critical patent/JP2007150275A/ja
Publication of JP2007150275A5 publication Critical patent/JP2007150275A5/ja
Priority to US13/748,657 priority patent/US8609539B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7438—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/099—Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
JP2006291272A 2005-11-02 2006-10-26 半導体内臓基板およびその製造方法 Expired - Fee Related JP5164362B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2006291272A JP5164362B2 (ja) 2005-11-02 2006-10-26 半導体内臓基板およびその製造方法
US11/555,760 US20070108610A1 (en) 2005-11-02 2006-11-02 Embedded semiconductor device substrate and production method thereof
US13/748,657 US8609539B2 (en) 2005-11-02 2013-01-24 Embedded semiconductor device substrate and production method thereof

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2005318962 2005-11-02
JP2005318962 2005-11-02
JP2006291272A JP5164362B2 (ja) 2005-11-02 2006-10-26 半導体内臓基板およびその製造方法

Publications (3)

Publication Number Publication Date
JP2007150275A JP2007150275A (ja) 2007-06-14
JP2007150275A5 JP2007150275A5 (https=) 2009-12-10
JP5164362B2 true JP5164362B2 (ja) 2013-03-21

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JP2006291272A Expired - Fee Related JP5164362B2 (ja) 2005-11-02 2006-10-26 半導体内臓基板およびその製造方法

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US (2) US20070108610A1 (https=)
JP (1) JP5164362B2 (https=)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100856209B1 (ko) * 2007-05-04 2008-09-03 삼성전자주식회사 집적회로가 내장된 인쇄회로기판 및 그 제조방법
FR2917234B1 (fr) * 2007-06-07 2009-11-06 Commissariat Energie Atomique Dispositif multi composants integres dans une matrice semi-conductrice.
KR101113889B1 (ko) 2007-12-04 2012-02-29 삼성테크윈 주식회사 전자 소자를 내장하는 회로기판 및 회로기판의 제조 방법
US8017451B2 (en) 2008-04-04 2011-09-13 The Charles Stark Draper Laboratory, Inc. Electronic modules and methods for forming the same
US8273603B2 (en) * 2008-04-04 2012-09-25 The Charles Stark Draper Laboratory, Inc. Interposers, electronic modules, and methods for forming the same
AT10247U8 (de) * 2008-05-30 2008-12-15 Austria Tech & System Tech Verfahren zur integration wenigstens eines elektronischen bauteils in eine leiterplatte sowie leiterplatte
FR2934082B1 (fr) * 2008-07-21 2011-05-27 Commissariat Energie Atomique Dispositif multi composants integres dans une matrice
KR101055471B1 (ko) * 2008-09-29 2011-08-08 삼성전기주식회사 전자소자 내장형 인쇄회로기판 및 그 제조방법
JP5467589B2 (ja) * 2009-01-05 2014-04-09 セイコーインスツル株式会社 電子回路部品および電子機器
FR2947948B1 (fr) * 2009-07-09 2012-03-09 Commissariat Energie Atomique Plaquette poignee presentant des fenetres de visualisation
JP5582597B2 (ja) * 2009-09-30 2014-09-03 セイコーインスツル株式会社 電子回路部品および電子機器
US8435837B2 (en) * 2009-12-15 2013-05-07 Silicon Storage Technology, Inc. Panel based lead frame packaging method and device
DE102009058764A1 (de) * 2009-12-15 2011-06-16 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur Herstellung einer elektronischen Baugruppe und elektronische Baugruppe
US8836094B1 (en) * 2013-03-14 2014-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package device including an opening in a flexible substrate and methods of forming the same
US9663357B2 (en) * 2015-07-15 2017-05-30 Texas Instruments Incorporated Open cavity package using chip-embedding technology
JP6693441B2 (ja) * 2017-02-27 2020-05-13 オムロン株式会社 電子装置およびその製造方法
DE102019103281B4 (de) * 2019-02-11 2023-03-16 Infineon Technologies Ag Verfahren zum bilden eines die-gehäuses

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49131863U (https=) * 1973-03-10 1974-11-13
JPS60252992A (ja) * 1984-05-30 1985-12-13 Toshiba Corp Ｉｃカ−ド
JPH074995B2 (ja) * 1986-05-20 1995-01-25 株式会社東芝 Ｉｃカ−ド及びその製造方法
JP2772157B2 (ja) * 1991-05-28 1998-07-02 三菱重工業株式会社 半導体装置の配線方法
US5548091A (en) * 1993-10-26 1996-08-20 Tessera, Inc. Semiconductor chip connection components with adhesives and methods for bonding to the chip
JPH07153867A (ja) * 1993-11-30 1995-06-16 Hitachi Ltd 半導体装置およびその製造方法
US5886877A (en) * 1995-10-13 1999-03-23 Meiko Electronics Co., Ltd. Circuit board, manufacturing method therefor, and bump-type contact head and semiconductor component packaging module using the circuit board
JP2842378B2 (ja) 1996-05-31 1999-01-06 日本電気株式会社 電子回路基板の高密度実装構造
CN100336426C (zh) * 2000-02-25 2007-09-05 揖斐电株式会社 多层印刷电路板以及多层印刷电路板的制造方法
JP2001291797A (ja) * 2000-04-10 2001-10-19 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
CN1278413C (zh) * 2000-09-25 2006-10-04 揖斐电株式会社 半导体元件及其制造方法、多层印刷布线板及其制造方法
JP3634735B2 (ja) * 2000-10-05 2005-03-30 三洋電機株式会社 半導体装置および半導体モジュール
DE10213296B9 (de) * 2002-03-25 2007-04-19 Infineon Technologies Ag Elektronisches Bauteil mit einem Halbleiterchip, Verfahren zu seiner Herstellung und Verfahren zur Herstellung eines Nutzens
JP2004152982A (ja) * 2002-10-30 2004-05-27 Matsushita Electric Ind Co Ltd 電子部品実装済部品の製造方法、及び該電子部品実装済部品を備えた電子部品実装済完成品の製造方法、並びに電子部品実装済完成品
JP3920195B2 (ja) 2002-11-11 2007-05-30 新光電気工業株式会社 電子部品実装構造及びその製造方法
JP4209178B2 (ja) * 2002-11-26 2009-01-14 新光電気工業株式会社 電子部品実装構造及びその製造方法
JP4489411B2 (ja) 2003-01-23 2010-06-23 新光電気工業株式会社 電子部品実装構造の製造方法
JP4137659B2 (ja) 2003-02-13 2008-08-20 新光電気工業株式会社 電子部品実装構造及びその製造方法
JP4200285B2 (ja) * 2003-04-02 2008-12-24 パナソニック株式会社 回路基板の製造方法
JP2004335641A (ja) 2003-05-06 2004-11-25 Canon Inc 半導体素子内蔵基板の製造方法
JP4298559B2 (ja) * 2004-03-29 2009-07-22 新光電気工業株式会社 電子部品実装構造及びその製造方法
JP4361826B2 (ja) * 2004-04-20 2009-11-11 新光電気工業株式会社 半導体装置
TW200539246A (en) * 2004-05-26 2005-12-01 Matsushita Electric Industrial Co Ltd Semiconductor device and method for manufacturing the same
JP4398305B2 (ja) * 2004-06-02 2010-01-13 カシオ計算機株式会社 半導体装置およびその製造方法
JP2006019441A (ja) * 2004-06-30 2006-01-19 Shinko Electric Ind Co Ltd 電子部品内蔵基板の製造方法
JP4575071B2 (ja) * 2004-08-02 2010-11-04 新光電気工業株式会社 電子部品内蔵基板の製造方法
JP2006059992A (ja) * 2004-08-19 2006-03-02 Shinko Electric Ind Co Ltd 電子部品内蔵基板の製造方法
JP2006165252A (ja) * 2004-12-07 2006-06-22 Shinko Electric Ind Co Ltd チップ内蔵基板の製造方法
TWI260056B (en) * 2005-02-01 2006-08-11 Phoenix Prec Technology Corp Module structure having an embedded chip
JP2006332094A (ja) * 2005-05-23 2006-12-07 Seiko Epson Corp 電子基板の製造方法及び半導体装置の製造方法並びに電子機器の製造方法

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Publication number Publication date
US8609539B2 (en) 2013-12-17
JP2007150275A (ja) 2007-06-14
US20070108610A1 (en) 2007-05-17
US20130130494A1 (en) 2013-05-23

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