US20070108610A1 - Embedded semiconductor device substrate and production method thereof - Google Patents

Embedded semiconductor device substrate and production method thereof Download PDF

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Publication number
US20070108610A1
US20070108610A1 US11/555,760 US55576006A US2007108610A1 US 20070108610 A1 US20070108610 A1 US 20070108610A1 US 55576006 A US55576006 A US 55576006A US 2007108610 A1 US2007108610 A1 US 2007108610A1
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semiconductor device
wiring pattern
layer
connection wiring
substrate
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Hiroshi Kondo
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Canon Inc
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Assigned to CANON KABUSHIKI KAISHA reassignment CANON KABUSHIKI KAISHA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KONDO, HIROSHI
Publication of US20070108610A1 publication Critical patent/US20070108610A1/en
Priority to US13/748,657 priority Critical patent/US8609539B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7438—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/099—Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • the present invention relates to an embedded semiconductor device substrate having a semiconductor device buried in an insulating resin layer of a printed wiring board, and a method of producing the same.
  • an embedded semiconductor device substrate having a semiconductor device buried inside of a printed wiring board has been proposed such as disclosed in Japanese Patent Application Laid-Open No. H09-321408.
  • a semiconductor device having stud bumps formed thereon is mounted in a recessed portion formed beforehand on a printed wiring board, and an insulating layer is then formed so as to cover the semiconductor device.
  • a semiconductor device 101 is mounted through an insulating epoxy resin 104 on a Cu foil 103 .
  • a prepreg material 105 is disposed at such a location that an opening 105 a of the prepreg materiel 105 contains the semiconductor device 101 .
  • the prepreg material 105 has approximately the same thickness as the thickness of the semiconductor device 101 , and the opening 105 a having a shape corresponding to the shape of the semiconductor device 101 is formed with a punching press.
  • RCC Resin Coated Cupper
  • the Cu foil 103 , prepreg material 105 , and RCC material 107 are disposed by stacking in this way, and are subjected to thermocompression bonding in a vacuum atmosphere as shown in FIG. 10C .
  • a part of the Cu foil 103 a corresponding to an electrode portion 102 on the semiconductor device 101 is removed by ordinary etching to form a hole portion.
  • a part of the epoxy resin 106 which is exposed via the hole portion is removed by a laser such as a CO 2 , YAG, or excimer laser to form an opening 108 , whereby the electrode portion 102 of the semiconductor device 101 is exposed therethrough.
  • a laser such as a CO 2 , YAG, or excimer laser to form an opening 108 , whereby the electrode portion 102 of the semiconductor device 101 is exposed therethrough.
  • FIG. 12E while a Cu layer 103 b is formed on the entire surface by plating, the opening 108 is filled with the Cu layer 103 b.
  • a resist material is coated on the Cu layer 103 b, and a wiring pattern is formed in an exposure step through a mask and a development step, so that the embedded semiconductor device substrate having the semiconductor device 101 integrated therein as shown in FIG. 10F is obtained.
  • the present invention has been accomplished in view of such problems, and it is an object of the present invention to provide an embedded semiconductor device substrate, which can increase the stability of electric connection to a wiring pattern, corresponding to the tendency of reduction in pitch of an electrode portion of a semiconductor device, and a method of producing the same.
  • an embedded semiconductor device substrate having a semiconductor device integrated in an insulating resin layer, wherein a wiring pattern is formed on the insulating resin layer, a bump for connection is formed on an electrode portion on the semiconductor device, and the wiring pattern and the bump are connected through a connection wiring pattern provided on the wiring pattern and the bump.
  • connection wiring pattern is thinner than the wiring pattern.
  • the wiring has a multi-layer structure which is comprised of a plurality of materials.
  • a method of producing an embedded semiconductor device substrate having a semiconductor device integrated therein comprising the steps of: forming a bump on an electrode portion on a surface of a semiconductor device; disposing the semiconductor device in an opening formed on a substrate; forming a conductive film on the semiconductor device and the substrate; integrating the semiconductor device and the substrate into a single body; patterning the conductive film to form wiring patterns and removing the conductive film on the semiconductor device to expose the bump; and forming a connection wiring pattern for connecting the electrode portion on the semiconductor device and the wiring pattern.
  • connection wiring pattern is formed by forming a connection wiring layer on the insulating resin layer and the semiconductor device, patterning a resist material formed on the connection wiring layer by performing direct exposure with a laser, and then performing etching.
  • connection wiring pattern is formed by forming a connection wiring layer on the insulating resin layer and the semiconductor device, performing direct writing of a resist material on the connection wiring layer, and then performing etching.
  • connection wiring pattern is formed by performing direct writing of a conductive material on the insulating resin layer and the semiconductor device.
  • FIG. 1 is a cross-sectional view of an embedded semiconductor device substrate according to Example 1 of the present invention.
  • FIGS. 2A, 2B , and 2 C are cross-sectional views illustrating the steps of Production Method 1 of a semiconductor substrate according to Example 1 of the present invention.
  • FIGS. 3A and 3B are cross-sectional views illustrating the steps of Production Method 1 of the semiconductor substrate according to Example 1 of the present invention.
  • FIGS. 4A, 4B , and 4 C are cross-sectional views illustrating the steps of Production Method 1 of the semiconductor substrate according to Example 1 of the present invention.
  • FIGS. 5A and 5B are plan views illustrating the arrangement of bumps of a semiconductor device and a connection wiring pattern according to Example 1 of the present invention.
  • FIGS. 6A and 6B are plan views illustrating the arrangement of bumps of a semiconductor device and a connection wiring pattern according to Example 1 of the present invention.
  • FIGS. 7A, 7B , and 7 C are cross-sectional views illustrating the steps of Production Method 2 of the semiconductor substrate according to Example 1 of the present invention.
  • FIG. 8 is a cross-sectional view of an embedded semiconductor device substrate according to Example 2 of the present invention.
  • FIGS. 9A and 9B are cross-sectional views illustrating the steps of a production method of a semiconductor substrate according to Example 2 of the present invention.
  • FIGS. 10A, 10B , 10 C, 10 D, 10 E, and 10 F are cross-sectional views illustrating the steps of a production method of a semiconductor substrate according to a conventional example.
  • FIG. 1 is a cross-sectional view of an embedded semiconductor device substrate 20 according to Example 1 of the present invention.
  • reference numeral 1 denotes a semiconductor device
  • reference numeral 2 denotes a bump formed on an electrode portion 11 on the semiconductor device 1 . Portions other than the electrode portion 11 on the semiconductor device 1 are covered with an insulating layer 13 .
  • Reference numeral 12 denotes a resin film provided on the insulating layer 13 and having a thickness which is approximately the same as the height of the bump 2 .
  • An insulating layer 4 is provided under the semiconductor device 1 .
  • Reference numeral 5 denotes an insulating resin layer which forms a body of a printed wiring board.
  • Reference symbol 3 a denotes a rear surface wiring pattern formed on a rear surface of the insulating resin layer 5
  • reference symbol 7 a denotes a front surface wiring pattern formed on a front surface of the insulating resin layer 5
  • Reference numeral 6 denotes an adhesive resin layer which seals the semiconductor device 1
  • Reference symbol 10 a denotes a connection wiring pattern which connects the front surface wiring pattern 7 a on the insulating resin layer 5 and the bump 2 on the semiconductor device 1 .
  • the connection wiring pattern 10 a connects the bump 2 and the front surface wiring pattern 7 a through a conductive protective layer 9 a.
  • bumps 2 are formed on the electrode portion 11 on an upper surface of the semiconductor device 1 .
  • a metal such as Au or Cu or a solder is used.
  • a sphere or cylinder with a diameter of 20 to 30 ⁇ m is used.
  • the upper surface of the semiconductor device 1 is covered with the insulating layer 13 , and only the electrode portion 11 is exposed to the upper surface.
  • An epoxy resin or the like can be used as the insulating layer 13 .
  • the resin film 12 having a thickness which is approximately the same as the height of the bump 2 is formed in an active area of the upper surface of the insulating layer 13 formed on the upper surface of the semiconductor device 1 .
  • a polyimide film or the like can be used as the resin film 12 .
  • the semiconductor device 1 having the bumps 2 and the resin film 12 formed on the surface thereof, and the rear surface wiring layer 3 are bonded through the insulating layer 4 .
  • the insulating layer 4 there is used an epoxy resin film of 10 to 50 ⁇ m in thickness or the like.
  • the rear surface wiring layer 3 it is possible to use a thin film such as of copper or aluminum of 10 to 35 ⁇ m in thickness.
  • the semiconductor device 1 is bonded to the rear surface wiring layer 3 through the insulating layer 4 by heat curing.
  • the insulating resin layer 5 which has approximately the same thickness as the thickness (50 to 150 ⁇ m) of the semiconductor device 1 , and has the opening 5 a with a shape corresponding to the shape of the semiconductor device 1 is disposed at such a location that the opening 5 a contains the semiconductor device 1 .
  • a prepreg material containing glass cloth can be used as the insulating resin layer 5 .
  • the semiconductor device 1 is disposed in the opening 5 a of the insulating resin layer 5 .
  • an RCC material 8 having the adhesive resin layer 6 such as of an epoxy lined on the front surface wiring layer 7 is disposed on the insulating resin layer 5 and semiconductor device 1 .
  • the front surface wiring layer 7 similarly to the rear surface wiring layer 3 , it is possible to use a thin film such as of copper or aluminum of 10 to 35 ⁇ m in thickness.
  • the adhesive resin layer 6 an epoxy resin film with a thickness of 20 to 60 ⁇ m or the like can be used.
  • the rear surface wiring layer 3 , the insulating resin layer 5 , and the RCC material 8 are simultaneously subjected to heat pressing at a temperature of 150 to 200° C. in a vacuum atmosphere. Thereby, the rear surface wiring layer 3 , the insulating resin layer 5 , and the RCC material 8 are integrated into a single substrate. Since the flowability of the adhesive resin layer 6 becomes high by the heating, the adhesive resin is flown to enter a gap between the semiconductor device 1 in the opening 5 a and the insulating resin layer 5 to fix the semiconductor device 1 securely. In addition, since the adhesive resin layer 6 on the bumps 2 is flown away by the bumps, the bumps 2 and the front surface wiring layer 7 come into contact with each other.
  • the reason why the prepreg material 5 containing glass cloth is used is to prevent the flatness of the surface after the heat pressing from being impaired due to a difference in pressure between a portion where the semiconductor device 1 exists and a portion where no semiconductor device exists generated by the pressure applied during the heat pressing. Also from this viewpoint, it is preferable that the thickness of the glass cloth is equal to or somewhat larger than the sum of the thickness of the semiconductor device 1 and the height of the bump 2 .
  • the above-mentioned resin film 12 prevents the front surface wiring layer 7 on the semiconductor device 1 from becoming uneven (non-flat) due to the bumps 2 provided on the semiconductor device 1 . Furthermore, when the bumps 2 deform to reduce their heights to the thickness of the resin film 12 , the resin film 12 also receives the applied pressure, so that it is possible to prevent the semiconductor device 1 from being damaged by concentration of the pressing pressure on the bumps 2 .
  • the front surface wiring layer 7 and the rear surface wiring layer 3 of the integrated substrate are patterned to form the front surface wiring pattern 7 a and the rear surface wiring pattern 3 a. Thereby, the top portions of the bumps 2 are exposed.
  • a protective layer 9 of 1 to 3 ⁇ m thick is formed on the front and the rear surfaces of the substrate by electroless plating.
  • a metal such as Ni can be used as the protective layer 9 .
  • the protective layer 9 plays roles of protecting the thus formed wiring pattern 7 a and of preventing diffusion between the bumps 2 of the semiconductor device 1 and the connection wiring pattern 10 a described later.
  • connection wiring layer 10 of 1 to 3 ⁇ m thick is formed on the protective layer 9 by plating.
  • a metal such as Cu can be used for the connection wiring layer 10 .
  • a resist R 1 is formed in alignment with those positions, as shown in FIG. 4B .
  • a negative resist layer is provided on the surface on the side of which the bumps 2 of the semiconductor device 1 are exposed, and the positions of the respective bumps 2 are detected with respect to the individual semiconductor devices.
  • direct exposure with a light beam is performed to an area ranging from the region where the bump 2 is exposed to the electrode portion of the wiring pattern 7 a to be connected.
  • the light beam any light may be used as long as it has a wavelength band in which the resist material is photosensitive, with UV light being generally used.
  • the resist pattern R 1 can be formed, not only by forming once a resist film on the entire surface and then performing direct writing with a laser as described above, but also by performing direct writing of a resist itself. By performing direct writing of the resist itself, it becomes possible to reduce the production steps.
  • the resist pattern R 1 is formed only on portions from the bumps 2 of the semiconductor device 1 to the electrode portion of the wiring pattern 7 a.
  • the connection wiring pattern layer 10 is etched with a persulfuric acid solution, a portion of the connection wiring pattern layer (Cu layer) 10 on the protective layer (Ni layer) 9 other than the portion covered with the resist pattern R 1 is removed. Thereby, the connection wiring pattern layer 10 is patterned to provide the connection wiring pattern 10 a.
  • the etching conditions are adjusted so that the etchant does not etch the protective layer (Ni layer) 9 .
  • the protective layer (Ni layer) 9 is etched.
  • a ferric chloride based solution is used as an etchant.
  • the ferric chloride based solution also etches the connection wiring pattern 10 a, since the connection wiring pattern 10 a is far thicker than the protective layer 9 , the connection wiring pattern will not be disconnected.
  • the connection wiring pattern 10 a is far thicker than the protective layer 9 , the connection wiring pattern will not be disconnected.
  • the embedded semiconductor device substrate 20 can be obtained.
  • FIGS. 5A, 5B , 6 A and 6 B are plan views of the embedded semiconductor device substrate 20 showing the connection wiring pattern 10 a which connects the bumps 2 and the wiring pattern 7 a.
  • FIGS. 5A and 6A are views showing the state before forming the connection wiring pattern 10 a
  • FIGS. 5B and 6B are views showing the state after forming the connection wiring pattern 10 a.
  • the semiconductor device 1 is disposed obliquely.
  • FIGS. 7A to 7 C a second method of producing the embedded semiconductor device substrate 20 shown in FIG. 1 will be explained with reference to FIGS. 7A to 7 C.
  • a positive resist R 2 is used instead of the negative resist R 1 used in the first production method.
  • the steps of the first production method described with reference to FIGS. 2A to 3 B are similarly carried out as such, and then the steps shown in FIGS. 7A to 7 C are carried out instead of the steps shown in FIGS. 4A to 4 C.
  • a positive resist R 2 is formed so that only portions of the protective layer (Ni layer) 9 in which the connection wiring pattern 10 a is to be formed is exposed. Then, electroplating is performed by using the protective layer 9 as a common electrode layer to form the connection wiring pattern (Cu layer) 10 a.
  • the thickness of the connection wiring pattern (Cu layer) 10 a is preferably 5 to 15 ⁇ m.
  • the resist pattern R 2 is stripped, and as shown in FIG.7C , the protective layer 9 is etched. At that time, although the connection wiring pattern 10 a is also etched, since the film thickness thereof is larger than that of the protective layer 9 , the film thickness becomes about 3 to 10 ⁇ m when etching is completed.
  • the resist pattern R 2 can be formed also by performing direct writing of a resist itself as is the case with the above-mentioned resist pattern R 1 . By performing direct writing of the resist itself, it becomes possible to reduce the production steps.
  • FIG. 8 is a cross-sectional view of an embedded semiconductor device substrate 30 according to Example 2 of the present invention.
  • this example has such a structure that there is no protective layer 9 .
  • the material of the bumps 2 of the semiconductor device 1 is Ni.
  • the protective layer 9 which functions as a diffusion barrier layer between the bumps 2 and the wiring pattern 7 a.
  • the elements which are the same as those shown in FIG. 1 are identified by like reference numerals or symbols.
  • FIGS. 9A and 9B the steps of the first production method described with reference to FIGS. 2A to 3 B are similarly carried out as such, and then the steps shown in FIGS. 9A and 9B are carried out instead of the steps shown in FIGS. 4A to 4 C.
  • connection wiring pattern layer (Cu layer) 10 is formed on the entire surface in a thickness of 3 to 10 ⁇ m by electroless plating. Then, the connection wiring pattern layer 10 is etched using a negative resist pattern R 3 to form the connection wiring pattern 10 a which is a very thin pattern as shown in FIG. 9B .
  • the bumps 2 are made of Ni and the connection wiring pattern 10 a is made of Cu
  • the bumps 2 may be made of Cu and the connection wiring pattern 10 a may be made of Ni.
  • the bumps 2 may be made of Ni and the connection wiring pattern 10 a may also be made of Ni, or the bumps 2 may be made of Cu and the connection wiring pattern 10 a may also be made of Cu.
  • the resist pattern R 3 can be formed also by performing direct writing of a resist itself as is the case with the above-mentioned resist pattern R 1 .
  • direct writing of the resist itself it becomes possible to reduce the production steps.
  • connection wiring pattern 10 a instead of the resist.
  • direct writing of the connection wiring pattern 10 a instead of the resist.
  • connection wiring pattern is formed in a separate step after burying the semiconductor device into the printed wiring board.

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
US11/555,760 2005-11-02 2006-11-02 Embedded semiconductor device substrate and production method thereof Abandoned US20070108610A1 (en)

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US20110140254A1 (en) * 2009-12-15 2011-06-16 Silicon Storage Technology, Inc. Panel Based Lead Frame Packaging Method And Device
US8975116B2 (en) * 2009-12-15 2015-03-10 Technische Universität Berlin Electronic assembly including an embedded electronic component
US10618206B2 (en) 2017-02-27 2020-04-14 Omron Corporation Resin-molded electronic device with disconnect prevention
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