CN101236943A - 内埋芯片的散热型无芯板薄型基板及其制造方法 - Google Patents

内埋芯片的散热型无芯板薄型基板及其制造方法 Download PDF

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CN101236943A
CN101236943A CNA2007100079600A CN200710007960A CN101236943A CN 101236943 A CN101236943 A CN 101236943A CN A2007100079600 A CNA2007100079600 A CN A2007100079600A CN 200710007960 A CN200710007960 A CN 200710007960A CN 101236943 A CN101236943 A CN 101236943A
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王建皓
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Advanced Semiconductor Engineering Inc
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Abstract

本发明公开了一种内埋芯片的散热型无芯板薄型基板，主要包含图案化承载金属层、至少一芯片、至少一介电层以及至少一线路层。该芯片贴设于该图案化承载金属层的散热片部。该介电层形成于该图案化承载金属层上并覆盖该芯片。该线路层形成于该介电层上，并电学连接该图案化承载金属层与该芯片。在该内埋芯片的散热型无芯板薄型基板工艺中，该图案化承载金属层的该散热片部在该线路层形成之后被图案化形成。由此形成一种能整合散热片、承载基板与内埋芯片成为一体化的薄板电子装置。

Description

内埋芯片的散热型无芯板薄型基板及其制造方法
技术领域
本发明涉及一种内埋芯片的电路板，特别涉及一种内埋芯片的散热型无芯板薄型基板及其制造方法。
背景技术
现有的电路板制作、芯片封装以及芯片封装件的模块结合为分开制造实施，通常所制得的电子装置，例如多芯片封装模块，会具有较厚结构及较长的电学传导路径。如图1所示，一种现有多芯片封装模块100主要包含电路基板110、多个芯片120以及散热片130，其中该芯片120可为具有多个凸块121的倒装焊芯片或是芯片封装件。该基板110具有多个设在上表面111的内连接垫113以及多个设在一下表面112的外连接垫114。该芯片120设置于该基板110的该上表面111，并以该凸块121电学连接至该内连接垫113。在该芯片120的上方贴设有该散热片130。通常多个焊球140接合至该外连接垫114。由于该基板110以印刷电路板的层压与增层技术制作，该芯片120的封装与模块结合则为个别实施，因此该多芯片封装模块100的厚度较厚且电学传导路径较长，易有串扰效应(cross-talk effect)。
发明内容
本发明的主要目的在于提供一种内埋芯片的散热型无芯板薄型基板，基板内的图案化承载金属层包含至少一散热片部，该散热片部设置有至少一芯片，该基板内的介电层覆盖该芯片，该基板内的线路层形成于该介电层上，该线路层电学连接该芯片至该图案化承载金属层，本发明将现有多芯片封装模块的基板、芯片与散热片整合成为一体化的薄板电子装置，其具有组件薄化并能增进内埋芯片的散热性与密封度。藉以提升组装性、互连可靠度(interconnection reliability)与电学效能、增加后续封装密度以及降低串扰效应(cross-talk effect)。
本发明的另一目的在于提供一种内埋芯片的散热型无芯板薄型基板的制造方法，其中该基板的该图案化承载金属层的图案化步骤在该基板内部的该线路层形成之后进行，使得该图案化承载金属层具有芯片承载、芯片散热与芯片电学连接的功能。
依据本发明，一种内埋芯片的散热型无芯板薄型基板主要包含图案化承载金属层、至少一芯片、介电层以及线路层。该图案化承载金属层至少包含散热片部。该芯片设置于该散热片部，且该芯片具有多个电极。该介电层形成于该图案化承载金属层上并覆盖该芯片，该介电层并具有多个通孔，该通孔贯通至该图案化承载金属层，并且该介电层显露出该芯片的该电极。该线路层形成于该介电层上，该第一线路层包含多个第一迹线以及多个第二迹线，该第一迹线经由该通孔电学连接至该图案化承载金属层，该第二迹线电学连接至该电极。
附图说明
图1为现有多芯片封装模块的截面示意图。
图2为依据本发明一个具体实施例，一种内埋芯片的散热型无芯板薄型基板的截面示意图。
图3A至3M为依据本发明第一具体实施例，该内埋芯片的散热型无芯板薄型基板在工艺中的截面示意图。
附图标记说明
100多芯片封装模块        110电路基板
111上表面                112下表面
113内连接垫              114外连接垫
120芯片                  121凸块
130散热片                140焊球
200内埋芯片的散热型无芯板薄型基板
210图案化承载金属层      210’承载金属层
211散热片部              212连接垫
213电镀层                220第一芯片
221电极                  230第一介电层
231通孔                  240第一线路层
241第一迹线          242第二迹线
251第二介电层        252第三介电层
253第四介电层        261第二线路层
262第三线路层        270第二芯片
271电极              280图案化覆盖金属层
280’覆盖金属层      281散热片部
282连接垫            291第一焊罩层
292开口              293第二焊罩层
294开口              310热压合装置
321掩模              322掩模
具体实施方式
请参阅图2，一种内埋芯片的散热型无芯板薄型基板200主要包含图案化承载金属层210、至少一第一芯片220、第一介电层230以及第一线路层240。其中，该图案化承载金属层210至少包含散热片部211。该图案化承载金属层210可由铜箔或其它导电膜加以图案化形成。在本实施例中，该图案化承载金属层210还包含多个连接垫212，以供对外电学导接。优选地，该图案化承载金属层210为线路层，包含线路结构，以减少基板内线路层数。
该第一芯片220以黏着或共晶接合的方式设置于该散热片部211，且该第一芯片220具有多个电极221，该电极221可如焊垫或是凸块。该第一芯片220包含集成电路组件(图未示出)。
该第一介电层230形成于该图案化承载金属层210上并覆盖该第一芯片220，该第一介电层230的材质可为如PI或PET等电绝缘性物质。该第一介电层230并具有多个通孔231，该通孔231贯通至该图案化承载金属层210。并且该第一介电层230显露出该电极221。该第一线路层240形成于该第一介电层230上，该第一线路层240包含多个第一迹线241以及多个第二迹线242，该第一迹线241经由该通孔231电学连接至该图案化承载金属层210的该连接垫212，该第二迹线242电学连接至该电极221。其中，该第一迹线241可直接或利用其它线路层以电学连接至相应的该第二迹线242。
在该内埋芯片的散热型无芯板薄型基板200的工艺中，该图案化承载金属层210的该散热片部211用以承载该第一芯片220，以该第一介电层230形成于该图案化承载金属层210上，并覆盖该第一芯片220，使得该第一芯片220被嵌埋于该图案化承载金属层210与该第一介电层230中，以达到增进散热性与薄化的功效。因此该图案化承载金属层210能省略现有的芯片承载件、散热片及承载基板内至少一线路层，而成为具备上述全部功能的单一组件，且该内埋芯片的散热型无芯板薄型基板200的内部可嵌埋有至少一芯片。
在本实施例中，该内埋芯片的散热型无芯板薄型基板200还包含第一焊罩层291，其形成该图案化承载金属层210的下方，该第一焊罩层291显露出该图案化承载金属层210的该连接垫212，并且，该第一焊罩层291具有显露该散热片部211的开口292，以使该散热片部211具有显露表面，其使得该内埋芯片的散热型无芯板薄型基板200具有良好散热性。优选地，该连接垫212的显露表面形成电镀层213，例如电镀镍金，以防止该连接垫212氧化，该电镀层213也可形成在该散热片部211的显露表面。此外，在本实施例中，在该第一线路层240上可另形成第二介电层251，在该第二介电层251上形成第二线路层261，且该第二线路层261电学导通至该第一线路层240。由于该第二介电层251用以隔离该第一线路层240与该第二线路层261，因此该第二介电层251的厚度可小于该第一介电层230。必要时可以逐层增加线路层与介电层直到所需的线路结构为止。在本实施例中，该内埋芯片的散热型无芯板薄型基板200可取代现有的多芯片封装模块，在该第二线路层261上可再形成第三介电层252，第三线路层262则可形成于该第三介电层252上，利用该第二线路层261与该第三线路层262电学连接该第一线路层240的该第一迹线241与该第二迹线242。另可藉由第四介电层253覆盖该第三线路层262。其中，至少一第二芯片270可设置于该第二线路层261上，该第二芯片270的多个电极271电学接合至该第二线路层261。优选地，该基板200可还包含图案化覆盖金属层280，其形成于该第二芯片270上与该第四介电层253上。该图案化覆盖金属层280至少包含贴附于该第二芯片270的散热片部281。另，在该基板200的最上层可形成第二焊罩层293，以覆盖该图案化覆盖金属层280的线路区段。该第二焊罩层293可具有开口294，以显露该图案化覆盖金属层280的该散热片部281。此外，当该图案化覆盖金属层280具有多个连接垫282时，该第二焊罩层293也可显露该连接垫282。优选地，该散热片部281及该连接垫282的显露表面也可形成该电镀层213，以防止氧化。因此，该内埋芯片的散热型无芯板薄型基板200具有优选的组装性与内部互连可靠度，能增加线路密度以及具有小而薄的尺寸外观。此外，更具有优选的电学功能增益性，不但能增加该芯片220、270在基板200内部电学互连功能，且能降低串扰效应。
关于该散热型无芯板薄型基板200的制造方法可参照图3A至3M。首先，请参阅图3A，提供承载金属层210’，其可为铜箔，并以胶黏着或共晶接合方式将至少一该第一芯片220贴设于该承载金属层210’上，且该第一芯片220的该电极221朝上显露。之后，请参阅图3B，利用数字喷墨印刷(digital inkjet printing)或是钢版印刷方式使该第一介电层230形成该承载金属层210’上并覆盖该第一芯片220并显露该电极221，其中以数字喷墨印刷方式为优选，可使得该第一介电层230达到各式图案变化并能控制该第一介电层230在不同区域的厚度差，例如该第一介电层230在该第一芯片220上的厚度可较薄，而在该承载金属层210’上的厚度可较厚。该第一介电层230可在形成的当时或是之后以曝光显影方式制成该通孔231，该通孔231贯通至该承载金属层210’。之后，请参阅第3C图，利用蚀刻铜箔或是光刻胶内电镀等方式使该第一线路层240形成于该第一介电层230上，该第一线路层240的该第一迹线241经由该通孔231电学连接至该承载金属层210’，该第一线路层240的该第二迹线242电学连接至该电极221。之后，请参阅图3D，将该第二介电层251形成于该第一线路层240上。在本实施例中，该第二介电层251具有适当的通孔结构，以显露出该第一线路层240的该第一迹线241及该第二迹线242。之后，请参阅图3E，将该第二线路层261形成于该第二介电层251上，且该第二线路层261电学导通至该第一线路层240。之后，请参阅图3F，将该第三介电层252形成于该第二线路层261上，该第三介电层252具有适当的通孔结构，以显露出部分的该第二线路层261。接着，请参阅图3G，利用热压合装置310将该第二芯片270设置于该第三介电层252上，并且如图3H所示，该第二芯片270的该电极271电学连接至该第二线路层261。之后，如图3I所示，将该第三线路层262形成于该第三介电层252上。接着，如图3J所示，将该第四介电层253形成于该第三线路层262上，也可运用数字喷墨印刷技术使该第四介电层253的外表面大致齐于该第二芯片270且不覆盖该第二芯片270。之后，请参阅图3K，将覆盖金属层280’形成于该第二芯片270与该第四介电层253上。之后，请参阅图3L，利用曝光显影技术，将掩模321形成于该承载金属层210’，且可将掩模322形成于该覆盖金属层280’，以蚀刻该承载金属层210’与该覆盖金属层280’，例如干膜或是光刻胶层均可作为该掩模321、322。接着，如图3M所示，该承载金属层210’被图案化而形成包含该散热片部211与该连接垫212的该图案化承载金属层210。该覆盖金属层280’被图案化而形成包含该散热片部281与该连接垫282的该图案化覆盖金属层280。最后，如图2所示，形成该第一焊罩层291于该图案化承载金属层210上，以及形成该第二焊罩层292于该图案化覆盖金属层280上，以制成该内埋芯片的散热型无芯板薄型基板200。因此，在工艺中该承载金属层210’具有芯片承载、芯片散热与芯片电学连接的功能。
本发明的保护范围当视后附的权利要求所界定的为准，本领域技术人员在不脱离本发明的精神和范围内所作的任何变化与修改，均属于本发明的保护范围。

Claims (12)

1. 一种内埋芯片的散热型无芯板薄型基板，其特征在于包含：
图案化承载金属层，其至少包含散热片部；
至少一芯片，其贴设于该散热片部，该芯片具有多个电极；
第一介电层，其形成于该图案化承载金属层上并覆盖该芯片，该第一介电层具有多个通孔，该通孔贯通至该图案化承载金属层，并且该第一介电层显露该电极；以及
第一线路层，其形成于该第一介电层上，该第一线路层包含多个第一迹线以及多个第二迹线，该第一迹线经由该通孔电学连接至该图案化承载金属层，该第二迹线电学连接至该电极。
2. 如权利要求1所述的内埋芯片的散热型无芯板薄型基板，还包含第一焊罩层，其形成于该图案化承载金属层的下方，且具有显露该散热片部的开口，以使该散热片部具有显露表面。
3. 如权利要求2所述的内埋芯片的散热型无芯板薄型基板，其中该图案化承载金属层还包含多个连接垫，且在该连接垫与该散热片部的该显露表面形成电镀层。
4. 如权利要求1或3所述的内埋芯片的散热型无芯板薄型基板，还包含第二介电层、第二线路层以及第二芯片，该第二介电层形成于该第一线路层上，该第二线路层形成于该第二介电层上，而该第二芯片设置于该第二线路层上。
5. 如权利要求4所述的内埋芯片的散热型无芯板薄型基板，还包含图案化覆盖金属层，其至少包含散热片部以及第二焊罩层，该散热片形成于该第二芯片上，该第二焊罩层形成于该图案化覆盖金属层上。
6. 如权利要求1所述的内埋芯片的散热型无芯板薄型基板，其中该图案化承载金属层也为线路层。
7. 一种内埋芯片的散热型无芯板薄型基板的制造方法，包含：
提供承载金属层；
贴设至少一芯片于该承载金属层，该芯片具有多个电极；
形成第一介电层于该承载金属层上并覆盖该芯片，该第一介电层具有多个通孔，该通孔贯通至该承载金属层，并且该第一介电层显露该电极；
形成第一线路层于该第一介电层上，该第一线路层包含多个第一迹线以及多个第二迹线，该第一迹线经由该通孔电学连接至该承载金属层，该第二迹线电学连接至该电极；以及
图案化该承载金属层，使该承载金属层包含被该芯片贴设的散热片部。
8. 如权利要求7所述的内埋芯片的散热型无芯板薄型基板的制造方法，还包含：形成第一焊罩层于该图案化承载金属层的下方，且该第一焊罩层具有显露该散热片部的开口，以使该散热片部具有显露表面。
9. 如权利要求8所述的内埋芯片的散热型无芯板薄型基板的制造方法，其中该图案化承载金属层还包含多个连接垫，其电学连接至该第一迹线。
10. 如权利要求9所述的内埋芯片的散热型无芯板薄型基板的制造方法，还包含：形成电镀层于该连接垫与该散热片部的该显露表面。
11. 如权利要求7所述的内埋芯片的散热型无芯板薄型基板的制造方法，还包含：
形成第二介电层于该第一线路层上；
形成第二线路层于该第二介电层上；
设置第二芯片于该第二线路层上；
形成图案化覆盖金属层于该第二芯片上，该图案化覆盖金属层至少包含贴附于该第二芯片的散热片部；以及
形成第二焊罩层于该图案化覆盖金属层上。
12. 如权利要求7所述的内埋芯片的散热型无芯板薄型基板的制造方法，其中该第一介电层以数字喷墨印刷方式形成。
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