JP5120983B2 - スペーサリソグラフィ - Google Patents

スペーサリソグラフィ Download PDF

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Publication number
JP5120983B2
JP5120983B2 JP2010516054A JP2010516054A JP5120983B2 JP 5120983 B2 JP5120983 B2 JP 5120983B2 JP 2010516054 A JP2010516054 A JP 2010516054A JP 2010516054 A JP2010516054 A JP 2010516054A JP 5120983 B2 JP5120983 B2 JP 5120983B2
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JP
Japan
Prior art keywords
mask pattern
layer
acid
organic material
forming
Prior art date
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JP2010516054A
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English (en)
Japanese (ja)
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JP2010534346A (ja
JP2010534346A5 (enExample
Inventor
キム リョウ−ハン
デン ユンフェイ
アイ． ワロウ トーマス
ラフォンテイン ブルーノ
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2010534346A publication Critical patent/JP2010534346A/ja
Publication of JP2010534346A5 publication Critical patent/JP2010534346A5/ja
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/40—Treatment after imagewise removal, e.g. baking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP2010516054A 2007-07-10 2008-07-10 スペーサリソグラフィ Active JP5120983B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/775,727 US8642474B2 (en) 2007-07-10 2007-07-10 Spacer lithography
US11/775,727 2007-07-10
PCT/US2008/008470 WO2009009095A1 (en) 2007-07-10 2008-07-10 Spacer lithography

Publications (3)

Publication Number Publication Date
JP2010534346A JP2010534346A (ja) 2010-11-04
JP2010534346A5 JP2010534346A5 (enExample) 2011-08-25
JP5120983B2 true JP5120983B2 (ja) 2013-01-16

Family

ID=39765015

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010516054A Active JP5120983B2 (ja) 2007-07-10 2008-07-10 スペーサリソグラフィ

Country Status (7)

Country Link
US (1) US8642474B2 (enExample)
EP (1) EP2168008B1 (enExample)
JP (1) JP5120983B2 (enExample)
KR (1) KR101520440B1 (enExample)
CN (1) CN101730864B (enExample)
TW (1) TWI431665B (enExample)
WO (1) WO2009009095A1 (enExample)

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TWI476816B (zh) * 2009-06-26 2015-03-11 羅門哈斯電子材料有限公司 自我對準間隔之多重圖案化方法
EP2336824A1 (en) * 2009-11-19 2011-06-22 Rohm and Haas Electronic Materials, L.L.C. Methods of forming electronic devices
US8815747B2 (en) * 2010-06-03 2014-08-26 Micron Technology, Inc. Methods of forming patterns on substrates
US9233840B2 (en) * 2010-10-28 2016-01-12 International Business Machines Corporation Method for improving self-assembled polymer features
US9330914B2 (en) 2013-10-08 2016-05-03 Micron Technology, Inc. Methods of forming line patterns in substrates
JP6126570B2 (ja) * 2013-12-13 2017-05-10 富士フイルム株式会社 パターン形成方法、電子デバイスの製造方法
US9257439B2 (en) 2014-02-27 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET SRAM
CN110391133B (zh) * 2018-04-17 2021-07-20 联华电子股份有限公司 图案化方法
US11069692B2 (en) 2018-07-31 2021-07-20 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET SRAM cells with dielectric fins
US11437385B2 (en) 2018-09-24 2022-09-06 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET SRAM cells with reduced fin pitch

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Also Published As

Publication number Publication date
US8642474B2 (en) 2014-02-04
TW200915389A (en) 2009-04-01
JP2010534346A (ja) 2010-11-04
EP2168008B1 (en) 2014-11-26
TWI431665B (zh) 2014-03-21
CN101730864A (zh) 2010-06-09
KR101520440B1 (ko) 2015-05-15
EP2168008A1 (en) 2010-03-31
WO2009009095A1 (en) 2009-01-15
KR20100057799A (ko) 2010-06-01
US20090017628A1 (en) 2009-01-15
CN101730864B (zh) 2012-07-18

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