JP5110995B2 - 積層型半導体装置及びその製造方法 - Google Patents

積層型半導体装置及びその製造方法 Download PDF

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Publication number
JP5110995B2
JP5110995B2 JP2007190030A JP2007190030A JP5110995B2 JP 5110995 B2 JP5110995 B2 JP 5110995B2 JP 2007190030 A JP2007190030 A JP 2007190030A JP 2007190030 A JP2007190030 A JP 2007190030A JP 5110995 B2 JP5110995 B2 JP 5110995B2
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Japan
Prior art keywords
semiconductor element
electrode terminal
metal wire
semiconductor
stacked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007190030A
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English (en)
Japanese (ja)
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JP2009027039A (ja
JP2009027039A5 (https=
Inventor
茂 水野
孝 栗原
晶紀 白石
啓 村山
光敏 東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2007190030A priority Critical patent/JP5110995B2/ja
Priority to US12/174,192 priority patent/US20090020887A1/en
Priority to TW097127083A priority patent/TW200905766A/zh
Priority to KR1020080069978A priority patent/KR20090009737A/ko
Publication of JP2009027039A publication Critical patent/JP2009027039A/ja
Publication of JP2009027039A5 publication Critical patent/JP2009027039A5/ja
Application granted granted Critical
Publication of JP5110995B2 publication Critical patent/JP5110995B2/ja
Expired - Fee Related legal-status Critical Current
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07131—Means for applying material, e.g. for deposition or forming coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07502—Connecting or disconnecting of bond wires using an auxiliary member
    • H10W72/07504—Connecting or disconnecting of bond wires using an auxiliary member the auxiliary member being temporary, e.g. a sacrificial coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/834—Interconnections on sidewalls of chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/231—Configurations of stacked chips the stacked chips being on both top and bottom sides of an auxiliary carrier having no electrical connection structure

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  • Wire Bonding (AREA)
JP2007190030A 2007-07-20 2007-07-20 積層型半導体装置及びその製造方法 Expired - Fee Related JP5110995B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2007190030A JP5110995B2 (ja) 2007-07-20 2007-07-20 積層型半導体装置及びその製造方法
US12/174,192 US20090020887A1 (en) 2007-07-20 2008-07-16 Semiconductor apparatus and manufacturing method thereof
TW097127083A TW200905766A (en) 2007-07-20 2008-07-17 Semiconductor apparatus and manufacturing method thereof
KR1020080069978A KR20090009737A (ko) 2007-07-20 2008-07-18 반도체장치 및 그 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007190030A JP5110995B2 (ja) 2007-07-20 2007-07-20 積層型半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
JP2009027039A JP2009027039A (ja) 2009-02-05
JP2009027039A5 JP2009027039A5 (https=) 2010-05-27
JP5110995B2 true JP5110995B2 (ja) 2012-12-26

Family

ID=40264182

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007190030A Expired - Fee Related JP5110995B2 (ja) 2007-07-20 2007-07-20 積層型半導体装置及びその製造方法

Country Status (4)

Country Link
US (1) US20090020887A1 (https=)
JP (1) JP5110995B2 (https=)
KR (1) KR20090009737A (https=)
TW (1) TW200905766A (https=)

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US8704379B2 (en) 2007-09-10 2014-04-22 Invensas Corporation Semiconductor die mount by conformal die coating
US8178978B2 (en) 2008-03-12 2012-05-15 Vertical Circuits, Inc. Support mounted electrically interconnected die assembly
US7863159B2 (en) 2008-06-19 2011-01-04 Vertical Circuits, Inc. Semiconductor die separation method
US20100140811A1 (en) * 2008-12-09 2010-06-10 Vertical Circuits, Inc. Semiconductor die interconnect formed by aerosol application of electrically conductive material
US9153517B2 (en) 2008-05-20 2015-10-06 Invensas Corporation Electrical connector between die pad and z-interconnect for stacked die assemblies
JP5112275B2 (ja) * 2008-12-16 2013-01-09 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
JP5136449B2 (ja) * 2009-02-06 2013-02-06 富士通株式会社 半導体装置の製造方法
JP5215244B2 (ja) * 2009-06-18 2013-06-19 新光電気工業株式会社 半導体装置
KR101088822B1 (ko) 2009-08-10 2011-12-01 주식회사 하이닉스반도체 반도체 패키지
WO2011056668A2 (en) 2009-10-27 2011-05-12 Vertical Circuits, Inc. Selective die electrical insulation additive process
TWI544604B (zh) 2009-11-04 2016-08-01 英維瑟斯公司 具有降低應力電互連的堆疊晶粒總成
KR102099878B1 (ko) * 2013-07-11 2020-04-10 삼성전자 주식회사 반도체 패키지
US9490195B1 (en) 2015-07-17 2016-11-08 Invensas Corporation Wafer-level flipped die stacks with leadframes or metal foil interconnects
US9871019B2 (en) 2015-07-17 2018-01-16 Invensas Corporation Flipped die stack assemblies with leadframe interconnects
US9825002B2 (en) 2015-07-17 2017-11-21 Invensas Corporation Flipped die stack
US9508691B1 (en) 2015-12-16 2016-11-29 Invensas Corporation Flipped die stacks with multiple rows of leadframe interconnects
US10566310B2 (en) 2016-04-11 2020-02-18 Invensas Corporation Microelectronic packages having stacked die and wire bond interconnects
US9595511B1 (en) 2016-05-12 2017-03-14 Invensas Corporation Microelectronic packages and assemblies with improved flyby signaling operation
US9728524B1 (en) 2016-06-30 2017-08-08 Invensas Corporation Enhanced density assembly having microelectronic packages mounted at substantial angle to board
CN111081687B (zh) * 2019-12-16 2022-02-01 东莞记忆存储科技有限公司 一种堆叠式芯片封装结构及其封装方法
JP2023111187A (ja) * 2022-01-31 2023-08-10 セイコーエプソン株式会社 電子機器、ロボットおよび移動ステージ
US12456707B2 (en) * 2022-10-06 2025-10-28 Texas Instruments Incorporated Stacked clip design for GaN half bridge IPM

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JPS4922224A (https=) * 1972-05-01 1974-02-27
US5313096A (en) * 1992-03-16 1994-05-17 Dense-Pac Microsystems, Inc. IC chip package having chip attached to and wire bonded within an overlying substrate
JPH10335374A (ja) * 1997-06-04 1998-12-18 Fujitsu Ltd 半導体装置及び半導体装置モジュール
KR100536823B1 (ko) * 1997-08-22 2005-12-16 큐빅 메모리, 인코포레이티드 열전도성 에폭시 예비성형체를 갖는 실리콘 세그먼트용 수직 상호접속 프로세스
JP3476383B2 (ja) * 1999-05-27 2003-12-10 シャープ株式会社 半導体積層パッケージ
JP3879351B2 (ja) * 2000-01-27 2007-02-14 セイコーエプソン株式会社 半導体チップの製造方法
JP2003142518A (ja) * 2001-11-02 2003-05-16 Nec Electronics Corp 半導体製造装置、半導体製造方法、半導体装置及び電子装置
JP2004303884A (ja) * 2003-03-31 2004-10-28 Seiko Epson Corp 三次元実装モジュールの製造方法とその方法で得られる三次元実装モジュール
US7215018B2 (en) * 2004-04-13 2007-05-08 Vertical Circuits, Inc. Stacked die BGA or LGA component assembly
JP5049684B2 (ja) * 2007-07-20 2012-10-17 新光電気工業株式会社 積層型半導体装置及びその製造方法

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JP2009027039A (ja) 2009-02-05
TW200905766A (en) 2009-02-01
KR20090009737A (ko) 2009-01-23
US20090020887A1 (en) 2009-01-22

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