JP5103861B2 - 半導体装置、半導体装置の製造方法、回路基板および電子機器 - Google Patents

半導体装置、半導体装置の製造方法、回路基板および電子機器 Download PDF

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Publication number
JP5103861B2
JP5103861B2 JP2006280113A JP2006280113A JP5103861B2 JP 5103861 B2 JP5103861 B2 JP 5103861B2 JP 2006280113 A JP2006280113 A JP 2006280113A JP 2006280113 A JP2006280113 A JP 2006280113A JP 5103861 B2 JP5103861 B2 JP 5103861B2
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Prior art keywords
insulating film
electrode
semiconductor device
substrate
electrode pad
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JP2006280113A
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Japanese (ja)
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JP2008098498A (ja
JP2008098498A5 (https=
Inventor
好彦 横山
伸晃 橋元
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Seiko Epson Corp
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Seiko Epson Corp
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Priority to JP2006280113A priority Critical patent/JP5103861B2/ja
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Publication of JP2008098498A5 publication Critical patent/JP2008098498A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2006280113A 2006-10-13 2006-10-13 半導体装置、半導体装置の製造方法、回路基板および電子機器 Active JP5103861B2 (ja)

Priority Applications (1)

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JP2006280113A JP5103861B2 (ja) 2006-10-13 2006-10-13 半導体装置、半導体装置の製造方法、回路基板および電子機器

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Application Number Priority Date Filing Date Title
JP2006280113A JP5103861B2 (ja) 2006-10-13 2006-10-13 半導体装置、半導体装置の製造方法、回路基板および電子機器

Publications (3)

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JP2008098498A JP2008098498A (ja) 2008-04-24
JP2008098498A5 JP2008098498A5 (https=) 2009-11-19
JP5103861B2 true JP5103861B2 (ja) 2012-12-19

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JP2006280113A Active JP5103861B2 (ja) 2006-10-13 2006-10-13 半導体装置、半導体装置の製造方法、回路基板および電子機器

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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5539624B2 (ja) * 2008-04-28 2014-07-02 ラピスセミコンダクタ株式会社 薄膜抵抗素子、及び薄膜抵抗素子の製造方法
US7786600B2 (en) * 2008-06-30 2010-08-31 Hynix Semiconductor Inc. Circuit substrate having circuit wire formed of conductive polarization particles, method of manufacturing the circuit substrate and semiconductor package having the circuit wire
EP2463896B1 (en) * 2010-12-07 2020-04-15 IMEC vzw Method for forming through-substrate vias surrounded by isolation trenches with an airgap and corresponding device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3983996B2 (ja) * 2001-04-23 2007-09-26 株式会社ルネサステクノロジ 半導体集積回路装置
JP2004095849A (ja) * 2002-08-30 2004-03-25 Fujikura Ltd 貫通電極付き半導体基板の製造方法、貫通電極付き半導体デバイスの製造方法
JP2005093486A (ja) * 2003-09-12 2005-04-07 Seiko Epson Corp 半導体装置の製造方法及び半導体装置
JP3821125B2 (ja) * 2003-12-18 2006-09-13 セイコーエプソン株式会社 半導体装置の製造方法、半導体装置、回路基板、電子機器
JP4873517B2 (ja) * 2004-10-28 2012-02-08 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法

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