JP5079342B2 - マルチプロセッサ装置 - Google Patents

マルチプロセッサ装置 Download PDF

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Publication number
JP5079342B2
JP5079342B2 JP2007011367A JP2007011367A JP5079342B2 JP 5079342 B2 JP5079342 B2 JP 5079342B2 JP 2007011367 A JP2007011367 A JP 2007011367A JP 2007011367 A JP2007011367 A JP 2007011367A JP 5079342 B2 JP5079342 B2 JP 5079342B2
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Japan
Prior art keywords
bus
cpu
clock
processors
external
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JP2007011367A
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Japanese (ja)
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JP2008176699A5 (enExample
JP2008176699A (ja
Inventor
幸一 石見
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Renesas Electronics Corp
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Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2007011367A priority Critical patent/JP5079342B2/ja
Priority to US11/970,732 priority patent/US8200878B2/en
Publication of JP2008176699A publication Critical patent/JP2008176699A/ja
Publication of JP2008176699A5 publication Critical patent/JP2008176699A5/ja
Priority to US13/471,968 priority patent/US8621127B2/en
Application granted granted Critical
Publication of JP5079342B2 publication Critical patent/JP5079342B2/ja
Priority to US14/103,809 priority patent/US20140101353A1/en
Priority to US15/415,079 priority patent/US10372654B2/en
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4031—Coupling between buses using bus bridges with arbitration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3293—Power saving characterised by the action undertaken by switching to a less power-consuming processor, e.g. sub-CPU
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Microcomputers (AREA)
  • Multi Processors (AREA)
JP2007011367A 2007-01-22 2007-01-22 マルチプロセッサ装置 Active JP5079342B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2007011367A JP5079342B2 (ja) 2007-01-22 2007-01-22 マルチプロセッサ装置
US11/970,732 US8200878B2 (en) 2007-01-22 2008-01-08 Multi-processor device with groups of processors consisting of respective separate external bus interfaces
US13/471,968 US8621127B2 (en) 2007-01-22 2012-05-15 Multi-processor device with groups of processors and respective separate external bus interfaces
US14/103,809 US20140101353A1 (en) 2007-01-22 2013-12-11 Multi-processor device
US15/415,079 US10372654B2 (en) 2007-01-22 2017-01-25 Multi-processor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007011367A JP5079342B2 (ja) 2007-01-22 2007-01-22 マルチプロセッサ装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2011047212A Division JP5432199B2 (ja) 2011-03-04 2011-03-04 マルチプロセッサ装置

Publications (3)

Publication Number Publication Date
JP2008176699A JP2008176699A (ja) 2008-07-31
JP2008176699A5 JP2008176699A5 (enExample) 2010-03-04
JP5079342B2 true JP5079342B2 (ja) 2012-11-21

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007011367A Active JP5079342B2 (ja) 2007-01-22 2007-01-22 マルチプロセッサ装置

Country Status (2)

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US (4) US8200878B2 (enExample)
JP (1) JP5079342B2 (enExample)

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JP5079342B2 (ja) * 2007-01-22 2012-11-21 ルネサスエレクトロニクス株式会社 マルチプロセッサ装置
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US10372654B2 (en) 2019-08-06
US20080282012A1 (en) 2008-11-13
US8621127B2 (en) 2013-12-31
US20120226847A1 (en) 2012-09-06

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