JP4027874B2 - クロック変更回路 - Google Patents
クロック変更回路 Download PDFInfo
- Publication number
- JP4027874B2 JP4027874B2 JP2003355061A JP2003355061A JP4027874B2 JP 4027874 B2 JP4027874 B2 JP 4027874B2 JP 2003355061 A JP2003355061 A JP 2003355061A JP 2003355061 A JP2003355061 A JP 2003355061A JP 4027874 B2 JP4027874 B2 JP 4027874B2
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- Prior art keywords
- clock
- circuit
- frequency
- clock signal
- signal
- Prior art date
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- 230000008859 change Effects 0.000 title claims description 22
- 206010044048 Tooth missing Diseases 0.000 claims description 28
- 230000007704 transition Effects 0.000 claims description 18
- 238000010586 diagram Methods 0.000 description 8
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 7
- 230000007423 decrease Effects 0.000 description 5
- 230000005856 abnormality Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Images
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Manipulation Of Pulses (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
11 分周器
12 セレクタ回路
13 歯抜けクロック生成回路
14 制御回路
21 カウンタ回路
22 比較器
23 アンド回路
24 制御信号生成回路
25 時間選択回路
26 タイマ
27 レジスタ
28 レジスタ
Claims (10)
- 原クロック信号の周波数を制御して出力クロック信号を生成するクロック生成回路と、
該出力クロック信号で動作する外部回路の第1の動作モードから第2の動作モードへの切り替えを示す動作モード切替信号に応じて該クロック生成回路を制御することで、該第1の動作モードでの第1の周波数から該第2の動作モードでの第2の周波数に該出力クロック信号を変化させる途中に、該第1の周波数と該第2の周波数の間の第3の周波数を介在させる制御回路
を含み、該クロック生成回路は、ある設定されたパルス数毎に所定数のパルスを選択して通過させそれ以外のパルスを間引く動作を実行することにより前記原クロック信号の周波数のn/m(n及びmは整数)の周波数のクロック信号を生成し、該n/mの周波数のクロック信号を前記第3の周波数の出力クロック信号として所定の期間持続させることを特徴とするクロック変更回路。 - 該制御回路は、該第3の周波数を該第1の周波数と該第2の周波数の間で段階的に変化させるように該クロック生成回路を制御することを特徴とする請求項1記載のクロック変更回路。
- 該クロック生成回路は、
分周動作を実行する分周回路と
パルスを間引く動作を実行する歯抜けクロック生成回路
を含むことを特徴とする請求項1記載のクロック変更回路。 - 該クロック生成回路は、
該原クロック信号を分周して1つ又は複数の分周クロック信号を生成する分周回路と、
該原クロック信号と該分周クロック信号から1つを選択クロック信号として選択する選択回路と、
該選択クロック信号のパルスを間引くことで出力クロック信号を生成する歯抜けクロック生成回路
を含み、該制御回路は該動作モード切替信号に応じて該選択回路の選択動作と該歯抜けクロック生成回路の間引き動作とを制御することを特徴とする請求項1記載のクロック変更回路。 - 該制御回路は、該第3の周波数を維持する時間の長さをデータとして格納する記憶回路を含むことを特徴とする請求項4記載のクロック変更回路。
- 該記憶回路は、該データを該動作モード切替信号の種類に応じて複数格納することを特徴とする請求項5記載のクロック変更回路。
- 該制御回路は、該歯抜けクロック生成回路によるパルスの間引き率を設定するレジスタを更に含むことを特徴とする請求項4記載のクロック変更回路。
- 該レジスタは、該パルスの間引き率を該動作モード切替信号の種類に応じて複数格納することを特徴とする請求項7記載のクロック変更回路。
- 該動作モード切替信号は複数種類の動作モード切替信号を含み、該動作モード切替信号の種類に応じて該制御回路は該クロック生成回路の制御を切り替えることを特徴とする請求項1記載のクロック変更回路。
- 該動作モード切替信号は、該外部回路の動作を停止する状態への遷移を示す動作モード切替信号と、該外部回路の動作を復帰する状態への遷移を示す動作モード切替信号を含むことを特徴とする請求項9記載のクロック変更回路。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003355061A JP4027874B2 (ja) | 2003-10-15 | 2003-10-15 | クロック変更回路 |
US10/796,005 US7012454B2 (en) | 2003-10-15 | 2004-03-10 | Clock shift circuit for gradual frequency change |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003355061A JP4027874B2 (ja) | 2003-10-15 | 2003-10-15 | クロック変更回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005122374A JP2005122374A (ja) | 2005-05-12 |
JP4027874B2 true JP4027874B2 (ja) | 2007-12-26 |
Family
ID=34509748
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003355061A Expired - Lifetime JP4027874B2 (ja) | 2003-10-15 | 2003-10-15 | クロック変更回路 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7012454B2 (ja) |
JP (1) | JP4027874B2 (ja) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7409162B2 (en) * | 2003-10-30 | 2008-08-05 | Magiq Technologies, Inc | Timing error reduction in QKD systems |
US7233187B2 (en) * | 2004-08-16 | 2007-06-19 | Magiq Technologies, Inc. | Dual-mode pulse generator |
US7605723B2 (en) * | 2004-12-14 | 2009-10-20 | Cirrus Logic, Inc. | Circuits and methods for implementing mode selection in multiple-mode integrated circuits |
US7587622B2 (en) * | 2005-01-11 | 2009-09-08 | Altera Corporation | Power management of components having clock processing circuits |
US7602222B2 (en) * | 2005-09-30 | 2009-10-13 | Mosaid Technologies Incorporated | Power up circuit with low power sleep mode operation |
US20070150765A1 (en) * | 2005-12-26 | 2007-06-28 | Takayuki Ochiai | Information processing apparatus having electronic device whose operating speed is controlled, and method of controlling the operating speed of the electronic device |
US7752476B2 (en) * | 2006-05-17 | 2010-07-06 | Advanced Micro Devices, Inc. | Fast transition from low-speed mode to high-speed mode in high-speed interfaces |
JP4763049B2 (ja) * | 2006-05-24 | 2011-08-31 | シャープ株式会社 | カウンタ回路を備える制御信号生成回路ならびに表示装置 |
KR100826975B1 (ko) * | 2006-06-30 | 2008-05-02 | 주식회사 하이닉스반도체 | 클럭 생성 회로 및 클럭 생성 방법 |
KR100723537B1 (ko) | 2006-09-12 | 2007-05-30 | 삼성전자주식회사 | 클럭 신호 발생 방법 및 장치와 이를 이용한 클럭 주파수제어 방법 및 장치 |
JP5079342B2 (ja) | 2007-01-22 | 2012-11-21 | ルネサスエレクトロニクス株式会社 | マルチプロセッサ装置 |
JP5499693B2 (ja) | 2009-12-24 | 2014-05-21 | 富士通セミコンダクター株式会社 | 半導体集積回路、半導体集積回路の制御方法及びその制御プログラム |
US20140122916A1 (en) * | 2012-10-31 | 2014-05-01 | Guadalupe J. Garcia | Reducing the overhead associated with frequency changes in processors |
US8884663B2 (en) * | 2013-02-25 | 2014-11-11 | Advanced Micro Devices, Inc. | State machine for low-noise clocking of high frequency clock |
JP5575947B2 (ja) * | 2013-04-04 | 2014-08-20 | ルネサスエレクトロニクス株式会社 | マルチプロセッサ装置 |
US9582027B2 (en) * | 2014-06-09 | 2017-02-28 | Qualcomm Incorporated | Clock swallowing device for reducing voltage noise |
US9817465B2 (en) * | 2014-06-27 | 2017-11-14 | Microsoft Technology Licensing, Llc | Low latency computer system power reduction |
US9778676B2 (en) | 2015-08-03 | 2017-10-03 | Qualcomm Incorporated | Power distribution network (PDN) droop/overshoot mitigation in dynamic frequency scaling |
US9996138B2 (en) * | 2015-09-04 | 2018-06-12 | Mediatek Inc. | Electronic system and related clock managing method |
US9999025B2 (en) * | 2016-03-08 | 2018-06-12 | Verily Life Sciences Llc | Beacon using an FBAR-based oscillator |
US10212657B2 (en) | 2016-04-27 | 2019-02-19 | Verily Life Sciences Llc | Bluetooth low energy beacon with FBAR-based oscillator-per-channel |
US10097387B1 (en) | 2016-08-15 | 2018-10-09 | Verily Life Sciences Llc | Temperature-stable FBAR transmitter |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0638119A (ja) * | 1992-06-15 | 1994-02-10 | Toshiba Corp | 映像表示装置 |
US5822596A (en) * | 1995-11-06 | 1998-10-13 | International Business Machines Corporation | Controlling power up using clock gating |
JPH11143573A (ja) * | 1997-11-10 | 1999-05-28 | Fujitsu Ltd | クロック供給方法及び情報処理装置 |
JPH11154370A (ja) * | 1997-11-20 | 1999-06-08 | Teac Corp | ディスク装置 |
JP2000183729A (ja) | 1998-12-15 | 2000-06-30 | Nec Eng Ltd | クロック発生回路 |
JP3552566B2 (ja) | 1999-01-14 | 2004-08-11 | Jfeエンジニアリング株式会社 | 廃プラスチックの資源化方法 |
JP4077988B2 (ja) * | 1999-07-19 | 2008-04-23 | 株式会社ルネサステクノロジ | クロック生成回路 |
JP2001213002A (ja) | 2000-02-04 | 2001-08-07 | Fuji Photo Film Co Ltd | 画像記録装置 |
US6448996B2 (en) * | 2000-02-04 | 2002-09-10 | Fuji Photo Film Co., Ltd. | Image recording apparatus and method of generating pixel clock |
JP2002202829A (ja) | 2000-12-28 | 2002-07-19 | Fujitsu Ltd | マイクロコンピュータ |
-
2003
- 2003-10-15 JP JP2003355061A patent/JP4027874B2/ja not_active Expired - Lifetime
-
2004
- 2004-03-10 US US10/796,005 patent/US7012454B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US7012454B2 (en) | 2006-03-14 |
US20050083098A1 (en) | 2005-04-21 |
JP2005122374A (ja) | 2005-05-12 |
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