JP5064689B2 - 半導体基板の埋設分離領域を形成する方法及び埋設分離領域をもつ半導体デバイス - Google Patents

半導体基板の埋設分離領域を形成する方法及び埋設分離領域をもつ半導体デバイス Download PDF

Info

Publication number
JP5064689B2
JP5064689B2 JP2006018863A JP2006018863A JP5064689B2 JP 5064689 B2 JP5064689 B2 JP 5064689B2 JP 2006018863 A JP2006018863 A JP 2006018863A JP 2006018863 A JP2006018863 A JP 2006018863A JP 5064689 B2 JP5064689 B2 JP 5064689B2
Authority
JP
Japan
Prior art keywords
layer
substrate
forming
opening
patterned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006018863A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006210927A5 (enExample
JP2006210927A (ja
Inventor
トシハル・フルカワ
マーク・シー・ヘイキー
スティーブン・ジェイ・ホームズ
デビッド・ブイ・ホラック
チャールズ・ダブリュー・コバーガー・サード
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JP2006210927A publication Critical patent/JP2006210927A/ja
Publication of JP2006210927A5 publication Critical patent/JP2006210927A5/ja
Application granted granted Critical
Publication of JP5064689B2 publication Critical patent/JP5064689B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76267—Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6744—Monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Nanotechnology (AREA)
  • Chemical & Material Sciences (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2006018863A 2005-01-28 2006-01-27 半導体基板の埋設分離領域を形成する方法及び埋設分離領域をもつ半導体デバイス Expired - Fee Related JP5064689B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/905,980 US7071047B1 (en) 2005-01-28 2005-01-28 Method of forming buried isolation regions in semiconductor substrates and semiconductor devices with buried isolation regions
US10/905980 2005-01-28

Publications (3)

Publication Number Publication Date
JP2006210927A JP2006210927A (ja) 2006-08-10
JP2006210927A5 JP2006210927A5 (enExample) 2008-11-13
JP5064689B2 true JP5064689B2 (ja) 2012-10-31

Family

ID=36613693

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006018863A Expired - Fee Related JP5064689B2 (ja) 2005-01-28 2006-01-27 半導体基板の埋設分離領域を形成する方法及び埋設分離領域をもつ半導体デバイス

Country Status (4)

Country Link
US (3) US7071047B1 (enExample)
JP (1) JP5064689B2 (enExample)
CN (1) CN100517635C (enExample)
TW (1) TWI374507B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10700263B2 (en) 2018-02-01 2020-06-30 International Business Machines Corporation Annealed seed layer for magnetic random access memory

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7456476B2 (en) * 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
KR100605497B1 (ko) * 2003-11-27 2006-07-28 삼성전자주식회사 에스오아이 기판들을 제조하는 방법들, 이를 사용하여반도체 소자들을 제조하는 방법들 및 그에 의해 제조된반도체 소자들
US7042009B2 (en) 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US20100117152A1 (en) * 2007-06-28 2010-05-13 Chang-Woo Oh Semiconductor devices
KR100555569B1 (ko) 2004-08-06 2006-03-03 삼성전자주식회사 절연막에 의해 제한된 채널영역을 갖는 반도체 소자 및 그제조방법
KR100843717B1 (ko) * 2007-06-28 2008-07-04 삼성전자주식회사 플로팅 바디 소자 및 벌크 바디 소자를 갖는 반도체소자 및그 제조방법
US7332439B2 (en) * 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US20060131265A1 (en) * 2004-12-17 2006-06-22 Samper Victor D Method of forming branched structures
KR100631905B1 (ko) * 2005-02-22 2006-10-11 삼성전기주식회사 질화물 단결정 기판 제조방법 및 이를 이용한 질화물 반도체 발광소자 제조방법
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7479421B2 (en) 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US20070090416A1 (en) 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US7241695B2 (en) * 2005-10-06 2007-07-10 Freescale Semiconductor, Inc. Semiconductor device having nano-pillars and method therefor
US20070249138A1 (en) * 2006-04-24 2007-10-25 Micron Technology, Inc. Buried dielectric slab structure for CMOS imager
US20100047959A1 (en) * 2006-08-07 2010-02-25 Emcore Solar Power, Inc. Epitaxial Lift Off on Film Mounted Inverted Metamorphic Multijunction Solar Cells
US7482270B2 (en) * 2006-12-05 2009-01-27 International Business Machines Corporation Fully and uniformly silicided gate structure and method for forming same
US7514339B2 (en) * 2007-01-09 2009-04-07 International Business Machines Corporation Method for fabricating shallow trench isolation structures using diblock copolymer patterning
US8299455B2 (en) 2007-10-15 2012-10-30 International Business Machines Corporation Semiconductor structures having improved contact resistance
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
FR2990794B1 (fr) * 2012-05-16 2016-11-18 Commissariat Energie Atomique Procede de realisation d'un substrat muni de zones actives variees et de transistors planaires et tridimensionnels
FR3000235B1 (fr) * 2012-12-21 2016-06-24 Arkema France Procede de fabrication de masques nanolithographiques
JP6299658B2 (ja) * 2015-04-22 2018-03-28 トヨタ自動車株式会社 絶縁ゲート型スイッチング素子
JP2016207830A (ja) * 2015-04-22 2016-12-08 トヨタ自動車株式会社 絶縁ゲート型スイッチング素子とその制御方法
US9722057B2 (en) * 2015-06-23 2017-08-01 Global Foundries Inc. Bipolar junction transistors with a buried dielectric region in the active device region
KR20220158173A (ko) 2021-05-21 2022-11-30 삼성전자주식회사 반도체 장치
US20240071833A1 (en) * 2022-08-25 2024-02-29 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid fin-dielectric semiconductor device

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH034514A (ja) * 1989-06-01 1991-01-10 Clarion Co Ltd ウエハの製造方法
US5243559A (en) * 1990-12-12 1993-09-07 Nippon Steel Corporation Semiconductor memory device
JPH0590396A (ja) 1991-09-30 1993-04-09 Mitsubishi Electric Corp 半導体装置及びその製造方法
JPH07502479A (ja) 1991-11-22 1995-03-16 ザ リージェンツ オブ ザ ユニバーシティ オブ カリフォルニア 自己集合性単一層を使って固体無機表面に共有結合した半導体微少結晶
US5298773A (en) 1992-08-17 1994-03-29 United Technologies Corporation Silicon-on-insulator H-transistor layout for gate arrays
US5338571A (en) 1993-02-10 1994-08-16 Northwestern University Method of forming self-assembled, mono- and multi-layer fullerene film and coated substrates produced thereby
JP3036619B2 (ja) 1994-03-23 2000-04-24 コマツ電子金属株式会社 Ｓｏｉ基板の製造方法およびｓｏｉ基板
EP0694960B1 (en) * 1994-07-25 2002-07-03 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe Process for the localized reduction of the lifetime of charge carriers
US5731619A (en) * 1996-05-22 1998-03-24 International Business Machines Corporation CMOS structure with FETS having isolated wells with merged depletions and methods of making same
FR2758907B1 (fr) * 1997-01-27 1999-05-07 Commissariat Energie Atomique Procede d'obtention d'un film mince, notamment semiconducteur, comportant une zone protegee des ions, et impliquant une etape d'implantation ionique
US5963817A (en) 1997-10-16 1999-10-05 International Business Machines Corporation Bulk and strained silicon on insulator using local selective oxidation
JP3762136B2 (ja) * 1998-04-24 2006-04-05 株式会社東芝 半導体装置
US6376285B1 (en) 1998-05-28 2002-04-23 Texas Instruments Incorporated Annealed porous silicon with epitaxial layer for SOI
KR100294640B1 (ko) * 1998-12-24 2001-08-07 박종섭 부동 몸체 효과를 제거한 실리콘 이중막 소자 및 그 제조방법
JP4365920B2 (ja) 1999-02-02 2009-11-18 キヤノン株式会社 分離方法及び半導体基板の製造方法
US6362082B1 (en) * 1999-06-28 2002-03-26 Intel Corporation Methodology for control of short channel effects in MOS transistors
US6573565B2 (en) 1999-07-28 2003-06-03 International Business Machines Corporation Method and structure for providing improved thermal conduction for silicon semiconductor devices
JP4074051B2 (ja) * 1999-08-31 2008-04-09 株式会社東芝 半導体基板およびその製造方法
US6221737B1 (en) 1999-09-30 2001-04-24 Philips Electronics North America Corporation Method of making semiconductor devices with graded top oxide and graded drift region
US6521974B1 (en) * 1999-10-14 2003-02-18 Hitachi, Ltd. Bipolar transistor and manufacturing method thereof
US6271094B1 (en) * 2000-02-14 2001-08-07 International Business Machines Corporation Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance
US6579463B1 (en) 2000-08-18 2003-06-17 The Regents Of The University Of Colorado Tunable nanomasks for pattern transfer and nanocluster array formation
US6358813B1 (en) 2000-11-15 2002-03-19 International Business Machines Corporation Method for increasing the capacitance of a semiconductor capacitors
US6444534B1 (en) * 2001-01-30 2002-09-03 Advanced Micro Devices, Inc. SOI semiconductor device opening implantation gettering method
US6551937B2 (en) 2001-08-23 2003-04-22 Institute Of Microelectronics Process for device using partial SOI
JP2003069029A (ja) 2001-08-27 2003-03-07 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
AU2003241396A1 (en) * 2002-05-07 2003-11-11 Agere Systems, Inc. A multi-layer inductor formed in a semiconductor substrate and having a core of ferromagnetic material
JP4277481B2 (ja) * 2002-05-08 2009-06-10 日本電気株式会社 半導体基板の製造方法、半導体装置の製造方法
JP4031329B2 (ja) * 2002-09-19 2008-01-09 株式会社東芝 半導体装置及びその製造方法
US6929984B2 (en) * 2003-07-21 2005-08-16 Micron Technology Inc. Gettering using voids formed by surface transformation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10700263B2 (en) 2018-02-01 2020-06-30 International Business Machines Corporation Annealed seed layer for magnetic random access memory

Also Published As

Publication number Publication date
US7071047B1 (en) 2006-07-04
US7352030B2 (en) 2008-04-01
CN1828861A (zh) 2006-09-06
TWI374507B (en) 2012-10-11
CN100517635C (zh) 2009-07-22
US20060172479A1 (en) 2006-08-03
US20080128811A1 (en) 2008-06-05
TW200711004A (en) 2007-03-16
JP2006210927A (ja) 2006-08-10

Similar Documents

Publication Publication Date Title
JP5064689B2 (ja) 半導体基板の埋設分離領域を形成する方法及び埋設分離領域をもつ半導体デバイス
KR100923193B1 (ko) 나노스케일 다중접합 양자점 소자 및 그 제조방법
KR101248339B1 (ko) 상이한 높이들을 갖는 인접하는 실리콘 핀들을 제조하는 방법
CN102422401B (zh) 用保形氮化物形成耐用由上至下硅纳米线结构的方法和该结构
CN110060972B (zh) 用于后段(beol)互连的自对准过孔及插塞图案化
US8642403B1 (en) Replacement contacts for all-around contacts
JPH03291921A (ja) 集積回路製作方法
US8207028B2 (en) Two-dimensional patterning employing self-assembled material
US7781274B2 (en) Multi-gate field effect transistor and method for manufacturing the same
US20040077107A1 (en) Method of making nanoscopic tunnel
CN101322230B (zh) 半导体器件制造方法
US6211054B1 (en) Method of forming a conductive line and method of forming a local interconnect
KR100325298B1 (ko) 비휘발성 메모리 소자의 제조 방법
TW202109624A (zh) 積體電路的製作方法
JP2004311953A (ja) 超微細チャンネルを有するｍｏｓｆｅｔ素子及びその製造方法
US7135407B2 (en) Method of manufacturing a semiconductor device
TWI703714B (zh) 形成影像感測元件中多晶矽閘極結構之方法、多晶矽閘極結構以及保護影像感測元件的畫素之方法
KR100713326B1 (ko) 반도체 소자의 극 미세 트랜지스터 제작방법
TWI892620B (zh) 半導體記憶體裝置製造方法
KR100511907B1 (ko) 반도체 소자의 제조방법
TW200903728A (en) Methods for fabricating a semiconductor device
KR100779015B1 (ko) 반도체 소자의 제조 방법
KR100314810B1 (ko) 대머신 게이트를 적용한 반도체 소자 제조방법
JP2005197724A (ja) 量子点を用いた非揮発性メモリーの製造方法
KR20030000662A (ko) 반도체 소자의 트랜지스터 제조 방법

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20081001

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20081001

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090206

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120319

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120529

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120706

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120724

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120809

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150817

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees