JP2006210927A5 - - Google Patents

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Publication number
JP2006210927A5
JP2006210927A5 JP2006018863A JP2006018863A JP2006210927A5 JP 2006210927 A5 JP2006210927 A5 JP 2006210927A5 JP 2006018863 A JP2006018863 A JP 2006018863A JP 2006018863 A JP2006018863 A JP 2006018863A JP 2006210927 A5 JP2006210927 A5 JP 2006210927A5
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JP
Japan
Prior art keywords
substrate
layer
forming
opening
top surface
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JP2006018863A
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English (en)
Japanese (ja)
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JP5064689B2 (ja
JP2006210927A (ja
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Priority claimed from US10/905,980 external-priority patent/US7071047B1/en
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Publication of JP2006210927A publication Critical patent/JP2006210927A/ja
Publication of JP2006210927A5 publication Critical patent/JP2006210927A5/ja
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Publication of JP5064689B2 publication Critical patent/JP5064689B2/ja
Expired - Fee Related legal-status Critical Current
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JP2006018863A 2005-01-28 2006-01-27 半導体基板の埋設分離領域を形成する方法及び埋設分離領域をもつ半導体デバイス Expired - Fee Related JP5064689B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/905980 2005-01-28
US10/905,980 US7071047B1 (en) 2005-01-28 2005-01-28 Method of forming buried isolation regions in semiconductor substrates and semiconductor devices with buried isolation regions

Publications (3)

Publication Number Publication Date
JP2006210927A JP2006210927A (ja) 2006-08-10
JP2006210927A5 true JP2006210927A5 (enExample) 2008-11-13
JP5064689B2 JP5064689B2 (ja) 2012-10-31

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ID=36613693

Family Applications (1)

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JP2006018863A Expired - Fee Related JP5064689B2 (ja) 2005-01-28 2006-01-27 半導体基板の埋設分離領域を形成する方法及び埋設分離領域をもつ半導体デバイス

Country Status (4)

Country Link
US (3) US7071047B1 (enExample)
JP (1) JP5064689B2 (enExample)
CN (1) CN100517635C (enExample)
TW (1) TWI374507B (enExample)

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JP2016207830A (ja) * 2015-04-22 2016-12-08 トヨタ自動車株式会社 絶縁ゲート型スイッチング素子とその制御方法
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