CN100517635C - 形成掩埋隔离区的方法以及具有掩埋隔离区的半导体器件 - Google Patents

形成掩埋隔离区的方法以及具有掩埋隔离区的半导体器件 Download PDF

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CN100517635C
CN100517635C CNB2006100027404A CN200610002740A CN100517635C CN 100517635 C CN100517635 C CN 100517635C CN B2006100027404 A CNB2006100027404 A CN B2006100027404A CN 200610002740 A CN200610002740 A CN 200610002740A CN 100517635 C CN100517635 C CN 100517635C
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top surface
layer
silicon substrate
silicon
patterned
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CN1828861A (zh
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S·J·霍姆斯
M·C·哈基
C·W·科布格尔三世
古川俊治
D·V·霍拉克
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Core Usa Second LLC
GlobalFoundries Inc
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    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
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    • H01L21/3105—After-treatment
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76267—Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
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    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
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  • Thin Film Transistor (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Recrystallisation Techniques (AREA)
CNB2006100027404A 2005-01-28 2006-01-25 形成掩埋隔离区的方法以及具有掩埋隔离区的半导体器件 Expired - Fee Related CN100517635C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/905,980 2005-01-28
US10/905,980 US7071047B1 (en) 2005-01-28 2005-01-28 Method of forming buried isolation regions in semiconductor substrates and semiconductor devices with buried isolation regions

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CN1828861A CN1828861A (zh) 2006-09-06
CN100517635C true CN100517635C (zh) 2009-07-22

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US (3) US7071047B1 (enExample)
JP (1) JP5064689B2 (enExample)
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TW (1) TWI374507B (enExample)

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US20060172479A1 (en) 2006-08-03
US7071047B1 (en) 2006-07-04
TW200711004A (en) 2007-03-16
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US20080128811A1 (en) 2008-06-05
US7352030B2 (en) 2008-04-01
CN1828861A (zh) 2006-09-06

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