JP5015802B2 - 選択的な金属めっきにより形成される配線構造体及びその形成方法 - Google Patents
選択的な金属めっきにより形成される配線構造体及びその形成方法 Download PDFInfo
- Publication number
- JP5015802B2 JP5015802B2 JP2007550566A JP2007550566A JP5015802B2 JP 5015802 B2 JP5015802 B2 JP 5015802B2 JP 2007550566 A JP2007550566 A JP 2007550566A JP 2007550566 A JP2007550566 A JP 2007550566A JP 5015802 B2 JP5015802 B2 JP 5015802B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring structure
- wiring
- insulating mandrel
- mandrel
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/038—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers covering conductive structures
- H10W20/039—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers covering conductive structures also covering sidewalls of the conductive structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
- H10W20/044—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroless plating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/052—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein
- H10W20/0523—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein by irradiating with ultraviolet or particle radiation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
- H10W20/0636—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material the conductive members being on sidewalls
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/072—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising air gaps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
- H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/098—Manufacture or treatment of dielectric parts thereof by filling between adjacent conductive parts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/435—Cross-sectional shapes or dispositions of interconnections
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/44—Conductive materials thereof
- H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
- H10W20/46—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising air gaps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
- H10W20/0425—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers comprising multiple stacked seed or nucleation layers
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Structure Of Printed Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/905,590 US7345370B2 (en) | 2005-01-12 | 2005-01-12 | Wiring patterns formed by selective metal plating |
| US10/905,590 | 2005-01-12 | ||
| PCT/US2006/000844 WO2006076377A2 (en) | 2005-01-12 | 2006-01-10 | Wiring patterns formed by selective metal plating |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2008527725A JP2008527725A (ja) | 2008-07-24 |
| JP2008527725A5 JP2008527725A5 (enExample) | 2008-12-11 |
| JP5015802B2 true JP5015802B2 (ja) | 2012-08-29 |
Family
ID=36653820
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007550566A Expired - Fee Related JP5015802B2 (ja) | 2005-01-12 | 2006-01-10 | 選択的な金属めっきにより形成される配線構造体及びその形成方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US7345370B2 (enExample) |
| EP (1) | EP1849187A4 (enExample) |
| JP (1) | JP5015802B2 (enExample) |
| CN (1) | CN100524712C (enExample) |
| WO (1) | WO2006076377A2 (enExample) |
Families Citing this family (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7510939B2 (en) * | 2006-01-31 | 2009-03-31 | International Business Machines Corporation | Microelectronic structure by selective deposition |
| US7968008B2 (en) | 2006-08-03 | 2011-06-28 | Fry's Metals, Inc. | Particles and inks and films using them |
| US8043931B1 (en) * | 2006-09-18 | 2011-10-25 | Gang Zhang | Methods for forming multi-layer silicon structures |
| US9615463B2 (en) | 2006-09-22 | 2017-04-04 | Oscar Khaselev | Method for producing a high-aspect ratio conductive pattern on a substrate |
| EP2174324B1 (en) * | 2007-08-03 | 2017-01-11 | Alpha Metals, Inc. | Method of manufacturing printed circuit board |
| GB2466255B (en) | 2008-12-17 | 2013-05-22 | Antenova Ltd | Antennas conducive to semiconductor packaging technology and a process for their manufacture |
| US8809128B2 (en) * | 2009-10-26 | 2014-08-19 | Sandisk 3D Llc | Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning |
| US8815747B2 (en) * | 2010-06-03 | 2014-08-26 | Micron Technology, Inc. | Methods of forming patterns on substrates |
| JP2013105891A (ja) * | 2011-11-14 | 2013-05-30 | Toshiba Corp | 半導体装置およびその製造方法 |
| US9034758B2 (en) | 2013-03-15 | 2015-05-19 | Microchip Technology Incorporated | Forming fence conductors using spacer etched trenches |
| US8836128B1 (en) | 2013-03-15 | 2014-09-16 | Microchip Technology Incorporated | Forming fence conductors in an integrated circuit |
| US9583435B2 (en) | 2013-03-15 | 2017-02-28 | Microchip Technology Incorporated | Forming fence conductors using spacer etched trenches |
| US9406331B1 (en) | 2013-06-17 | 2016-08-02 | Western Digital (Fremont), Llc | Method for making ultra-narrow read sensor and read transducer device resulting therefrom |
| US8987008B2 (en) * | 2013-08-20 | 2015-03-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit layout and method with double patterning |
| US9330914B2 (en) | 2013-10-08 | 2016-05-03 | Micron Technology, Inc. | Methods of forming line patterns in substrates |
| US10490497B2 (en) | 2014-06-13 | 2019-11-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Selective formation of conductor nanowires |
| US9312064B1 (en) | 2015-03-02 | 2016-04-12 | Western Digital (Fremont), Llc | Method to fabricate a magnetic head including ion milling of read gap using dual layer hard mask |
| US10037957B2 (en) * | 2016-11-14 | 2018-07-31 | Amkor Technology, Inc. | Semiconductor device and method of manufacturing thereof |
| US9966338B1 (en) * | 2017-04-18 | 2018-05-08 | Globalfoundries Inc. | Pre-spacer self-aligned cut formation |
| US11672128B2 (en) * | 2020-07-20 | 2023-06-06 | Micron Technology, Inc. | Methods of incorporating leaker devices into capacitor configurations to reduce cell disturb, and capacitor configurations incorporating leaker devices |
| US12183630B2 (en) * | 2022-03-09 | 2024-12-31 | International Business Machines Corporation | Additive interconnect formation |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS5687326A (en) | 1979-12-17 | 1981-07-15 | Sony Corp | Method of forming wiring |
| IL84255A (en) | 1987-10-23 | 1993-02-21 | Galram Technology Ind Ltd | Process for removal of post- baked photoresist layer |
| US4919768A (en) | 1989-09-22 | 1990-04-24 | Shipley Company Inc. | Electroplating process |
| US5342501A (en) | 1989-11-21 | 1994-08-30 | Eric F. Harnden | Method for electroplating metal onto a non-conductive substrate treated with basic accelerating solutions for metal plating |
| US5331116A (en) | 1992-04-30 | 1994-07-19 | Sgs-Thomson Microelectronics, Inc. | Structure and method for forming contact structures in integrated circuits |
| US6127257A (en) | 1993-11-18 | 2000-10-03 | Motorola Inc. | Method of making a contact structure |
| US6576976B2 (en) | 1997-01-03 | 2003-06-10 | Integrated Device Technology, Inc. | Semiconductor integrated circuit with an insulation structure having reduced permittivity |
| JPH10261710A (ja) | 1997-03-18 | 1998-09-29 | Sony Corp | 配線形成方法及び半導体装置の製造方法 |
| US6117784A (en) | 1997-11-12 | 2000-09-12 | International Business Machines Corporation | Process for integrated circuit wiring |
| US6040214A (en) | 1998-02-19 | 2000-03-21 | International Business Machines Corporation | Method for making field effect transistors having sub-lithographic gates with vertical side walls |
| KR100635685B1 (ko) * | 1998-05-25 | 2006-10-17 | 가부시키가이샤 히타치세이사쿠쇼 | 반도체장치 및 그 제조방법 |
| AT405842B (de) | 1998-06-19 | 1999-11-25 | Miba Gleitlager Ag | Verfahren zum aufbringen einer metallischen schicht auf eine polymeroberfläche eines werkstückes |
| US6190986B1 (en) | 1999-01-04 | 2001-02-20 | International Business Machines Corporation | Method of producing sulithographic fuses using a phase shift mask |
| US7007378B2 (en) * | 1999-06-24 | 2006-03-07 | International Business Machines Corporation | Process for manufacturing a printed wiring board |
| US6440839B1 (en) | 1999-08-18 | 2002-08-27 | Advanced Micro Devices, Inc. | Selective air gap insulation |
| US6815329B2 (en) * | 2000-02-08 | 2004-11-09 | International Business Machines Corporation | Multilayer interconnect structure containing air gaps and method for making |
| DE60125338T2 (de) * | 2000-03-07 | 2007-07-05 | Asm International N.V. | Gradierte dünne schichten |
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| JP2002075995A (ja) | 2000-08-24 | 2002-03-15 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
| TWI226103B (en) | 2000-08-31 | 2005-01-01 | Georgia Tech Res Inst | Fabrication of semiconductor devices with air gaps for ultra low capacitance interconnections and methods of making same |
| US6660154B2 (en) | 2000-10-25 | 2003-12-09 | Shipley Company, L.L.C. | Seed layer |
| JP2002170885A (ja) * | 2000-12-04 | 2002-06-14 | Fujitsu Ltd | 半導体装置の製造方法 |
| US20020092673A1 (en) * | 2001-01-17 | 2002-07-18 | International Business Machines Corporation | Tungsten encapsulated copper interconnections using electroplating |
| US6653231B2 (en) | 2001-03-28 | 2003-11-25 | Advanced Micro Devices, Inc. | Process for reducing the critical dimensions of integrated circuit device features |
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| JP3561240B2 (ja) * | 2001-05-25 | 2004-09-02 | 京セラ株式会社 | 配線基板の製造方法 |
| US20030008243A1 (en) * | 2001-07-09 | 2003-01-09 | Micron Technology, Inc. | Copper electroless deposition technology for ULSI metalization |
| TWI312166B (en) * | 2001-09-28 | 2009-07-11 | Toppan Printing Co Ltd | Multi-layer circuit board, integrated circuit package, and manufacturing method for multi-layer circuit board |
| JP3967108B2 (ja) | 2001-10-26 | 2007-08-29 | 富士通株式会社 | 半導体装置およびその製造方法 |
| US20030116439A1 (en) * | 2001-12-21 | 2003-06-26 | International Business Machines Corporation | Method for forming encapsulated metal interconnect structures in semiconductor integrated circuit devices |
| JP4063619B2 (ja) | 2002-03-13 | 2008-03-19 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP2003298232A (ja) * | 2002-04-02 | 2003-10-17 | Sony Corp | 多層配線基板の製造方法および多層配線基板 |
| US6713396B2 (en) | 2002-04-29 | 2004-03-30 | Hewlett-Packard Development Company, L.P. | Method of fabricating high density sub-lithographic features on a substrate |
| US6716753B1 (en) * | 2002-07-29 | 2004-04-06 | Taiwan Semiconductor Manufacturing Company | Method for forming a self-passivated copper interconnect structure |
| US6911229B2 (en) * | 2002-08-09 | 2005-06-28 | International Business Machines Corporation | Structure comprising an interlayer of palladium and/or platinum and method for fabrication thereof |
| JP2004103911A (ja) | 2002-09-11 | 2004-04-02 | Shinko Electric Ind Co Ltd | 配線形成方法 |
| US7001833B2 (en) * | 2002-09-27 | 2006-02-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming openings in low-k dielectric layers |
| US7148265B2 (en) * | 2002-09-30 | 2006-12-12 | Rohm And Haas Electronic Materials Llc | Functional polymer |
| US6936536B2 (en) * | 2002-10-09 | 2005-08-30 | Micron Technology, Inc. | Methods of forming conductive through-wafer vias |
| US6900126B2 (en) * | 2002-11-20 | 2005-05-31 | International Business Machines Corporation | Method of forming metallized pattern |
| US20040108136A1 (en) * | 2002-12-04 | 2004-06-10 | International Business Machines Corporation | Structure comprising a barrier layer of a tungsten alloy comprising cobalt and/or nickel |
| JP2004273969A (ja) * | 2003-03-12 | 2004-09-30 | Sony Corp | 磁気記憶装置の製造方法 |
| US7485162B2 (en) * | 2003-09-30 | 2009-02-03 | Fujimi Incorporated | Polishing composition |
| US7068138B2 (en) * | 2004-01-29 | 2006-06-27 | International Business Machines Corporation | High Q factor integrated circuit inductor |
| US7052932B2 (en) * | 2004-02-24 | 2006-05-30 | Chartered Semiconductor Manufacturing Ltd. | Oxygen doped SiC for Cu barrier and etch stop layer in dual damascene fabrication |
| US20060145350A1 (en) * | 2004-12-30 | 2006-07-06 | Harald Gross | High frequency conductors for packages of integrated circuits |
| JP2007163268A (ja) * | 2005-12-13 | 2007-06-28 | Canon Inc | 酵素電極 |
-
2005
- 2005-01-12 US US10/905,590 patent/US7345370B2/en not_active Expired - Lifetime
-
2006
- 2006-01-10 EP EP06717977A patent/EP1849187A4/en not_active Withdrawn
- 2006-01-10 WO PCT/US2006/000844 patent/WO2006076377A2/en not_active Ceased
- 2006-01-10 CN CN200680001918.1A patent/CN100524712C/zh not_active Expired - Fee Related
- 2006-01-10 JP JP2007550566A patent/JP5015802B2/ja not_active Expired - Fee Related
-
2007
- 2007-05-08 US US11/745,610 patent/US7521808B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US20070207604A1 (en) | 2007-09-06 |
| EP1849187A4 (en) | 2010-11-17 |
| CN101103459A (zh) | 2008-01-09 |
| US7345370B2 (en) | 2008-03-18 |
| US20060154463A1 (en) | 2006-07-13 |
| EP1849187A2 (en) | 2007-10-31 |
| WO2006076377A3 (en) | 2007-02-08 |
| JP2008527725A (ja) | 2008-07-24 |
| WO2006076377A2 (en) | 2006-07-20 |
| CN100524712C (zh) | 2009-08-05 |
| US7521808B2 (en) | 2009-04-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
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