CN107078040B - 阻挡层的去除方法和半导体结构的形成方法 - Google Patents
阻挡层的去除方法和半导体结构的形成方法 Download PDFInfo
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- 230000004888 barrier function Effects 0.000 title claims abstract description 149
- 238000000034 method Methods 0.000 title claims abstract description 100
- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 229910052751 metal Inorganic materials 0.000 claims abstract description 100
- 239000002184 metal Substances 0.000 claims abstract description 100
- 229910052707 ruthenium Inorganic materials 0.000 claims abstract description 50
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims abstract description 49
- 229910017052 cobalt Inorganic materials 0.000 claims abstract description 41
- 239000010941 cobalt Substances 0.000 claims abstract description 41
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims abstract description 41
- 239000000463 material Substances 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 23
- 239000007789 gas Substances 0.000 claims description 19
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 18
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 17
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 12
- 239000010936 titanium Substances 0.000 claims description 12
- 229910052719 titanium Inorganic materials 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 10
- 229910052715 tantalum Inorganic materials 0.000 claims description 10
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 10
- 239000000126 substance Substances 0.000 claims description 8
- 238000007747 plating Methods 0.000 claims description 4
- IGELFKKMDLGCJO-UHFFFAOYSA-N xenon difluoride Chemical compound F[Xe]F IGELFKKMDLGCJO-UHFFFAOYSA-N 0.000 claims description 4
- ARUUTJKURHLAMI-UHFFFAOYSA-N xenon hexafluoride Chemical compound F[Xe](F)(F)(F)(F)F ARUUTJKURHLAMI-UHFFFAOYSA-N 0.000 claims description 4
- RPSSQXXJRBEGEE-UHFFFAOYSA-N xenon tetrafluoride Chemical compound F[Xe](F)(F)F RPSSQXXJRBEGEE-UHFFFAOYSA-N 0.000 claims description 4
- 239000012808 vapor phase Substances 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 2
- 238000000576 coating method Methods 0.000 claims 2
- 239000000203 mixture Substances 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 229910052681 coesite Inorganic materials 0.000 description 7
- 229910052906 cristobalite Inorganic materials 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 229910052682 stishovite Inorganic materials 0.000 description 7
- 229910052905 tridymite Inorganic materials 0.000 description 7
- 238000000151 deposition Methods 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 239000010937 tungsten Substances 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 4
- 229910020177 SiOF Inorganic materials 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- -1 tungsten nitride Chemical class 0.000 description 3
- 238000005498 polishing Methods 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
本发明揭示了一种阻挡层的去除方法,该阻挡层包括至少一层钌或钴,该阻挡层的去除方法包括:采用热流蚀刻方法去除形成在半导体结构的非凹进区域上包括钌或钴层的阻挡层。本发明还进一步揭示了一种半导体结构的形成方法,包括:提供一半导体结构,该半导体结构包括介质层、形成在介质层上的硬掩膜层、形成在硬掩膜层和介质层上的凹进区、形成在硬掩膜层上以及凹进区的侧壁和底部上且包括至少一层钌或钴的阻挡层、形成在阻挡层上并填满凹进区的金属层;去除形成在非凹进区域上的金属层和凹进区内的部分金属,并在凹进区内留下一定量的金属;采用热流蚀刻方法去除形成在非凹进区域上且包括钌或钴层的阻挡层和硬掩膜层。
Description
技术领域
本发明涉及集成电路制造工艺,尤其涉及一种阻挡层的去除方法和半导体结构的形成方法。
背景技术
在半导体结构中,形成电路的材料通常是铝。但是随着集成电路特征尺寸越来越小,铝由于其高电阻,不再适合用在半导体结构中形成电路。铜由于其具有良好的导电性而代替铝被用到集成电路中。然而,铜很容易扩散到SiO2,从而严重影响到集成电路的性能。因此,为了解决这个问题,需要使用阻挡层来阻止铜扩散到SiO2中。
目前,阻挡层的材料通常采用钽、氮化钽、钛或氮化钛,且形成在半导体结构的非凹进区域上的阻挡层主要靠化学机械抛光(CMP)去除。对于20nm或低于20nm节点工艺,阻挡层的厚度必须足够薄。对于钽、氮化钽、钛或氮化钛阻挡层,如果钽、氮化钽、钛或氮化钛阻挡层的厚度太薄,就会降低阻挡层阻止铜扩散到SiO2中的能力。因此,钽、氮化钽、钛或氮化钛阻挡层无法满足20nm或低于20nm节点工艺的要求。
因此,需要寻找一种新的材料用在20nm或低于20nm节点工艺中形成阻挡层。事实证明,钴或钌可以用来形成阻挡层。钴或钌阻止铜扩散到SiO2中的能力要远强于钽、氮化钽、钛和氮化钛。但是,当使用钴作为半导体结构中的阻挡层时,在化学机械抛光阻挡层的过程中,钴阻挡层接触到研磨液时,凹进区(例如槽、孔)侧壁上的钴阻挡层可能会被化学腐蚀。一旦铜和钴阻挡层之间形成原电池,凹进区的顶部会存在电化学腐蚀的问题。另外,相比较而言,钌的硬度更高,当对钌阻挡层进行化学机械抛光时,很容易产生划痕。
综上,由于新材料的特性,阻挡层很难通过CMP去除,由此导致新材料产业化遭遇瓶颈。
发明内容
本发明提出一种阻挡层的去除方法,该阻挡层包括至少一层钌或钴,该阻挡层的去除方法包括:采用热流蚀刻方法去除形成在半导体结构的非凹进区域上包括钌或钴层的阻挡层。
本发明还提出一种半导体结构的形成方法,包括:提供一半导体结构,该半导体结构包括介质层、形成在介质层上的硬掩膜层、形成在硬掩膜层和介质层上的凹进区、形成在硬掩膜层上以及凹进区的侧壁和底部上且包括至少一层钌或钴的阻挡层、形成在阻挡层上并填满凹进区的金属层;去除形成在非凹进区域上的金属层和凹进区内的部分金属,并在凹进区内留下一定量的金属;采用热流蚀刻方法去除形成在非凹进区域上且包括钌或钴层的阻挡层和硬掩膜层。
在本发明中,采用热流蚀刻方法去除包括钌或钴层的阻挡层,克服了化学机械抛光钌或钴阻挡层时产生的弊端。除此以外,在半导体结构形成过程中,利用热流蚀刻去除阻挡层和硬掩膜层时不会产生机械力。而且,可以采用电抛光方法去除非凹进区域上的金属层,且不会产生机械力。由于在半导体结构形成过程中,没有机械力作用于介质层,因此,低k或超低k介质材料可以用在半导体结构中。
附图说明
图1-1至图1-3揭示了根据本发明的一示范性实施例的半导体结构形成过程的剖视图;
图2揭示了根据本发明的一示范性实施例的半导体结构形成方法的流程图;
图3-1至图3-4揭示了根据本发明的另一示范性实施例的半导体结构形成过程的剖视图;
图4揭示了根据本发明的另一示范性实施例的半导体结构形成方法的流程图;
图5-1至图5-4揭示了根据本发明的又一示范性实施例的半导体结构形成过程的剖视图;
图6揭示了根据本发明的又一示范性实施例的半导体结构形成方法的流程图。
具体实施方式
本发明提出一种阻挡层的去除方法,该阻挡层包括至少一层钌或钴,该阻挡层的去除方法包括:采用热流蚀刻方法去除形成在半导体结构的非凹进区域上且包括钌或钴层的阻挡层。下述实施例将阐述本发明的阻挡层的去除方法和半导体结构的形成方法。
参考图1-1至图1-3,揭示了根据本发明的一示范性实施例的半导体结构形成过程。半导体结构包括衬底101,例如晶圆。衬底101可能已经包含集成电路器件和必要的连接结构,这些没有在图中显示。在某些应用中,衬底101上有绝缘层102,绝缘层102可以是SiCN。介质层形成在绝缘层102上,如果衬底上没有绝缘层,那么介质层直接形成在衬底上。介质层可能包括的材料有SiO2、SiOC、SiOF、SiLK、BD、BDII、BDIII等。优选的,介质层选择低k介质材料来降低半导体器件内的半导体结构间的电容。根据不同的结构需求,介质层可以有两层或两层以上。如图所示的实施例中,介质层包括两层,第一介质层103形成在绝缘层102上,第二介质层104形成在第一介质层103上。第一介质层103可以是低k介质层,第二介质层104可以是TEOS。硬掩膜层105沉积在第二介质层104上,硬掩膜层105的材料可能包括氮化钛、氮化钽、钨或氮化钨。使用现有方法在硬掩膜层105、第二介质层104、第一介质层103和绝缘层102上制作凹进区,如沟、槽等。图中示意的凹进区108作为示例。
在硬掩膜层105上以及凹进区108的侧壁和底部上沉积阻挡层106。阻挡层106的材料至少包括钌或钴以满足20nm或低于20nm节点工艺的需求。为了提高阻挡层106与硬掩膜层105、第二介质层104、第一介质层103、绝缘层102之间的粘合性,阻挡层106最好包括两层,即第一阻挡层和第二阻挡层。第一阻挡层形成在硬掩膜层105上以及凹进区108的侧壁和底部上,第一阻挡层的材料可以是钛、氮化钛、钽或氮化钽。第二阻挡层形成在第一阻挡层上,第二阻挡层的材料可以是钌或钴。通常,如果第二阻挡层为钴,第一阻挡层最好选择氮化钛;如果第二阻挡层是钌,第一阻挡层最好是氮化钽。
金属层107形成在阻挡层106上并填满凹进区108。在某些应用中,在沉积金属层107之前,先在阻挡层106上沉积金属种子层。金属种子层可以包括和金属层107相同的材料以便于金属层107沉积、粘合在阻挡层106上。如图1-1,金属层107填满凹进区108并覆盖非凹进区域。金属层107优选为铜层。
参考图1-2,去除非凹进区域上的金属层107和凹进区内的部分金属,并在凹进区内保留一定量的金属。在本实施例中,凹进区108内的金属层表面与第二介质层104的上表面齐平。采用CMP方法、电抛光方法或者CMP与电抛光相结合的方法去除非凹进区域上的金属层107和凹进区内的部分金属。优选的,采用CMP方法去除大部分的金属层107,保留500-1000埃连续的金属层107覆盖在半导体结构上,然后采用电抛光方法去除非凹进区域上剩余的金属层107和凹进区内的部分金属。在CMP工艺过程中,芯片内的台阶高度差将减到最小。在专利申请号为PCT/CN2012/075990中揭示了电抛光的方法及装置,其内容在这里引入作为参考。
参考图1-3,采用热流蚀刻方法去除非凹进区域上的阻挡层106和硬掩膜层105。热流蚀刻也可以被称之为热气相化学刻蚀。热流蚀刻所使用的化学气体从以下气体中择一或是包含以下至少一种气体的混合气体:XeF2、XeF4、XeF6。以XeF2为例,XeF2和钌或钴的化学反应式为:
Ru+3XeF2→RuF6(挥发)+3Xe(气体)
Co+2XeF2→CoF4(挥发)+2Xe(气体)
热流蚀刻含钌的阻挡层106的温度为0-400℃,100-350℃较佳。热流蚀刻含钌的阻挡层106的压力为10毫托-20托。XeF2的流速为0-50sccm,且流速可以通过质量流量控制器来控制。在这些条件下,钌的蚀刻速率与钽、氮化钽、钛或氮化钛的蚀刻速率几乎相同。在110℃下,流速为9sccm时,钌的蚀刻速率大约为250埃/min。热流蚀刻含钴的阻挡层106的温度为120-600℃,200-400℃较佳。如图1-3,当阻挡层106和硬掩膜层105去除后,金属线被隔开。
在采用热流蚀刻去除阻挡层106之前,衬底101的表面需要使用含HF溶液处理或使用含HF蒸汽气相处理。由于电抛光去除金属过程中,阻挡层106的表面会形成氧化膜,且氧化膜会降低下方阻挡层的蚀刻效率。因此,在采用热流蚀刻去除阻挡层106之前,最好对衬底101的表面进行处理以去除衬底101表面的氧化膜。
相应地,如图2所示,根据本发明的一示范性实施例的半导体结构的形成方法,包括以下步骤:
步骤201:提供一半导体结构,该半导体结构包括介质层、形成在介质层上的硬掩膜层、形成在硬掩膜层和介质层上的凹进区、形成在硬掩膜层上以及凹进区的侧壁和底部上且包括至少一层钌或钴的阻挡层、形成在阻挡层上并填满凹进区的金属层;
步骤203:去除非凹进区域上的金属层和凹进区内的部分金属,并在凹进区内留下一定量的金属;
步骤205:采用热流蚀刻方法去除非凹进区域上且包括钌或钴层的阻挡层和硬掩膜层。
在本实施例中,凹进区内的金属表面与介质层的上表面平齐。
参考图3-1至图3-4,揭示了根据本发明的另一示范性实施例的半导体结构形成过程。半导体结构包括衬底301,例如晶圆。衬底301可能已经包含集成电路器件和必要的连接结构,这些在图中未显示。在某些应用中,衬底301上有绝缘层302,绝缘层302可以是SiCN。介质层形成在绝缘层302上,如果衬底上没有绝缘层,那么介质层直接形成在衬底上。介质层可能包括的材料有SiO2、SiOC、SiOF、SiLK、BD、BDII、BDIII等。优选的,介质层选择低k介质材料以减小半导体器件中的半导体结构间的电容。根据不同的结构需求,介质层可以有两层或两层以上。在如图所示的实施例中,介质层包括两层,第一介质层303形成在绝缘层302上,第二介质层304形成在第一介质层303上。第一介质层303可以是低k介质层,第二介质层304可以是TEOS。硬掩膜层305沉积在第二介质层304上,硬掩膜层305的材料包括氮化钛、氮化钽、钨或氮化钨。使用现有技术在硬掩膜层305、第二介质层304、第一介质层303和绝缘层302上制作凹进区,如沟、槽等。图中所示的凹进区308作为示例。
阻挡层306沉积在硬掩膜层305上以及凹进区308的侧壁和底部上。为了满足20nm或低于20nm节点工艺的需求,阻挡层306的材料至少包括钌。为了提高阻挡层306与硬掩膜层305、第二介质层304、第一介质层303、绝缘层302之间的粘合性,阻挡层306最好包括两层,即第一阻挡层和第二阻挡层。第一阻挡层形成在硬掩膜层305上以及凹进区308的侧壁和底部上,第一阻挡层的材料可以是钛、氮化钛、钽或氮化钽。第二阻挡层形成在第一阻挡层上,第二阻挡层的材料可以是钌。通常,如果第二阻挡层是钌,第一阻挡层最好是氮化钽。
金属层307形成在阻挡层306上并填满凹进区308。在某些应用中,在沉积金属层307之前,先在阻挡层306上沉积金属种子层。金属种子层可以包括和金属层307相同的材料以便于金属层307沉积、粘合在阻挡层306上。如图3-1,金属层307填满凹进区308并覆盖非凹进区域。金属层307优选为铜层。
参考图3-2,去除非凹进区域上的金属层307和凹进区内的部分金属,并在凹进区内保留一定量的金属。在本实施例中,凹进区308内的金属层表面低于第二介质层304的上表面。采用CMP方法、电抛光方法或者CMP与电抛光相结合的方法去除非凹进区域上的金属层307和凹进区内的部分金属。优选的,采用CMP方法去除大部分的金属层307,保留500-1000埃连续的金属层307覆盖在半导体结构上,然后采用电抛光方法去除非凹进区域上剩余的金属层307和凹进区内的部分金属。在CMP工艺过程中,芯片内的台阶高度差将减到最小。在专利申请号为PCT/CN2012/075990中揭示了电抛光的方法及装置,其内容在这里引入作为参考。
参考图3-3,选择性的在凹进区内的金属表面上镀一层覆盖层309。此处的“选择性的镀”意思是仅在凹进区308内的金属表面镀一层覆盖层309,而非凹进区域上的阻挡层306的表面没有被镀上覆盖层309。凹进区308内的覆盖层309的上表面与第二介质层304的上表面齐平。覆盖层309的材料一般选用钴,但其他材料也可以使用。
参考图3-4,采用热流蚀刻方法去除非凹进区域上的阻挡层306和硬掩膜层305。热流蚀刻所使用的化学气体从以下气体中择一或是包含以下至少一种气体的混合气体:XeF2、XeF4、XeF6。以XeF2为例,热流蚀刻含钌的阻挡层306的温度为0-400℃,50-120℃较佳。热流蚀刻含钌的阻挡层306的压力为10毫托-20托。XeF2的流速为0-50sccm,且流速可以通过质量流量控制器来控制。在这些条件下,钌的蚀刻速率与钽、氮化钽、钛或氮化钛的蚀刻速率几乎相同。在110℃下,钌的蚀刻速率大约为250埃/min。当温度低于120℃时,XeF2和钴之间的反应可以被忽略。
在采用热流蚀刻去除阻挡层306之前,衬底301的表面需要使用含HF溶液处理或含HF蒸汽气相处理。由于电抛光去除金属过程中,阻挡层306的表面会形成氧化膜,且氧化膜会降低下方阻挡层的蚀刻效率。因此,在采用热流蚀刻去除阻挡层306之前,最好对衬底301的表面进行处理以去除衬底301表面的氧化膜。
相应地,如图4所示,根据本发明的另一示范性实施例的半导体结构的形成方法,包括以下步骤:
步骤401:提供一半导体结构,该半导体结构包括介质层、形成在介质层上的硬掩膜层、形成在硬掩膜层和介质层上的凹进区、形成在硬掩膜层上以及凹进区的侧壁和底部上且包括至少一层钌的阻挡层、形成在阻挡层上并填满凹进区的金属层;
步骤403:去除非凹进区域上的金属层和凹进区内的部分金属,并在凹进区内保留一定量的金属,凹进区内的金属表面低于介质层的上表面;
步骤404:选择性的在凹进区内的金属表面上镀一层覆盖层,其中,凹进区内的覆盖层的上表面与介质层的上表面齐平;
步骤405:采用热流蚀刻方法去除非凹进区域上且包括钌层的阻挡层和硬掩膜层。
参考图5-1至图5-4,揭示了根据本发明的又一示范性实施例的半导体结构形成过程。半导体结构包括衬底501,例如晶圆。在某些应用中,衬底501上有绝缘层502,绝缘层502可以是SiCN。介质层形成在绝缘层502上。如果衬底上没有绝缘层,那么介质层直接形成在衬底上。介质层可能包括的材料有SiO2、SiOC、SiOF、SiLK、BD、BDII、BDIII等。优选的,介质层选择低k介质材料以减小半导体器件中的半导体结构间的电容。根据不同的结构需求,介质层可以有两层或两层以上。在如图所示的实施例中,介质层包括两层,第一介质层503形成在绝缘层502上,第二介质层504形成在第一介质层503上。第一介质层503可以是低k介质层,第二介质层504可以是TEOS。硬掩膜层505沉积在第二介质层504上,硬掩膜层505的材料包括氮化钛、氮化钽、钨或氮化钨。使用现有技术在硬掩膜层505、第二介质层504、第一介质层503和绝缘层502上制作凹进区,如沟、槽等。图中所示的凹进区508作为示例。
阻挡层506沉积在硬掩膜层505上以及凹进区508的侧壁和底部上。为了满足20nm或低于20nm节点工艺的需求,阻挡层506的材料至少包括钌或钴。为了提高阻挡层506与硬掩膜层505、第二介质层504、第一介质层503、绝缘层502之间的粘合性,阻挡层506最好包括两层,即第一阻挡层和第二阻挡层。第一阻挡层形成在硬掩膜层505上以及凹进区508的侧壁和底部上,第一阻挡层的材料可以是钛、氮化钛、钽或氮化钽。第二阻挡层形成在第一阻挡层上,第二阻挡层的材料可以是钌或钴。通常,如果第二阻挡层为钴,第一阻挡层最好选择氮化钛;如果第二阻挡层是钌,第一阻挡层最好是氮化钽。
金属层507形成在阻挡层506上并填满凹进区508。在某些应用中,在沉积金属层507之前,先在阻挡层506上沉积金属种子层。金属种子层可以包括和金属层507相同的材料以便于金属层507沉积、粘合在阻挡层506上。如图5-1,金属层507填满凹进区508并覆盖非凹进区域。金属层507优选为铜层。
参考图5-2,去除非凹进区域上的金属层507和凹进区内的部分金属,并在凹进区内保留一定量的金属。在本实施例中,凹进区508内的金属层表面低于第二介质层504的上表面。采用CMP方法、电抛光方法或者CMP与电抛光相结合的方法去除非凹进区域上的金属层507和凹进区内的部分金属。优选的,采用CMP方法去除大部分的金属层507,保留500-1000埃连续的金属层507覆盖在半导体结构上,然后采用电抛光方法去除非凹进区域上剩余的金属层507和凹进区内的部分金属。在CMP工艺过程中,芯片内的台阶高度差将减到最小。在专利申请号为PCT/CN2012/075990中揭示了电抛光的方法及装置,其内容在这里引入作为参考。
采用热流蚀刻方法去除非凹进区域上的阻挡层506和硬掩膜层505。在去除阻挡层506和硬掩膜层505的过程中,凹进区508侧壁上的部分阻挡层506可能被蚀刻。如图5-3A和图5-3B示意了采用热流蚀刻方法去除非凹进区域上的阻挡层506和硬掩膜层505后的两种极端情形,实际的工艺结果通常介于这两种极端情形之间。
在采用热流蚀刻方法去除阻挡层506之前,需要使用含HF溶液处理衬底501的表面或者使用含HF蒸汽气相处理衬底501的表面。由于电抛光去除金属过程中,阻挡层506的表面会形成氧化膜,且氧化膜会降低下方阻挡层的蚀刻效率。因此,在采用热流蚀刻去除阻挡层506之前,最好对衬底501的表面进行处理以去除衬底501表面的氧化膜。
参考图5-4,选择性的在凹进区508内的金属表面上镀一层覆盖层509。凹进区508内的覆盖层509的上表面与第二介质层504的上表面齐平。覆盖层509的材料通常选用钴,但也可以使用其他材料。由于在凹进区508内的金属表面镀有一层覆盖层509,所以阻挡层506能够被过蚀刻以确保非凹进区域上的阻挡层506无残留。
相应地,如图6所示,根据本发明的又一示范性实施例的半导体结构的形成方法,包括以下步骤:
步骤601:提供一半导体结构,该半导体结构包括介质层、形成在介质层上的硬掩膜层、形成在硬掩膜层和介质层上的凹进区、形成在硬掩膜层上以及凹进区的侧壁和底部上且包括至少一层钌或钴的阻挡层、形成在阻挡层上并填满凹进区的金属层;
步骤603:去除非凹进区域上的金属层和凹进区内的部分金属,并在凹进区内保留一定量的金属,凹进区内的金属表面低于介质层的上表面;
步骤605:采用热流蚀刻方法去除非凹进区域上且包括钌或钴层的阻挡层和硬掩膜层;
步骤606:选择性的在凹进区内的金属表面上镀一层覆盖层,其中,凹进区内的覆盖层的上表面与介质层的上表面齐平。
本发明通过上述实施方式及相关图式说明,己具体、详实的揭露了相关技术,使本领域的技术人员可以据以实施。而以上所述实施例只是用来说明本发明,而不是用来限制本发明的,本发明的权利范围,应由本发明的权利要求来界定。至于本文中所述元件数目的改变或等效元件的代替等仍都应属于本发明的权利范围。
Claims (21)
1.一种阻挡层的去除方法,其特征在于,该去除方法用于20nm或以下的节点工艺,该阻挡层包括至少一层钌或钴,该阻挡层的去除方法包括:采用热流蚀刻方法去除形成在半导体结构的非凹进区域上包括钌或钴层的阻挡层,热流蚀刻所使用的化学气体从以下气体中择一或是包含以下至少一种气体的混合气体:XeF2、XeF4、XeF6。
2.如权利要求1所述的方法,其特征在于,热流蚀刻含钌阻挡层的温度为0-400℃。
3.如权利要求2所述的方法,其特征在于,热流蚀刻含钌阻挡层的温度为100-350℃。
4.如权利要求3所述的方法,其特征在于,热流蚀刻含钌阻挡层的温度为50-120℃。
5.如权利要求1所述的方法,其特征在于,热流蚀刻含钌阻挡层的压力为10毫托-20托。
6.如权利要求2所述的方法,其特征在于,化学气体的流速为0-50sccm。
7.如权利要求1所述的方法,其特征在于,热流蚀刻含钴阻挡层的温度为120-600℃。
8.如权利要求7所述的方法,其特征在于,热流蚀刻含钴阻挡层的温度为200-400℃。
9.如权利要求1所述的方法,其特征在于,该阻挡层还包括另一层材料为钛、氮化钛、钽或氮化钽的阻挡层。
10.一种半导体结构的形成方法,其特征在于,包括:
提供一用于20nm或以下的节点工艺的半导体结构,该半导体结构包括介质层、形成在介质层上的硬掩膜层、形成在硬掩膜层和介质层上的凹进区、形成在硬掩膜层上以及凹进区的侧壁和底部上且包括至少一层钌或钴的阻挡层、形成在阻挡层上并填满凹进区的金属层;
去除非凹进区域上的金属层和凹进区内的部分金属,并在凹进区内留下一定量的金属;
采用热流蚀刻方法去除非凹进区域上且包括钌或钴层的阻挡层和硬掩膜层,热流蚀刻所使用的化学气体从以下气体中择一或是包含以下至少一种气体的混合气体:XeF2、XeF4、XeF6。
11.如权利要求10所述的方法,其特征在于,凹进区内的金属表面与介质层的上表面齐平。
12.如权利要求10所述的方法,其特征在于,凹进区内的金属表面低于介质层的上表面。
13.如权利要求12所述的方法,其特征在于,还包括选择性的在凹进区内的金属表面镀一层覆盖层。
14.如权利要求13所述的方法,其特征在于,凹进区内的覆盖层的上表面与介质层的上表面齐平。
15.如权利要求13所述的方法,其特征在于,覆盖层的材料为钴。
16.如权利要求13所述的方法,其特征在于,所述选择性的在凹进区内的金属表面镀一层覆盖层的步骤在所述采用热流蚀刻方法去除非凹进区域上且包括钌或钴层的阻挡层和硬掩膜层的步骤之前执行。
17.如权利要求13所述的方法,其特征在于,所述选择性的在凹进区内的金属表面镀一层覆盖层的步骤在所述采用热流蚀刻方法去除非凹进区域上且包括钌或钴层的阻挡层和硬掩膜层的步骤之后执行。
18.如权利要求10所述的方法,其特征在于,所述阻挡层还包括另一层材料为钛、氮化钛、钽或氮化钽的阻挡层。
19.如权利要求10所述的方法,其特征在于,采用CMP方法或电抛光方法或CMP和电抛光相结合的方法去除非凹进区域上的金属层和凹进区内的部分金属。
20.如权利要求10所述的方法,其特征在于,金属层为铜层。
21.如权利要求10所述的方法,其特征在于,在去除阻挡层之前,使用含HF溶液处理衬底表面或者使用含HF蒸汽气相处理衬底表面。
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