JP4988091B2 - ダマシンコンタクトおよびゲートプロセスで作製された自己整列ソースおよびドレイン延在部 - Google Patents

ダマシンコンタクトおよびゲートプロセスで作製された自己整列ソースおよびドレイン延在部 Download PDF

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Publication number
JP4988091B2
JP4988091B2 JP2000616072A JP2000616072A JP4988091B2 JP 4988091 B2 JP4988091 B2 JP 4988091B2 JP 2000616072 A JP2000616072 A JP 2000616072A JP 2000616072 A JP2000616072 A JP 2000616072A JP 4988091 B2 JP4988091 B2 JP 4988091B2
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region
substrate
conductive structure
gate
forming
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JP2002543623A (ja
JP2002543623A5 (enExample
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シアン，チ
ブイノスキィ，マシュー・エス
リン，ミン−レン
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0181—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2000616072A 1999-05-03 2000-02-29 ダマシンコンタクトおよびゲートプロセスで作製された自己整列ソースおよびドレイン延在部 Expired - Lifetime JP4988091B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/303,693 1999-05-03
US09/303,693 US6271132B1 (en) 1999-05-03 1999-05-03 Self-aligned source and drain extensions fabricated in a damascene contact and gate process
PCT/US2000/005157 WO2000067322A2 (en) 1999-05-03 2000-02-29 Self-aligned source and drain extensions fabricated in a damascene contact and gate process

Publications (3)

Publication Number Publication Date
JP2002543623A JP2002543623A (ja) 2002-12-17
JP2002543623A5 JP2002543623A5 (enExample) 2007-03-15
JP4988091B2 true JP4988091B2 (ja) 2012-08-01

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JP2000616072A Expired - Lifetime JP4988091B2 (ja) 1999-05-03 2000-02-29 ダマシンコンタクトおよびゲートプロセスで作製された自己整列ソースおよびドレイン延在部

Country Status (6)

Country Link
US (1) US6271132B1 (enExample)
EP (1) EP1186017B1 (enExample)
JP (1) JP4988091B2 (enExample)
KR (1) KR100764918B1 (enExample)
DE (1) DE60042739D1 (enExample)
WO (1) WO2000067322A2 (enExample)

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WO2002047146A2 (en) * 2000-12-07 2002-06-13 Advanced Micro Devices, Inc. DAMASCENE NiSi METAL GATE HIGH-K TRANSISTOR
US6541821B1 (en) 2000-12-07 2003-04-01 Advanced Micro Devices, Inc. SOI device with source/drain extensions and adjacent shallow pockets
US6727149B1 (en) * 2000-12-07 2004-04-27 Advanced Micro Devices, Inc. Method of making a hybrid SOI device that suppresses floating body effects
US6406945B1 (en) * 2001-01-26 2002-06-18 Chartered Semiconductor Manufacturing Ltd. Method for forming a transistor gate dielectric with high-K and low-K regions
US6518107B2 (en) * 2001-02-16 2003-02-11 Advanced Micro Devices, Inc. Non-arsenic N-type dopant implantation for improved source/drain interfaces with nickel silicides
US6468921B1 (en) * 2001-09-26 2002-10-22 Winbond Electronics Corp. Thin-film forming method
US6455383B1 (en) * 2001-10-25 2002-09-24 Silicon-Based Technology Corp. Methods of fabricating scaled MOSFETs
KR20030058584A (ko) * 2001-12-31 2003-07-07 주식회사 하이닉스반도체 반도체소자의 콘택 형성방법
US6518133B1 (en) 2002-04-24 2003-02-11 Chartered Semiconductor Manufacturing Ltd Method for fabricating a small dimensional gate with elevated source/drain structures
US6727151B2 (en) 2002-08-07 2004-04-27 Chartered Semiconductor Manufacturing Ltd. Method to fabricate elevated source/drain structures in MOS transistors
US6780691B2 (en) 2002-08-16 2004-08-24 Chartered Semiconductor Manufacturing Ltd. Method to fabricate elevated source/drain transistor with large area for silicidation
JP3840198B2 (ja) * 2003-04-28 2006-11-01 株式会社東芝 半導体装置およびその製造方法
JP4377721B2 (ja) * 2004-03-11 2009-12-02 株式会社東芝 半導体装置の製造方法
US6884715B1 (en) 2004-06-04 2005-04-26 International Business Machines Corporation Method for forming a self-aligned contact with a silicide or damascene conductor and the structure formed thereby
KR100562650B1 (ko) * 2004-06-25 2006-03-20 주식회사 하이닉스반도체 반도체 소자 제조 방법
US7126199B2 (en) 2004-09-27 2006-10-24 Intel Corporation Multilayer metal gate electrode
US7138308B2 (en) * 2004-12-14 2006-11-21 International Business Machines Corporation Replacement gate with TERA cap
US7358196B2 (en) * 2005-02-07 2008-04-15 Applied Materials, Inc. Wet chemical treatment to form a thin oxide for high k gate dielectrics
EP1914800A1 (en) * 2006-10-20 2008-04-23 Interuniversitair Microelektronica Centrum Method of manufacturing a semiconductor device with multiple dielectrics
JP4950710B2 (ja) * 2007-03-19 2012-06-13 株式会社東芝 半導体装置及び半導体装置の製造方法
JP5462161B2 (ja) * 2007-07-20 2014-04-02 アイメック Ｉｉｉ−ｖ族ｍｅｓｆｅｔでのダマシンコンタクト製造方法
US20090206416A1 (en) * 2008-02-19 2009-08-20 International Business Machines Corporation Dual metal gate structures and methods
US7955909B2 (en) * 2008-03-28 2011-06-07 International Business Machines Corporation Strained ultra-thin SOI transistor formed by replacement gate
US8012843B2 (en) * 2009-08-07 2011-09-06 Varian Semiconductor Equipment Associates, Inc. Optimized halo or pocket cold implants
CN102237399B (zh) * 2010-04-22 2015-01-07 联华电子股份有限公司 具有金属栅极的半导体元件及其制作方法
US10038063B2 (en) 2014-06-10 2018-07-31 International Business Machines Corporation Tunable breakdown voltage RF FET devices

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JPH07202187A (ja) * 1993-11-23 1995-08-04 Lg Semicon Co Ltd Ｍｏｓトランジスタの製造方法
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Also Published As

Publication number Publication date
JP2002543623A (ja) 2002-12-17
KR100764918B1 (ko) 2007-10-09
KR20020011133A (ko) 2002-02-07
US6271132B1 (en) 2001-08-07
DE60042739D1 (de) 2009-09-24
EP1186017B1 (en) 2009-08-12
WO2000067322A2 (en) 2000-11-09
WO2000067322A3 (en) 2001-03-29
EP1186017A2 (en) 2002-03-13

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