KR100764918B1 - 상감 세공 컨택 및 게이트 공정으로 제조된 자기-정렬 소스 및 드레인 확장부 - Google Patents

상감 세공 컨택 및 게이트 공정으로 제조된 자기-정렬 소스 및 드레인 확장부 Download PDF

Info

Publication number
KR100764918B1
KR100764918B1 KR1020017014059A KR20017014059A KR100764918B1 KR 100764918 B1 KR100764918 B1 KR 100764918B1 KR 1020017014059 A KR1020017014059 A KR 1020017014059A KR 20017014059 A KR20017014059 A KR 20017014059A KR 100764918 B1 KR100764918 B1 KR 100764918B1
Authority
KR
South Korea
Prior art keywords
gate
region
opening
conductive
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
KR1020017014059A
Other languages
English (en)
Korean (ko)
Other versions
KR20020011133A (ko
Inventor
시앙퀴
바이노스키매튜에스.
린밍-렌
Original Assignee
어드밴스드 마이크로 디바이시즈, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Publication of KR20020011133A publication Critical patent/KR20020011133A/ko
Application granted granted Critical
Publication of KR100764918B1 publication Critical patent/KR100764918B1/ko
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0181—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
KR1020017014059A 1999-05-03 2000-02-29 상감 세공 컨택 및 게이트 공정으로 제조된 자기-정렬 소스 및 드레인 확장부 Expired - Lifetime KR100764918B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/303,693 US6271132B1 (en) 1999-05-03 1999-05-03 Self-aligned source and drain extensions fabricated in a damascene contact and gate process
US09/303,693 1999-05-03

Publications (2)

Publication Number Publication Date
KR20020011133A KR20020011133A (ko) 2002-02-07
KR100764918B1 true KR100764918B1 (ko) 2007-10-09

Family

ID=23173261

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020017014059A Expired - Lifetime KR100764918B1 (ko) 1999-05-03 2000-02-29 상감 세공 컨택 및 게이트 공정으로 제조된 자기-정렬 소스 및 드레인 확장부

Country Status (6)

Country Link
US (1) US6271132B1 (enExample)
EP (1) EP1186017B1 (enExample)
JP (1) JP4988091B2 (enExample)
KR (1) KR100764918B1 (enExample)
DE (1) DE60042739D1 (enExample)
WO (1) WO2000067322A2 (enExample)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6306714B1 (en) * 2000-11-16 2001-10-23 Chartered Semiconductor Manufacturing Inc. Method to form an elevated S/D CMOS device by contacting S/D through the contact of oxide
US6303449B1 (en) * 2000-11-16 2001-10-16 Chartered Semiconductor Manufacturing Inc. Method to form self-aligned elevated source/drain by selective removal of gate dielectric in the source/drain region followed by poly deposition and CMP
EP1334522A1 (en) * 2000-11-16 2003-08-13 Advanced Micro Devices, Inc. Semiconductor device with reduced line-to-line capacitance and cross talk noise
WO2002047146A2 (en) * 2000-12-07 2002-06-13 Advanced Micro Devices, Inc. DAMASCENE NiSi METAL GATE HIGH-K TRANSISTOR
US6541821B1 (en) 2000-12-07 2003-04-01 Advanced Micro Devices, Inc. SOI device with source/drain extensions and adjacent shallow pockets
US6727149B1 (en) * 2000-12-07 2004-04-27 Advanced Micro Devices, Inc. Method of making a hybrid SOI device that suppresses floating body effects
US6406945B1 (en) * 2001-01-26 2002-06-18 Chartered Semiconductor Manufacturing Ltd. Method for forming a transistor gate dielectric with high-K and low-K regions
US6518107B2 (en) * 2001-02-16 2003-02-11 Advanced Micro Devices, Inc. Non-arsenic N-type dopant implantation for improved source/drain interfaces with nickel silicides
US6468921B1 (en) * 2001-09-26 2002-10-22 Winbond Electronics Corp. Thin-film forming method
US6455383B1 (en) * 2001-10-25 2002-09-24 Silicon-Based Technology Corp. Methods of fabricating scaled MOSFETs
KR20030058584A (ko) * 2001-12-31 2003-07-07 주식회사 하이닉스반도체 반도체소자의 콘택 형성방법
US6518133B1 (en) 2002-04-24 2003-02-11 Chartered Semiconductor Manufacturing Ltd Method for fabricating a small dimensional gate with elevated source/drain structures
US6727151B2 (en) 2002-08-07 2004-04-27 Chartered Semiconductor Manufacturing Ltd. Method to fabricate elevated source/drain structures in MOS transistors
US6780691B2 (en) 2002-08-16 2004-08-24 Chartered Semiconductor Manufacturing Ltd. Method to fabricate elevated source/drain transistor with large area for silicidation
JP3840198B2 (ja) * 2003-04-28 2006-11-01 株式会社東芝 半導体装置およびその製造方法
JP4377721B2 (ja) * 2004-03-11 2009-12-02 株式会社東芝 半導体装置の製造方法
US6884715B1 (en) 2004-06-04 2005-04-26 International Business Machines Corporation Method for forming a self-aligned contact with a silicide or damascene conductor and the structure formed thereby
KR100562650B1 (ko) * 2004-06-25 2006-03-20 주식회사 하이닉스반도체 반도체 소자 제조 방법
US7126199B2 (en) * 2004-09-27 2006-10-24 Intel Corporation Multilayer metal gate electrode
US7138308B2 (en) * 2004-12-14 2006-11-21 International Business Machines Corporation Replacement gate with TERA cap
US7358196B2 (en) * 2005-02-07 2008-04-15 Applied Materials, Inc. Wet chemical treatment to form a thin oxide for high k gate dielectrics
EP1914800A1 (en) * 2006-10-20 2008-04-23 Interuniversitair Microelektronica Centrum Method of manufacturing a semiconductor device with multiple dielectrics
JP4950710B2 (ja) * 2007-03-19 2012-06-13 株式会社東芝 半導体装置及び半導体装置の製造方法
WO2009012536A1 (en) * 2007-07-20 2009-01-29 Interuniversitair Microelektronica Centrum Damascene contacts on iii-v cmos devices
US20090206416A1 (en) * 2008-02-19 2009-08-20 International Business Machines Corporation Dual metal gate structures and methods
US7955909B2 (en) * 2008-03-28 2011-06-07 International Business Machines Corporation Strained ultra-thin SOI transistor formed by replacement gate
US8012843B2 (en) * 2009-08-07 2011-09-06 Varian Semiconductor Equipment Associates, Inc. Optimized halo or pocket cold implants
CN102237399B (zh) * 2010-04-22 2015-01-07 联华电子股份有限公司 具有金属栅极的半导体元件及其制作方法
US10038063B2 (en) 2014-06-10 2018-07-31 International Business Machines Corporation Tunable breakdown voltage RF FET devices

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0167301B1 (ko) * 1995-12-29 1999-02-01 문정환 모스전계효과트랜지스터 제조방법
KR0186071B1 (ko) * 1995-12-29 1999-04-15 문정환 모스전계효과트랜지스터 제조방법

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5386583A (en) * 1977-01-10 1978-07-31 Matsushita Electric Ind Co Ltd Mos type semiconductor device and its production
CA1216962A (en) 1985-06-28 1987-01-20 Hussein M. Naguib Mos device processing
JPS62199068A (ja) 1986-02-27 1987-09-02 Toshiba Corp 半導体装置及びその製造方法
US4745082A (en) 1986-06-12 1988-05-17 Ford Microelectronics, Inc. Method of making a self-aligned MESFET using a substitutional gate with side walls
JPS6336564A (ja) * 1986-07-31 1988-02-17 Nec Corp 半導体装置の製造方法
US4792531A (en) * 1987-10-05 1988-12-20 Menlo Industries, Inc. Self-aligned gate process
JP2936624B2 (ja) 1990-02-26 1999-08-23 日本電気株式会社 半導体装置の製造方法
JP2778600B2 (ja) 1990-03-20 1998-07-23 富士通株式会社 半導体装置の製造方法
JP3029653B2 (ja) 1990-09-14 2000-04-04 株式会社東芝 半導体装置の製造方法
SG63578A1 (en) 1990-11-16 1999-03-30 Seiko Epson Corp Thin film semiconductor device process for fabricating the same and silicon film
KR100274555B1 (ko) 1991-06-26 2000-12-15 윌리엄 비. 켐플러 절연 게이트 전계 효과 트랜지스터 구조물 및 이의 제조 방법
JP2716303B2 (ja) 1991-12-06 1998-02-18 シャープ株式会社 Ｍｏｓ形電界効果トランジスタの製造方法
US5391510A (en) 1992-02-28 1995-02-21 International Business Machines Corporation Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps
US5393685A (en) 1992-08-10 1995-02-28 Taiwan Semiconductor Manufacturing Company Peeling free metal silicide films using rapid thermal anneal
US5374575A (en) 1993-11-23 1994-12-20 Goldstar Electron Co., Ltd. Method for fabricating MOS transistor
KR0135163B1 (ko) 1993-12-16 1998-04-22 문정환 얕은 접합의 소오스/드레인영역과 실리사이드를 갖는 모스트랜지스터의 제조방법
JP2586342B2 (ja) * 1994-08-27 1997-02-26 日本電気株式会社 半導体装置の製造方法
US5429956A (en) 1994-09-30 1995-07-04 United Microelectronics Corporation Method for fabricating a field effect transistor with a self-aligned anti-punchthrough implant channel
US5593907A (en) 1995-03-08 1997-01-14 Advanced Micro Devices Large tilt angle boron implant methodology for reducing subthreshold current in NMOS integrated circuit devices
JPH08264562A (ja) 1995-03-24 1996-10-11 Mitsubishi Electric Corp 半導体装置，及びその製造方法
JPH09153610A (ja) * 1995-12-01 1997-06-10 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP4139907B2 (ja) 1996-05-08 2008-08-27 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド イオン注入方法、集積回路製造プロセス、および集積回路ｍｏｓ製造プロセス
US5858843A (en) 1996-09-27 1999-01-12 Intel Corporation Low temperature method of forming gate electrode and gate dielectric
US5834355A (en) * 1996-12-31 1998-11-10 Intel Corporation Method for implanting halo structures using removable spacer
JPH10200096A (ja) * 1997-01-06 1998-07-31 Sony Corp Ｍｏｓ型電界効果トランジスタ及びその製造方法
JP3495869B2 (ja) * 1997-01-07 2004-02-09 株式会社東芝 半導体装置の製造方法
US5793090A (en) 1997-01-10 1998-08-11 Advanced Micro Devices, Inc. Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance
US5960270A (en) * 1997-08-11 1999-09-28 Motorola, Inc. Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions
JP3125726B2 (ja) * 1997-08-26 2001-01-22 日本電気株式会社 半導体装置の製造方法
KR100248506B1 (ko) * 1997-08-30 2000-03-15 윤종용 트랜지스터의 특성 개선을 위한 반도체 장치 제조 방법
US5858848A (en) * 1997-10-24 1999-01-12 Advanced Micro Devices, Inc. Semiconductor fabrication employing self-aligned sidewall spacers laterally adjacent to a transistor gate
US5856225A (en) 1997-11-24 1999-01-05 Chartered Semiconductor Manufacturing Ltd Creation of a self-aligned, ion implanted channel region, after source and drain formation

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0167301B1 (ko) * 1995-12-29 1999-02-01 문정환 모스전계효과트랜지스터 제조방법
KR0186071B1 (ko) * 1995-12-29 1999-04-15 문정환 모스전계효과트랜지스터 제조방법

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
1001673010000
1001860710000

Also Published As

Publication number Publication date
WO2000067322A3 (en) 2001-03-29
WO2000067322A2 (en) 2000-11-09
KR20020011133A (ko) 2002-02-07
DE60042739D1 (de) 2009-09-24
JP4988091B2 (ja) 2012-08-01
EP1186017A2 (en) 2002-03-13
US6271132B1 (en) 2001-08-07
JP2002543623A (ja) 2002-12-17
EP1186017B1 (en) 2009-08-12

Similar Documents

Publication Publication Date Title
KR100764918B1 (ko) 상감 세공 컨택 및 게이트 공정으로 제조된 자기-정렬 소스 및 드레인 확장부
US6737308B2 (en) Semiconductor device having LDD-type source/drain regions and fabrication method thereof
US8735991B2 (en) High gate density devices and methods
US5777370A (en) Trench isolation of field effect transistors
US7955919B2 (en) Spacer-less transistor integration scheme for high-K gate dielectrics and small gate-to-gate spaces applicable to Si, SiGe and strained silicon schemes
KR101201489B1 (ko) Ｓｏｉ 디바이스 제조 방법
US7482243B2 (en) Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique
US6015727A (en) Damascene formation of borderless contact MOS transistors
US6291278B1 (en) Method of forming transistors with self aligned damascene gate contact
US7247569B2 (en) Ultra-thin Si MOSFET device structure and method of manufacture
KR20090096885A (ko) 국부적 매립 절연막을 구비하는 반도체 장치 및 그 제조방법
US20190051565A1 (en) Cmos devices and manufacturing method thereof
US5256585A (en) Process for fabricating a gate-drain overlapped semiconductor
US6677194B2 (en) Method of manufacturing a semiconductor integrated circuit device
EP0344292B1 (en) A process of fabricating self-aligned semiconductor devices
US6492249B2 (en) High-K gate dielectric process with process with self aligned damascene contact to damascene gate and a low-k inter level dielectric
KR20030047371A (ko) 반도체소자 및 그 형성 방법
KR100596772B1 (ko) 다마신 공정을 이용한 텅스텐 게이트 모스팻 소자의제조방법
KR19980018188A (ko) 비정질화된 폴리실리콘을 사용하는 서브미크론 마이크로일렉트로닉스 응용을 위한 자기 정렬 ＰＯＣｌ₃제조 방법
KR100453950B1 (ko) 모스형 트랜지스터의 게이트전극 형성방법
US6465314B1 (en) Semiconductor processing methods
KR20020027772A (ko) 듀얼 게이트형 모스 트랜지스터 제조방법
JP3714396B2 (ja) 半導体装置の製造方法
KR100618807B1 (ko) 셀프 얼라인 컨택이 가능한 이중 게이트 폴리 구조의반도체 소자 제조방법과 그 게이트 구조체
KR20050008884A (ko) 엔모스 트랜지스터의 제조 방법

Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20011103

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
A201 Request for examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20041214

Comment text: Request for Examination of Application

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20060626

Patent event code: PE09021S01D

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20070209

Patent event code: PE09021S01D

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 20070808

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 20071001

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 20071002

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
G170 Re-publication after modification of scope of protection [patent]
PG1701 Publication of correction
PR1001 Payment of annual fee

Payment date: 20100930

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 20110929

Start annual number: 5

End annual number: 5

FPAY Annual fee payment

Payment date: 20120927

Year of fee payment: 6

PR1001 Payment of annual fee

Payment date: 20120927

Start annual number: 6

End annual number: 6

FPAY Annual fee payment

Payment date: 20130926

Year of fee payment: 7

PR1001 Payment of annual fee

Payment date: 20130926

Start annual number: 7

End annual number: 7

FPAY Annual fee payment

Payment date: 20140923

Year of fee payment: 8

PR1001 Payment of annual fee

Payment date: 20140923

Start annual number: 8

End annual number: 8

FPAY Annual fee payment

Payment date: 20150918

Year of fee payment: 9

PR1001 Payment of annual fee

Payment date: 20150918

Start annual number: 9

End annual number: 9

FPAY Annual fee payment

Payment date: 20160921

Year of fee payment: 10

PR1001 Payment of annual fee

Payment date: 20160921

Start annual number: 10

End annual number: 10

FPAY Annual fee payment

Payment date: 20170919

Year of fee payment: 11

PR1001 Payment of annual fee

Payment date: 20170919

Start annual number: 11

End annual number: 11

FPAY Annual fee payment

Payment date: 20180918

Year of fee payment: 12

PR1001 Payment of annual fee

Payment date: 20180918

Start annual number: 12

End annual number: 12

PC1801 Expiration of term

Termination date: 20200831

Termination category: Expiration of duration