JP4965462B2 - プレーナ型ダブルゲートトランジスタを形成する方法 - Google Patents

プレーナ型ダブルゲートトランジスタを形成する方法 Download PDF

Info

Publication number
JP4965462B2
JP4965462B2 JP2007553098A JP2007553098A JP4965462B2 JP 4965462 B2 JP4965462 B2 JP 4965462B2 JP 2007553098 A JP2007553098 A JP 2007553098A JP 2007553098 A JP2007553098 A JP 2007553098A JP 4965462 B2 JP4965462 B2 JP 4965462B2
Authority
JP
Japan
Prior art keywords
semiconductor layer
layer
sidewall
forming
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007553098A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008529301A5 (enExample
JP2008529301A (ja
Inventor
ケイ． オルロースキー、マリウス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
NXP USA Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of JP2008529301A publication Critical patent/JP2008529301A/ja
Publication of JP2008529301A5 publication Critical patent/JP2008529301A5/ja
Application granted granted Critical
Publication of JP4965462B2 publication Critical patent/JP4965462B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
JP2007553098A 2005-01-31 2005-12-14 プレーナ型ダブルゲートトランジスタを形成する方法 Expired - Fee Related JP4965462B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/047,448 2005-01-31
US11/047,448 US7202117B2 (en) 2005-01-31 2005-01-31 Method of making a planar double-gated transistor
PCT/US2005/045202 WO2006083401A2 (en) 2005-01-31 2005-12-14 Method of making a planar double-gated transistor

Publications (3)

Publication Number Publication Date
JP2008529301A JP2008529301A (ja) 2008-07-31
JP2008529301A5 JP2008529301A5 (enExample) 2009-02-12
JP4965462B2 true JP4965462B2 (ja) 2012-07-04

Family

ID=36757105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007553098A Expired - Fee Related JP4965462B2 (ja) 2005-01-31 2005-12-14 プレーナ型ダブルゲートトランジスタを形成する方法

Country Status (7)

Country Link
US (1) US7202117B2 (enExample)
EP (1) EP1846945A2 (enExample)
JP (1) JP4965462B2 (enExample)
KR (1) KR20070100777A (enExample)
CN (1) CN100514547C (enExample)
TW (1) TWI397128B (enExample)
WO (1) WO2006083401A2 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7999251B2 (en) 2006-09-11 2011-08-16 International Business Machines Corporation Nanowire MOSFET with doped epitaxial contacts for source and drain
US7872303B2 (en) * 2008-08-14 2011-01-18 International Business Machines Corporation FinFET with longitudinal stress in a channel
CN101901837A (zh) * 2010-06-24 2010-12-01 复旦大学 一种栅控pn场效应晶体管及其控制方法
US9087741B2 (en) 2011-07-11 2015-07-21 International Business Machines Corporation CMOS with dual raised source and drain for NMOS and PMOS
FR2995720B1 (fr) * 2012-09-18 2014-10-24 Commissariat Energie Atomique Procede de realisation d'un dispositif a effet de champ a double grille a grilles independantes
CN104702226A (zh) * 2015-03-31 2015-06-10 宜确半导体（苏州）有限公司 一种改进的共源共栅射频功率放大器
KR102527382B1 (ko) 2016-06-21 2023-04-28 삼성전자주식회사 반도체 소자
FR3060840B1 (fr) * 2016-12-15 2019-05-31 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de realisation d'un dispositif semi-conducteur a espaceurs internes auto-alignes
FR3060841B1 (fr) 2016-12-15 2021-02-12 Commissariat Energie Atomique Procede de realisation d'un dispositif semi-conducteur a espaceurs internes auto-alignes
US10921619B2 (en) 2019-03-12 2021-02-16 Cisco Technology, Inc. Optical modulator with region epitaxially re-grown over polycrystalline silicon

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3063191D1 (en) * 1979-11-29 1983-06-16 Tokyo Shibaura Electric Co Method for manufacturing a semiconductor integrated circuit
US5258635A (en) 1988-09-06 1993-11-02 Kabushiki Kaisha Toshiba MOS-type semiconductor integrated circuit device
US5604368A (en) * 1994-07-15 1997-02-18 International Business Machines Corporation Self-aligned double-gate MOSFET by selective lateral epitaxy
US5773331A (en) 1996-12-17 1998-06-30 International Business Machines Corporation Method for making single and double gate field effect transistors with sidewall source-drain contacts
JP2967477B2 (ja) * 1997-11-26 1999-10-25 日本電気株式会社 半導体装置の製造方法
US6339002B1 (en) 1999-02-10 2002-01-15 International Business Machines Corporation Method utilizing CMP to fabricate double gate MOSFETS with conductive sidewall contacts
US6365465B1 (en) * 1999-03-19 2002-04-02 International Business Machines Corporation Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques
FR2799305B1 (fr) 1999-10-05 2004-06-18 St Microelectronics Sa Procede de fabrication d'un dispositif semi-conducteur a grille enveloppante et dispositif obtenu
WO2001028000A1 (en) 1999-10-14 2001-04-19 Shin-Etsu Handotai Co., Ltd. Method for manufacturing soi wafer, and soi wafer
TW490745B (en) * 2000-05-15 2002-06-11 Ibm Self-aligned double gate MOSFET with separate gates
US6642115B1 (en) * 2000-05-15 2003-11-04 International Business Machines Corporation Double-gate FET with planarized surfaces and self-aligned silicides
WO2002023624A2 (en) * 2000-09-14 2002-03-21 Infineon Technologies North America Corp. Field effect transistor and method of fabrication
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
FR2823010B1 (fr) * 2001-04-02 2003-08-15 St Microelectronics Sa Procede de fabrication d'un transistor vertical a grille isolee a quadruple canal de conduction, et circuit integre comportant un tel transistor
KR100414217B1 (ko) 2001-04-12 2004-01-07 삼성전자주식회사 게이트 올 어라운드형 트랜지스터를 가진 반도체 장치 및그 형성 방법
US6960806B2 (en) * 2001-06-21 2005-11-01 International Business Machines Corporation Double gated vertical transistor with different first and second gate materials
US6967351B2 (en) * 2001-12-04 2005-11-22 International Business Machines Corporation Finfet SRAM cell using low mobility plane for cell stability and method for forming
US6580132B1 (en) 2002-04-10 2003-06-17 International Business Machines Corporation Damascene double-gate FET
JP3793808B2 (ja) * 2002-05-02 2006-07-05 国立大学法人東京工業大学 電界効果トランジスタの製造方法
JP2004119693A (ja) * 2002-09-26 2004-04-15 Tokyo Inst Of Technol 強誘電体メモリデバイス及び強誘電体メモリデバイスの製造方法
JP2004128079A (ja) 2002-09-30 2004-04-22 Speedfam Co Ltd Ｓｏｉウェハーのための多段局所ドライエッチング方法
KR100481209B1 (ko) * 2002-10-01 2005-04-08 삼성전자주식회사 다중 채널을 갖는 모스 트랜지스터 및 그 제조방법
EP1519420A2 (en) * 2003-09-25 2005-03-30 Interuniversitaire Microelectronica Centrum vzw ( IMEC) Multiple gate semiconductor device and method for forming same
US7105390B2 (en) * 2003-12-30 2006-09-12 Intel Corporation Nonplanar transistors with metal gate electrodes

Also Published As

Publication number Publication date
WO2006083401A3 (en) 2007-06-14
US20060172468A1 (en) 2006-08-03
TW200636869A (en) 2006-10-16
TWI397128B (zh) 2013-05-21
KR20070100777A (ko) 2007-10-11
CN100514547C (zh) 2009-07-15
CN101103437A (zh) 2008-01-09
US7202117B2 (en) 2007-04-10
JP2008529301A (ja) 2008-07-31
WO2006083401A2 (en) 2006-08-10
EP1846945A2 (en) 2007-10-24

Similar Documents

Publication Publication Date Title
US9842737B2 (en) Self-aligned quadruple patterning process
US7629220B2 (en) Method for forming a semiconductor device and structure thereof
CN110729189B (zh) 半导体器件及其制造方法
US9343325B2 (en) Trilayer SIT process with transfer layer for FINFET patterning
CN112530943A (zh) 半导体器件及其制造方法
JP2006522486A5 (enExample)
US9269627B1 (en) Fin cut on SIT level
USRE50174E1 (en) Structure and process to tuck fin tips self-aligned to gates
JP4965462B2 (ja) プレーナ型ダブルゲートトランジスタを形成する方法
CN109473356A (zh) 用于形成垂直通道器件的方法、以及垂直通道器件
US7851340B2 (en) Semiconductor fin integration using a sacrificial fin
CN114203635A (zh) 用于形成半导体器件的方法
US11205647B2 (en) Semiconductor device and method of manufacture
TW202329329A (zh) 半導體裝置及其製造方法
CN108962750B (zh) 纳米线围栅mos器件及其制备方法
CN110970504B (zh) 晶体管
CN108565218A (zh) 环栅纳米线场效应晶体管及其制备方法
CN103187290B (zh) 鳍片式场效应晶体管及其制造方法
CN105489647B (zh) 一种半导体器件及其制造方法
US20160181382A1 (en) Method for fabricating a transistor with a raised source-drain structure
CN108231584A (zh) 环栅纳米线场效应晶体管及其制备方法
JP2015023060A (ja) 半導体装置の製造方法
TW202105617A (zh) 一種形成半導體裝置的方法
CN113394099A (zh) 半导体结构的形成方法
CN104766867A (zh) 半导体器件及其制造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20081215

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20081215

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120222

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120306

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120329

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150406

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees