TW490745B - Self-aligned double gate MOSFET with separate gates - Google Patents

Abstract

A structure and method of manufacturing a double-gate integrated circuit which includes forming a laminated structure having a channel layer and first insulating layers on each side of the channel layer, forming openings in the laminated structure, forming drain and source regions in the openings, removing portions of the laminated structure to leave a first portion of the channel layer exposed, forming a first gate dielectric layer on the channel layer, forming a first gate electrode on the first gate dielectric layer, removing portions of the laminated structure to leave a second portion of the channel layer exposed, forming a second gate dielectric layer on the channel layer, forming a second gate electrode on the second gate dielectric layer, doping the drain and source regions, using self-aligned ion implantation, wherein the first gate electrode and the second gate electrode are formed independent of each other.

Description

490745 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _B7_ V. Description of the Invention (1) BACKGROUND OF THE INVENTION Field of the Invention The present invention relates generally to a self-aligned double gate metal-oxygen half field effect transistor (DG -MOSFET). Furthermore, the top and bottom gates of the present invention can be formed using different materials. Description of Related Techniques A double gate metal-oxide-semiconductor field-effect transistor (DG-MOSFET) is a MOSFET with one top and one bottom gate of a control channel. This double-gate MOSFET has some advantages over a conventional single-gate MOSFET: higher conductivity, lower parasitic capacitance, avoiding dopant variation effects, and excellent short tunneling effects. In particular, good short channel characteristics are obtained that are as low as 20 nm channel length without the need for doping in the channel region. This circumvents all tunnel collapse, doping quality, and impurity cracking issues related to channel doping. Conventional systems have attempted to make a dual gate structure with self-aligned top and bottom gates of the channel area. However, there is no satisfactory method to obtain this self-aligned structure. Previous efforts generally fall into the following categories. A first type consists of etching silicon (Si) into a columnar structure and depositing gates (vertical field effect transistors (FETs)) around it. A second type is to etch a silicon-on-insulator (SOI) film into a thin rod. The source / drain contacts are fabricated on both sides of the rod and the gate material is deposited on all three surfaces of the thin silicon rod. Another method involves manufacturing a conventional single-gate MOSFET, and then using bonding and etch-back techniques to form the second gate. A fourth conventional method begins with a thin SOI film, patterning a strip and digging a channel under it by etching the buried oxide to form a suspended silicon bridge. Then, this method deposits completely around the suspended silicon bridge. -4- Please read the notes on the back first

Page ordering This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 490745 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs __B7_ V. Description of the invention (2) The brake material. All the above methods have serious disadvantages. For example, the first and second requirements form a vertical pillar or silicon rod with a thickness of 10 nm and it is difficult to reach this size with good thickness control and prevent reactive ion etching (RIE) damage. In this vertical example (first), it is difficult to make a low series resistance to contact the source / drain terminal buried under the pillar. In another example (second), the width of the device is limited by the height of the silicon rod. In this third example, thickness control and top / bottom gate self-alignment are major issues. In the fourth example, the control beyond the gate length is poor, and the two gate systems are electrically connected and must be formed of the same material. Application No. 09 / 272,297 (hereinafter referred to as nChan,) filed on March 19, 1999, incorporated herein by reference, jointly filed by KK K. Chan, GM Cohen, Y. Taur, and HSP Wong The instruction is named " Self-Aligned Double-Gate MOSFET by Selective Epitaxy and Silicon Wafer Bonding Techniques .... using a method for manufacturing a dual-gate MOSFET structure with self-aligned top and bottom gates in the channel region . The regulations avoid most of the above problems. However, the top and bottom gates are still physically connected. This occurs because the gate material is deposited in a processing step to form a π all around the channel. This is not expected in some applications for the following reasons. First, from the point of view of circuit design, a two-electrically separated gate is better. Second, the bottom gate and the top gate system are mainly formed of the same material, so that only a symmetrical DG-MOSFET can be manufactured. The bottom gate material is different from the asymmetric DG-MOSFET of the top gate and cannot be manufactured. Please read the notes on the back first

Page Alignment This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 490745 A7 B7 V. Description of the invention (3) Chan revealed that a suspension silicon bridge (the channel) is formed, followed by a uniform surround E To deposit the gate material to form a " all around the channel, the gate. In order to obtain a good threshold voltage control, the channel thickness should be reduced to 3-5 nanometers. It's unclear whether such thin bridges can be handled with high yields. As such, this would impose a restriction on the system proposed by Chan. Therefore, there is a need for depositing independent top and bottom gates to form a self-aligned DG-MOSFET. This type of structure will yield many advantages. For example, the independently formed gate allows the gate to be electrically separated; forming and providing a planarized structure by changing the material and thickness makes it easy to connect the device. In addition, there is a dg_m0sfet for allowing the formation of a very thin channel (please read the precautions on the back before this page)-installation requirements. Summary of the invention Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics Therefore, one object of the present invention is to provide a structure and method for manufacturing a double gate integrated circuit, which includes forming a passivation layer on each side of the channel layer And the first insulating layer of the laminated structure, forming an opening in the laminated structure, forming a drain and source region in the opening of the child, removing a part of the laminated layer from the laminated structure A part is formed on the channel layer—a first gate dielectric layer, a first gate is formed on the first gate dielectric layer, so that the laminated structure leaves an exposed channel layer A second part, forming a second gate dielectric layer on the salt transport layer, forming a second gate on the second gate dielectric layer, and doping using self-aligned ion implantation In the drain and source regions, the first gate and the second gate are formed separately from each other. The salt gate is typically formed of silicon dioxide, but it can be made of other dielectric materials. This paper rule Money_Household Standard (CNS) A4 size 7J10 x 297 meters ^ 7 lines. 490745 Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Printing KI_Β7_ V. Description of Invention (4) Formation. At the same time, the gate dielectric related to the top gate is independent of the gate dielectric related to the bottom gate. As such, the gate dielectric can be of different thicknesses and materials. Brief Description of the Drawings The foregoing and other objects, viewpoints, and advantages will be better understood from a preferred embodiment of the present invention, which is described in detail below with reference to the drawings. Schematic diagram of a part of a thin stack deposition and adhesion method; Figure 2 is a schematic diagram describing a part of the thin stack deposition and adhesion method; Figure 3 is a diagram of a thin stack Schematic diagram of partial deposition and adhesion method; Figure 4 is a schematic diagram describing a part of the deposition and adhesion method used to make a thin stack; Schematic diagram of the bonding method; Figure 6 is a schematic diagram describing a part of the deposition and bonding method used to make a thin stack; Figure 7 is a schematic diagram illustrating a cross section along the LL line in Figure 8; / Figure 8 FIG. 9 is a schematic diagram illustrating a top view of a DG-MOSFET manufactured according to the present invention; FIG. 9 is a schematic diagram illustrating a cross-section taken along line LL in FIG. 10; Using the epitaxial method to extend the SOI channel to the source Schematic diagram of the drain region; (Please read the precautions on the back before ^ —— this page) ·. _Line · This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) A7 B7 Ministry of Economy Wisdom Printed by the Employees' Cooperative of the Property Bureau V. Description of the invention (5) Figure 11 is a schematic diagram describing the side wall spacer; Figure 12 is a description of filling the source and drain trenches with the source / drain material and Then use CMP as its schematic diagram; Figure 13 is a schematic diagram describing the source and non-recessed recesses; Figure 14 is a schematic diagram describing the source and drain recesses filled with a dielectric material; Figure 15 is A schematic diagram describing the etching of the top nitride film; FIG. 16 is a schematic diagram describing the formation of the side wall, FIG. 17 is a schematic diagram describing the structure after the top gate dielectric is grown; FIG. 18 is a diagram illustrating the deposition of the top gate material And a schematic diagram of the structure after using CMP for its planarization; FIG. 19 is a schematic diagram describing the use of the nitride hard mask to define the device platform; FIG. 20 is a schematic diagram illustrating a section along the LL line in FIG. 19; Figure 21 describes this Figure 22 is a schematic diagram of the structure along the LL line after the table is etched; Figure 22 is a diagram illustrating the structure along the WW line after the platform is etched; Figure 23 is a schematic diagram of the side wall along the LL line; Figure 24 is a description Schematic diagram of the side wall along the WW line; / Figure 25 is a schematic diagram illustrating the structure along the LL line after the platform has been etched into the box; Figure 26 is a schematic depicting the platform etched to the rear edge of the box The schematic diagram of the structure along the LL line; Figure 27 is a description of the structure along the LL line and the oxidation is used to insulate the dew (please read the precautions on the back first and then 3 ^ this page). Applicable to China National Standard (CNS) A4 (210 X 297 mm) 490745

V. Description of the invention (6 Schematic diagram of the source and non-polar walls; Figure 28 is a description of the structure along the WW grasshopper> She 4 Lane · mp, mouth w νν, 杲 < structure and the use of oxidation to Schematic diagram of insulating the exposed source and non-electrode sidewalls; Figure 29 is a schematic diagram illustrating the structure along the LL line after the bottom nitride film is removed by wet etching; Figure 30 is a schematic diagram illustrating the removal of the bottom nitrogen by wet etching Schematic diagram of the structure along the WW line after the formation of the film; FIG. 31 is a schematic diagram of the structure along the L_L line after growing the bottom gate dielectric, depositing the bottom gate material, and flattening it with CMP; FIG. 32 It is a schematic diagram describing the structure along the w_w line after the bottom gate dielectric is grown, the bottom gate material is deposited, and CMP is used to planarize it. The structure of the dielectric material along the LL line after forming a side wall; FIG. 34 is a schematic diagram of the structure of the dielectric material along the WW line after removing the dielectric from the source drain recess region; Series 35 describes self-aligned source / drain implantation along the LL line Schematic diagram; Figure 36 is a schematic diagram describing the formation of self-aligned silicide along the LL line; Figure 37 is a schematic diagram describing the formation of self-aligned silicide along the LL line; The recessed source and drain regions are based on a paper size that applies the Chinese National Standard (CNS) A4 (210 X 297 mm) (please read the precautions on the back first || ^ this page)- --Line · Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 490745 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (7) Schematic diagram of refilling of electrical materials; Figure 39 is a description for etching this Top schematic view along the LL line in a nitride hard mask with excessive bottom gate material; FIG. 40 is a schematic top view illustrating the WW line in a nitride hard mask with excessive bottom gate material; FIG. 41 is a schematic diagram describing the purification and planarization of a device using a dielectric deposition and CMP along the LL line; FIG. 42 is a schematic depicting the use of a dielectric deposition and CMP as a passivation for the device along the w_W line Schematic diagram of flattening; Figure 43 A schematic diagram describing the passivation and planarization of the device using a dielectric deposition and CMP along the l_L line; FIG. 44 is a description depicting the passivation and planarization of the device using a dielectric deposition and CMP along the WW line Schematic diagram; Figure 45 is a schematic diagram describing the contact holes (through holes) openings used to contact the source and drain of the device and the top and bottom gates; Figure 46 is a diagram depicting the source and drain contacts of the device Schematic diagram of the contact hole (through hole) opening of the electrode and the top and bottom gate electrodes; FIG. 47 is a diagram describing the opening of the contact hole (through hole) and the contact used to contact the hum, drain and top and bottom gates of the device; Schematic diagram of metallization; Figure 48 is a schematic diagram of a partially completed structure along the line w-w according to the present invention; and Figure 49 is a schematic top view of the structure of the present invention. The preferred embodiment of the invention is described in detail below. A self-aligned double with an electrically separated top and bottom gates -10- (Please read the precautions on the back before 3 ^ this page) 士 L5J · --- This paper size applies to China National Standard (CNS) A4 specification (210 x 297 mm) 490745 A7 B7 V. Description of the invention (8) Gate metal oxide semiconductor (DG-MOSFET) and its manufacturing method. Furthermore, the top and bottom gates include different materials. As shown in Figures 1-6, the invention begins with the formation of a series of layers. First, the present invention forms a thin silicon dioxide 1 (for example, about 2 nanometers thick) on a single wafer 5 A, which is referred to as the donor wafer. Second, a layer of silicon nitride 2 (which may be, for example, about 100 nanometers thick) is formed on the silicon dioxide layer 1. Third, a thick (eg, about 400 nm) silicon dioxide layer 3 is formed on the silicon nitride layer 2. Fourth, the wafer is bonded to an operation wafer 4. The bonding uses standard silicon wafer bonding techniques, such as boron etch stop, smartCut, and those familiar with those skilled in the art (a detailed discussion of bonding techniques can be found in 1997 incorporated herein by reference) The second edition of Kluwer Academic Press published by Silicon-On-Insulator Technology by Jean-Pierre Colinge. Next, the SOI layer 5 is formed to a thickness required for the MOSFET channel. For example, if the smartCut technology is used, a thin second layer is transferred from the surface of the donor wafer 5 A to the operation wafer 4. The transmitted fragment is typically adhered to an insulating film such as silicon dioxide, and is therefore referred to as silicon on insulator (SOI). The thickness of the transferred SOI film is determined by the hydrogen implantation depth of part of the smartCut technology. Once the SOI film is transferred onto the operation wafer 4, it can be further thinned by oxidation and striping. The thickness of the SOI film is typically measured using ellipse or X-ray diffraction technology (see here incorporated by reference, August 1999, Applied Physics Letters by GM Cohen et al, Issue 75 (6), p. 787 ) To monitor. Next, a thin layer of silicon dioxide 6 is formed on the SOI layer 5 (approximately 2 nanometers-11-this paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm)) (Please read the note on the back first) Matters reprinted on this page): ® Printed clothing B7 by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (9) m). This system then forms a thick silicon nitride layer 7 (for example, about 150 nm) on the silicon dioxide layer 6. After the first tandem layer is completed, the present invention etches two regions 8 in the stacked film. As shown in Figures 7 and 8, the etch stop (or other similar control feature) is positioned at some distance from the buried oxide (BOX) 3. The distance between these two regions will be the gate length (Lg) of the MOSFET manufactured. This disclosure illustrates the structure and method of the present invention along different section lines for clarity. For example, Figures 7, 9, 11-18, 20, 21, 23, 25, 27, 29, 31, 33-38, 40, 41, 43, 45, and 47 are top views of Figures 8 and 9 along LL Schematic illustration of the line cut. The invention begins a series of steps to reshape the etched area. First, as shown in FIGS. 9 and 10, an epitaxial silicon (epi) extension 9 system selectively grows outside the single crystal SOI 5 channel. The epi extension 9 extends to the etched area 8 and grows around the entire circumference of the etched area. The epi extension 9 is preferably about 50 nm in size. Extensions can also be achieved by growing other alloys such as silicon germanium, silicon carbide germanium, or other suitable materials known to those skilled in the technology.

Next, the present invention forms a side wall spacer 10 on the side wall of the etched area 8 as shown in FIG. This system uses a dielectric (not included in the pattern) deposited on the entire structure to perform the shape. The thickness of the dielectric determines the thickness of the spacers 10 caused. The dielectric may also be a composite (e.g., an oxide and nitride layer is then deposited) to provide etch selectivity. In a preferred embodiment, a reactive ion etch system is used to form the sidewall spacers 10. In addition, isotropic etching (reactive ion etching or wet chemical etching) is performed from this SOI -12- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 490745 A7 B7 V. Description of the invention ( 1) The remaining spacer dielectric is removed during the silicon extension by exposing the silicon. Next, as shown in FIG. 12, the present invention forms a source / drain region 11. This system first deposits amorphous silicon or polycrystalline silicon 11 into the etched region 8. As shown in FIG. 12, the amorphous silicon is deposited until the amorphous silicon level is higher than the surface of the nitride 7. Second, chemical-mechanical polishing (CMP) was used to flatten the top surface. The CMP process mainly removes amorphous silicon and selects nitride 7 °. Then, as shown in FIG. 13, the silicon in the source / inverted region 11 is etched using reactive ions to form the recess 12. Finally, as shown in FIG. 14, a dielectric 13 (such as an oxide) is accumulated to the concave region I, so that the dielectric completely conforms to the concave region 12. Next, the dielectric is planarized using CMP. At the same time, the present invention reshapes the top of the structure shown in FIG. 15. This is performed 'first' to remove the top nitride 7 using wet chemical etching (e.g., hot phosphoric acid). Second 'forms the side wall µ as shown in FIG. The wall is formed by uniformly depositing a dielectric onto the entire structure and then etching the dielectric to form a side wall. The thickness of the dielectric determines the thickness of the side wall 14. Third, the top sacrificial pad oxide is removed by wet chemical etching (for example, hydrofluoric acid). Next, a top gate dielectric 15 is grown on the top surface of the soi channel 5 as shown in FIG. 17. . The top gate material 16 (for example, doped polycrystalline silicon or crane) is uniformly deposited to form a gate electrode as shown in FIG. 18. Finally, chemical mechanical polishing is used to planarize the top surface. The CMP process uses a slurry of selective nitride 7 to primarily remove the top gate material. Next, the present invention places a platform hard mask 17 on the structure shown in FIGS. 19 and 20. The platform hard mask is made of a thickness of preferably about 100 nanometers. -13- The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) A7 5. Description of the invention (11)

A nitride film is deposited and then patterned. Figures 22, 24, 26, 28, 30, 32, 42, 44, 46, and 48 are cross-sectional views taken along line W-W shown in Figure 19. More specifically, the present invention uses the platform hard mask 7 to isolate individual devices. The structure was patterned as follows: (1) The SOI film was etched through reactive ion etching (RIE) and stopped on the nitride shown in Figures 21 and 22; ⑺ uniformly deposited a For example, a dielectric of low temperature oxide (LT0) of about 75 nanometers is preferable and the dielectric is etched to form a side wall ι8 as shown in Figs. 23 and 24; (3) the platform is completed by etching a certain distance Etching becomes BOX 3 as shown in Figs. The bottom nitride 2 side wall is also exposed during this process. As shown in FIGS. 27 and 28, a thermal oxide 19 is grown in the present invention to isolate the exposed source and drain walls. Next, as shown in FIGS. 29 and 30, the present invention removes the bottom nitride 2 and the top nitride hard mask 17 by wet chemical etching (for example, hot phosphoric acid). The bottom nitride 2 is removed to form a channel 20 along the width of the device and a suspension bridge along the length. At the same time, the bottom sacrificial pad oxide 1 is removed using a wet chemical etch (for example, a hydrofluoric additive). Next, as shown in FIGS. 31 and 32, the present invention forms the bottom gate electrode 22. This is achieved by a first growing bottom gate dielectric 21 on the bottom surface of the SOI channel 5. The bottom gate material 22 (eg, doped polycrystalline silicon, tungsten, etc.) is uniformly deposited to form the bottom gate. Next, CMP is used to planarize the top surface. The CMP process mainly removes the bottom gate material and selects it to the LT0 13. 14- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 public love) (Please read the precautions on the back before filling out this page) Dan Filler · Intellectual Property Bureau, Ministry of Economic Affairs, Consumer Consumption Cooperative, Printing A7- -—-— B7_____ — V. Description of the Invention (l2) As shown in FIG. 33, the present invention etches the source / drain cap dielectric LT〇13. As shown in FIG. 34, the present invention uniformly deposits a dielectric on the entire structure to form the side wall 23. Again, this dielectric thickness determines the thickness of the resulting spacer. The dielectric is then etched to form the final sidewall structure 23. Next, as shown in FIG. 35, the present invention uses a self-aligned ion implantation 24 to dope the source / drain regions 11 to dope silicon at a high concentration. To mask the soi channel region from the ion implantation, the top multi-gate 16 is used as a self-aligned implantation mask. The side wall spacer 23 will be implanted by displacing the source / drain from the channel region. The implant is then subjected to a rapid thermal tempering to activate the dopant. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Next, as shown in FIG. 37, a self-aligned silicide treatment is applied to form a silicide 26 covering the source / drain and gate 11. This is done using any standard treatment method known to those skilled in the art. For example, in the preparation for the silicide, a metal 25 such as titanium or titanium is uniformly deposited on the entire structure as shown in Fig. 36 and the structure is heated. After depositing the silicide, as shown in FIG. 38, a dielectric such as LTO is uniformly deposited on the silicide to form an LTO cover 27. This is followed by using CMP to planarize the top surface. The CMP process mainly removes the dielectric material 27 and selects the silicide 26 and / or the gate materials 16 and 22. Due to the limited selection of this CMP process, some or all of the gate silicide 26 will be removed. In this example, the self-aligned silicide process is repeated to form a new gate silicide. Then, the bottom gate electrode 22 is terminated. First, a nitride or LTO film 27, preferably about 100 nanometers, is deposited and then lithographically used to -15- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love) " ~ ~ 490745 A7

V. Description of the Invention (13) Patterning to form a hard mask defining a bottom gate region 28 as shown in the top view of FIG. 39 and the section along the line L_L in FIG. 40. Second, the excess bottom gate material 22 is etched down to the B0X 3, and a thick passivation dielectric 29 is deposited as shown in "" and "". Then use CMP to flatten the top surface. The CMP process primarily removes the dielectric material 29 and chooses not to remove the nitride hard mask 28. A second passivation dielectric 30 is then deposited as shown in Figs. Next, as shown in FIGS. 45 and 46, a contact hole 31 is formed on the source and drain electrodes 1] L by patterning and etching using photolithography, and the contact hole 32 is etched and covered on the two gate electrodes 16, 22 on. Metallization 33 is then deposited and then patterned to form electrical contacts to the source, the drain, and the bottom and top gates as shown in Figures 47 and 48. If the gate length is very short, a second-order metallization can be applied to allow a looser design rule for the top gate contact. Figure 49 shows a top view of the complete structure. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Many benefits over conventional techniques are achieved by using specific improvements of the present invention. First, the present invention deposits the top and bottom parts in two separate steps and produces electrically separated top and bottom parts, which leads to some advantages. For example, the bottom gate can be used to control the far threshold voltage 'thereby allowing a hybrid threshold voltage (Vt) circuit for low current applications. This structure is also allowed for increasing the circuit density. When the gate system is electrically separated, the 'far double-gate MOSFET includes a four-terminal device having two input gates. As such, a single device can be used to configure two-bit logic operations such as an inverse sum gate (nFET) or an inverse sum gate (pFET) cell. Configuring these two-bit logic functions typically requires two standard MOSFETs per cell. In this circuit density, the paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love) 490745 A7

Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. This increase in invention note (14) is also applied to the analog circuit. For example, one: ¾ at the time of mixing can be configured by applying the oscillator voltage to one gate and the signal (data) voltage to the other gate. Because the present invention grows the top and bottom gates and the gates are electrically separated, the gates and the dielectric can be of different materials and different thicknesses. Moreover, different doping levels and doping types can be integrated into each gate. Therefore, a non-symmetrical gate can be manufactured. The asymmetric double-gate MOSFET system is most suitable for mixed applications where the gates are connected together to obtain speed requirements and can be used separately to obtain, for example, low current and high density for static random access memory (SRAM). At the same time, the present invention provides a planar structure that makes it easy to connect the device. Devices with a very thin channel about 3 to 5 nanometers thick need to have a good threshold voltage behavior. Fabricating a suspended silicon bridge with a thin layer reduces overall yield. The present invention maintains the channel with a thick layer 22. Thus, the present invention allows devices with very thin channels to be manufactured and allows such devices to have a good critical voltage behavior. The present invention also utilizes a self-aligned silicidation process to reduce the _connection resistance. The present invention has been described with the preferred embodiment as a representative, and those skilled in the art will understand that the present invention can be modified and implemented within the spirit and scope of the attached patent application scope. · Please read the notes of S first. Binding Page -17-

Claims (1)

490745 A8 B8 C8 D8 VI. Patent application scope 1. A transistor including: a channel region; a first gate electrode in the channel region; a second gate electrode in the channel region; A gate and the second gate are electrically separated from each other. 2. For the transistor according to item 1 of the patent application scope, wherein the first gate electrode includes a concentration different from that of the second electrode. 3. The transistor according to item 1 of the patent application, wherein the first gate includes a doping type different from that of the second gate. 4. The transistor according to item 1 of the patent application scope further includes a first gate dielectric below the first gate and a second gate dielectric above the second gate. 5. The transistor according to item 1 of the patent application, wherein the first gate has a first conductive contact and the second gate has a second conductive contact, and the first conductive contact and the second conductive contact Co-planar. 6. The transistor according to item 1 of the patent application, wherein the first gate includes a material different from the second gate. 7. The transistor as claimed in claim 1, wherein the first gate includes a thickness different from that of the second gate. 8. The transistor according to item 1 of the patent application, wherein the third gate, the second gate and the channel region form a planarization structure. 9. The transistor according to item 4 of the patent application, wherein the first gate dielectric includes a material different from the second gate dielectric. -18-This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm). Please read the notes on the back before reading Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed 490745 A8 B8 C8 D8 VI. Application for patent scope 10. For the transistor with the scope of patent application item 4, the first gate dielectric includes a The thickness of the two gate dielectric. 11. A semiconductor wafer having at least one transistor, the transistor comprising: a channel region; a first gate on the top of the channel region; a second gate under the channel region; wherein the first The gate includes a material different from the second gate. 12. The semiconductor wafer as claimed in claim 11, wherein the first gate and the second gate have different dopant concentrations. 13. For example, the semiconductor wafer of claim 11 in which the first gate and the second gate have different types of dopants. 14. The semiconductor wafer as claimed in claim 11 further comprising a first gate dielectric below the first gate and a second gate dielectric above the second interrogator. 15. The semiconductor wafer as claimed in claim 14, wherein the first gate dielectric comprises a material different from the second gate dielectric. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 16. For the semiconductor chip of the scope of application for patent No. 14, wherein the first gate dielectric includes a thickness different from that of the second gate dielectric. 17. The semiconductor wafer as claimed in claim 11 in which the first gate has a first conductive contact and the second gate has a second conductive contact, and the first conductive contact and the second conductive contact Coplanar plane 0 18. For the semiconductor wafer with the scope of patent application No. 11, where the first gate -19- this paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 490745 A8B8C8D8 Intellectual property of the Ministry of Economic Affairs Printed by the Bureau's Consumer Cooperatives 6. The scope of patent application and the second gate are electrically separated. 19. The semiconductor wafer as claimed in claim 11, wherein the first gate and the second gate have different thicknesses. 20. The semiconductor wafer as claimed in claim 11, wherein the first gate, the second gate, and the channel region form a planarization structure. 21. A method of forming a transistor, comprising the steps of: forming a laminated structure including a first gate electrode covering a channel region; removing the laminated portion under the channel region; and A second gate is formed under the channel region, wherein the first gate and the second gate are electrically separated from each other. 22. The method of forming a transistor as claimed in claim 21, wherein the first gate supports the channel region during the removal method. 23. The method of forming a transistor as claimed in claim 21, wherein the first gate includes a doping concentration different from that of the second gate. 24. The method for forming a transistor according to item 21 of the patent application scope, further comprising applying different kinds of impurities to the first gate electrode and the second question electrode. 25. The method for forming a transistor according to item 21 of the scope of patent application, further comprising forming a first gate dielectric under the first gate and a second gate dielectric over the second gate. quality. 26. The method of forming a transistor as claimed in claim 24, wherein the first gate dielectric includes a material different from the second gate dielectric. -20- This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before I ___ This page:-" a · line- 490745 A8 B8 C8 D8 Ministry of Economy Printed by the Intellectual Property Bureau employee consumer cooperative 6. Application for patent scope 27. For the method of forming a transistor in the scope of application for patent No. 24, wherein the first gate dielectric includes a gate dielectric different from the first gate dielectric 28. The method for forming a transistor according to item 21 of the scope of patent application, further comprising forming a first gate oxide under the first gate electrode and a second gate electrode on the second gate electrode. Oxide 29. The method for forming a transistor according to item 21 of the patent application, wherein the first gate has a first conductive contact and the second gate has a second conductive contact, and the first conductive contact And the second conductive contact are coplanar. 30. If the method of forming a transistor according to item 21 of the patent application, the first gate electrode includes a material different from the second gate electrode. 31. If the patent application item 21 The first method of forming a transistor The gate includes a thickness different from that of the second gate. 32. The first gate, the second gate, and the channel region form a flat twist structure as in the method for forming a transistor of item 21 of the patent application. 33 · -A method for manufacturing a double-gate transistor, including the following steps: forming a laminated structure having a channel layer and a first layer on each side of the channel layer; #-forming an opening in the laminated structure by insulation ; Forming a drain and source region in the opening; removing a part of the laminated structure to leave a part exposing the channel layer; 3 < __ · __- 21-This paper size applies to the Chinese National Standard (CNS ) A4 specifications (21G X 297) _ (Please read the precautions on the back before I · n on the first page of this page where one of the four dagger knot line- The scope of the patent application is to form a first gate dielectric layer on the home channel layer; to form a first gate electrode on the first gate dielectric layer; to remove the laminated structure to leave the channel exposed One of the first layer of the layer; forming a second gate dielectric layer on the child passivation layer;第二 A second gate is formed on the second gate dielectric layer; the drain and source regions are doped so that the first gate and the second gate are mutually shaped (please read the note on the back first) Matters on page 9) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 34. If the method of patent application No. 33 is applied, the gates are electrically separated. 35. The method according to item 33 of the patent application. The polar region includes a self-aligned ion implantation. 36. The method of claim 33, wherein the method further includes forming the first gate electrode to have a thickness greater than a thickness of the second gate electrode. For example, the method of item 33 of the Shenlong patent scope, wherein the method further includes forming the first gate electrode to have a width larger than the width of the second gate electrode. The method of claim 33, wherein the method further includes forming the first gate dielectric to have a width greater than the width of the second gate dielectric. 39. The method of claim 33, further comprising forming the first gate from—a first material and the second from a second material—the first and first doping the drain and Source .: Line · (CNSM4 specification (21〇-22- x 297 ^ 17 490745 A8 B8 C8 D8 6. Apply for patent range gate. 40. For the method of applying for patent range item 33, further includes forming a source from a first The first gate dielectric of the material and the second gate dielectric of a second material. 41. For example, the method of claim 33 in the patent application range, in which a portion of the laminated structure is removed and left A channel is formed in the laminate by exposing a second part of the channel layer, and wherein the channel is formed between an upper layer and a lower layer. 42. The method of claim 33 in the patent application, wherein the The first gate dielectric includes a material different from the second gate dielectric, I, A. 43. For example, the method for applying a salute to item 33 of the patent application, wherein the first gate dielectric includes a丨 Thickness of two gate dielectrics 0 (Please read the note on the back first Re-entry page) line - Ministry of Economic Affairs Intellectual Property Office employees consumer cooperatives printed -23- This paper scales applicable Chinese National Standard (CNS) A4 size (210 X 297 mm)