CN1219329C - Self-aligned dual-gate metal-oxide-semiconductor field-effect transistor with split gate - Google Patents

Abstract

Double-gate integrated circuit structure and manufacturing method thereof, comprising: forming a stacked structure having a channel layer and a first insulating layer on each side of the channel layer; forming an opening in the stacked structure; forming a drain region and a source region in the opening ; exposing the first part of the channel layer; forming a first gate dielectric layer on the channel layer; forming a first gate on the first gate dielectric; exposing the second part of the channel layer; forming on the channel layer a second gate dielectric layer; forming a second gate on the second gate dielectric layer; doping the drain and source regions by self-aligned ion implantation, wherein the first gate and the second gate are formed separately from each other.

Description

Self-aligned dual-gate metal-oxide-semiconductor field-effect transistor with split gate

technical field

The present invention generally relates to self-aligned dual-gate metal-oxide-semiconductor (DG-MOSFET) having electrically separated top and bottom gates. In addition, in the present invention, the top gate and the bottom gate may be formed of different materials.

Background technique

A dual-gate metal-oxide-semiconductor field-effect transistor (DG-MOSFET) is a MOSFET with a top gate and a bottom gate that control the charge carriers in the channel. Dual-gate MOSFETs have several advantages over conventional single-gate MOSFETs: higher transconductance, low parasitic capacitance, avoidance of dopant fluctuation effects, and excellent short-channel characteristics. In addition, good short channel characteristics with a channel length as low as 20 nm and no doping in the channel region can be obtained. Tunneling, dopant quantization, and impurity scattering problems associated with channel doping can then be prevented.

Conventional systems attempt to self-align a dual gate structure with a top gate and a bottom gate with the channel region. However, there is still no satisfactory method of realizing such a self-aligned structure. Previous efforts have generally focused on the following aspects. The first aspect involves etching silicon (Si) into pillar structures and depositing gates (vertical field effect transistors (FETs)) around them. The second aspect is to etch the silicon film on the insulator into a thin rod shape, so that the source/drain contacts are located at both ends of the rod, and deposit gate material on all three surfaces of the thin Si rod. Another way is to make a conventional single-gate MOSFET and then use a bond-back technique to form the second gate. A fourth conventional approach starts with a thin SOI film, which is then patterned and tunneled under it by etching a mask oxide to form suspended Si bridges. The method then deposits gate material around the suspended Si bridges.

All of the above methods have serious flaws. For example, the first and second methods require vertical pillars or Si rods with a thickness of 10nm, but it is difficult to achieve this size under the condition of well-controlled thickness, and it is difficult to prevent reactive ion etching (RIE) damage. Meanwhile, in the vertical (first approach) case, it is difficult to achieve low series resistance contact with the source/drain terminals buried under the pillars. In the latter (second approach) case, the device width is limited by the Si rod height. In the third case, thickness control and top/bottom gate self-alignment are the main issues. In the fourth case, the gate length is poorly controlled, the two gates are electrically connected and must be formed from the same material.

Copending Application No. 09/272297, filed March 19, 1999, by K.K.Chan, G.M.Cohen, Y.Taut, H.S.P. Wong, entitled "Self-Aligned Double-Gate MOSFET by Selective Epitaxy and Silicon Wafer Bonding Techniques" (hereinafter referred to as Chan), which is hereby incorporated by reference, employs a method of fabricating a dual-gate MOSFET structure with top and bottom gates self-aligned to the channel region. This method overcomes most of the above-mentioned problems. However, the top and bottom gates are still physically connected. This is due to the fact that the gate material is deposited as an "all-around the channel" gate in only one process step.

This is undesirable in some applications for the following reasons. First, from a circuit design point of view, two electrically separated gates are preferable. Second, the bottom and top gates are basically made of the same material, so only symmetrical DG-MOSFETs can be fabricated. An asymmetrical DG-MOSFET with a different bottom gate material than the top gate cannot be realized.

Chan discloses a method of forming a "full-enclosed trench" gate by forming a suspended silicon bridge (trench) and then conformally depositing gate material around it. For good threshold voltage control, the channel thickness should be as thin as 3-5 nm. It is unclear whether such thin bridges can be processed in sufficiently high yields. Therefore, there will be limitations to the method proposed by Chan.

Therefore, there is a need for self-aligned DG-MOSFETs that can be formed by depositing the top and bottom gates separately. This structure will yield many advantages. For example, each gate can be electrically separated by forming each gate separately; each gate can be fabricated with different materials and different thicknesses, which can provide a planar structure for easy connection of devices. In addition, DG-MOSFETs capable of forming very thin channels are also desired.

Contents of the invention

Therefore, the object of the present invention is to provide a dual-gate integrated circuit structure and a method of manufacturing the same, said method comprising: forming a stacked structure having a channel layer and a first insulating layer on each side of the channel layer; Openings are formed on the structure; drains and sources are formed in the openings; some parts of the stacked structure are removed to expose the first part of the channel layer; a first gate dielectric layer is formed on the channel layer; a gate dielectric layer is formed on the first gate dielectric layer The first gate; removing some parts of the stacked structure to expose the second part of the channel layer; forming a second gate dielectric layer on the channel layer; forming a second gate on the second gate dielectric layer; alignment ion implantation, doping the drain region and the source region, wherein the first gate and the second gate are formed separately.

The present invention provides a transistor comprising: a channel region; a first gate on top of the channel region; a second gate below the channel region; and a source region and a drain adjacent to the channel region region; wherein said channel region includes extensions extending into said source and drain regions.

The present invention provides a transistor, comprising: a channel region; a first gate on the top of the channel region; a second gate below the channel region; and a source region adjacent to the channel region and a drain region; wherein said channel region includes extensions extending into said source and drain regions, wherein said first gate is of a different material than said second gate.

The present invention provides a semiconductor chip having at least one transistor, said transistor comprising: a channel region; a first gate on top of said channel region; a second gate below said channel region; A source region and a drain region adjacent to the channel region; wherein, the source region and the drain region are self-aligned with the first gate and the second gate, and the source region and the drain region are aligned with the first gate and the second gate The two gates do not overlap each other; and wherein said channel region includes extensions extending into said source and drain regions, wherein said first gate is of a different material than said second gate.

The present invention provides a method for manufacturing a double-gate transistor, comprising: forming a stacked structure having a channel layer and insulating layers on upper and lower surfaces of the channel layer; forming openings in the stacked structure, The insulating layer on the lower surface of the channel layer is exposed at the opening; a drain region and a source region are formed in the opening, and an epitaxial layer is selectively grown from the channel layer to extend to the opening region; the stacked structure is removed in the an insulating layer on the upper surface of the channel layer, exposing the upper surface of the channel layer; forming a first gate dielectric layer on the channel layer; forming a first grid on the first gate dielectric layer; removing The insulating layer of the laminated structure on the lower surface of the channel layer exposes the lower surface of the channel layer; a second gate dielectric layer is formed on the lower surface of the channel layer; forming a second gate on the dielectric layer; doping the drain region and the source region, wherein the first gate and the second gate are formed separately from each other and have different materials.

The gate dielectric is generally composed of SiO ₂ , but can also be formed of other dielectric materials. In addition, the gate dielectric associated with the top gate is different from the gate dielectric associated with the bottom gate. The gate dielectric can then be formed from different thicknesses and from different materials.

Description of drawings

From the following detailed description of the preferred embodiments of the present invention in conjunction with the accompanying drawings, the above-mentioned and other objects, solutions and advantages of the present invention can be better understood, wherein:

Figure 1 is a schematic diagram showing a portion of the deposition and bonding used to fabricate a film stack;

Figure 2 is a schematic diagram showing a portion of the deposition and bonding used to fabricate a film stack;

Figure 3 is a schematic diagram showing a portion of the deposition and bonding used to fabricate a film stack;

Figure 4 is a schematic diagram showing a portion of the deposition and bonding used to fabricate a film stack;

Figure 5 is a schematic diagram showing a portion of the deposition and bonding used to fabricate a film stack;

Figure 6 is a schematic diagram showing a portion of the deposition and bonding used to fabricate a film stack;

Fig. 7 is a schematic cross-sectional view taken along the line L-L in Fig. 8;

Figure 8 is a schematic top view of a DG-MOSFET manufactured according to the present invention;

Figure 9 is a schematic cross-sectional view of Figure 10 taken along the L-L line;

Fig. 10 is a schematic top view of a DG-MOSFET manufactured according to the present invention, showing the extension of the SOI channel into the source and drain regions by epitaxy;

Figure 11 is a schematic diagram showing sidewall pads;

Figure 12 is a diagram showing filling of source and drain trenches with source/drain material and subsequent planarization using CMP;

13 is a diagram showing source and drain recesses;

Figure 14 is a diagram showing source and drain wells filled with a dielectric material;

Fig. 15 is a diagram showing the corrosion situation of the upper nitride film;

Fig. 16 is a diagram showing the formation of side walls;

Figure 17 is a diagram showing the structure after growing the top gate dielectric;

Figure 18 is a diagram showing the structure after deposition of top gate material and planarization by CMP;

Figure 19 is a diagram showing a structure with a nitride hard mask for defining device mesas;

Figure 20 is a sectional view of Figure 19 taken along the line L-L;

Fig. 21 is a diagram showing the structure along the L-L line after the mesa is etched;

Fig. 22 is a diagram showing the structure along the line W-W after the mesa is etched;

Figure 23 is a diagram showing sidewalls along line L-L;

Figure 24 is a diagram showing sidewalls along line W-W;

Fig. 25 is a diagram showing a structure in which the mesa is continuously etched into a box-shaped trailing edge L-L;

Fig. 26 is a diagram showing a structure in which the mesa is continuously etched into a box-shaped trailing edge L-L;

27 is a diagram showing the structure along the line L-L and the situation of the source and drain sidewalls exposed by the oxidation isolation;

28 is a diagram showing the structure along the line W-W and the situation of the source and drain sidewalls exposed by the oxidation isolation;

29 is a diagram showing the structure along line L-L after removing the bottom nitride film by wet etching;

30 is a diagram showing the structure along line W-W after removing the bottom nitride film by wet etching;

31 is a diagram showing the structure along the line L-L after bottom gate dielectric growth, bottom gate material deposition, and planarization by CMP;

32 is a diagram showing the structure along the line W-W after bottom gate dielectric growth, bottom gate material deposition, and planarization by CMP;

33 is a diagram showing the structure along the line L-L after removing the dielectric in the source-drain recess region and forming sidewalls;

34 is a diagram showing the structure along the line W-W after removing the dielectric in the source-drain recess region and forming sidewalls;

Figure 35 is a diagram showing self-aligned source/drain implantation along line L-L;

FIG. 36 is a diagram showing salicide formation along line L-L;

FIG. 37 is a diagram showing salicide formation along line L-L.

38 is a diagram showing the situation of filling the recessed source and drain regions with a dielectric material along the line L-L;

39 is a top view and a cross-sectional view along line L-L showing a nitride hardmask used to etch excess bottom gate material;

40 is a top view along line W-W showing a nitride hardmask used to etch excess bottom gate material;

Figure 41 is a diagram showing passivation and planarization of the device using dielectric deposition and CMP along line L-L;

Figure 42 is a diagram showing passivation and planarization of the device using dielectric deposition and CMP along line W-W;

Figure 43 is a diagram showing passivation and planarization of the device using dielectric deposition and CMP along line L-L;

Figure 44 is a diagram showing passivation and planarization of the device using dielectric deposition and CMP along line W-W;

45 is a diagram showing contact hole (via) openings for contacting device sources, drains, and top and bottom gates;

FIG. 46 is a diagram showing contact hole (via) openings for contacting device sources, drains, and top and bottom gates;

Figure 47 is a diagram showing contact hole (via) openings and metal for contacting device sources, drains, and top and bottom gates;

Figure 48 is a diagram showing a partially completed structure of the present invention along line W-W;

Figure 49 is a top view of the structure of the present invention.

Detailed ways

The self-aligned double-gate metal-oxide-semiconductor (DG-MOSFET) with electrically separated top gate and bottom gate of the present invention and its manufacturing method are described below. Also, the top gate and the bottom gate are composed of different materials. As shown in Figures 1-6, the present invention begins with the formation of a series of layers. First, the present invention forms a thin silicon dioxide 1 (eg about 2 nm thick) on a single wafer 5A called a donor wafer. Second, a silicon nitride layer 2 (for example, about 100 nm in thickness) is formed on the silicon dioxide layer 1 . Third, a thick silicon dioxide layer 3 (for example about 400 nm thick) is formed on the nitride layer 2 . Fourth, the crystalline wafer is bonded to the support wafer 4 . The bonding is performed using standard silicon wafer bonding techniques such as boron etch stop, smartcut, and others known to those skilled in the art (for a detailed discussion of bonding techniques, see Jean-Pierre Colinge, Silicon-On - Isulator Technology, 2nd EdKluwer Academic Publishers, 1997, incorporated herein by reference). Then, the SOI layer 5 is formed to the desired thickness of the MOSFET channel. For example, if a flexible dicing technique is used, a thin Si layer is transferred from the surface of the donor wafer 5A to the support wafer 4 . The transferred Si layer is typically bonded to an insulating film such as SiO ₂ , hence the name Silicon-on-Insulator (SOI). The thickness of the transferred SOI film is determined by the depth of hydrogen implantation as part of the flexible dicing technique. Once the SOI film is transferred to the support wafer 4, it can be further thinned by oxidation and lift-off. SOI film thickness is typically monitored using ellipsometry or X-ray diffraction techniques (see GM Cohent et al., Applied Physics Lrtters, 75(6), p. 787, August 1999, incorporated herein by reference).

Then, a thin silicon dioxide layer 6 (about 2 nm) is formed on the SOI layer 5 . A thick silicon nitride layer 7 (eg about 150 nm) is then formed on the silicon dioxide layer 6 .

After completing the first series of layers, the invention etches the two regions 8 into a laminated film. As shown in Figures 7-8, the etch stop (or other similar control structure) is located some distance in the buried oxide (BOX) 3 . The distance between the two regions will become the length (Lg) of the fabricated MOSFET gate.

For purposes of clarity, this disclosure shows the structures and methods of the invention along different hatching lines. For example, Figures 7, 9, 11-18, 20, 21, 23, 25, 27, 29, 31, 33-38, 40, 41, 43, 45 and 47 are cuts along the lines L-L of the structures shown in Figures 8 and 9 An illustration of a top view.

The present invention then begins a series of steps to reshape the etched area. First, as shown in Figures 9 and 10, epitaxial silicon (epi) extensions 9 are selectively grown from a single crystal SOI 5 channel. The epitaxial extension 9 extends to the etched area 8 and grows over the entire periphery of the etched area. The size of the epitaxial extension 9 is preferably about 50 nm. The extension can also be achieved by growing other alloys such as SiGe, SiGeC, or other suitable materials known to those skilled in the art.

Then, the present invention forms sidewall pads 10 on the sidewalls of the etched region 8, as shown in FIG. 11 . This step is accomplished by depositing a dielectric (not included in the figure) over the entire structure. The thickness of the media determines the thickness of the resulting liner 10 . The dielectric can also be a composite (eg sequentially deposited oxide and nitride layers) to provide etch selectivity. In a preferred embodiment, reactive ion etching is used to form sidewall pads 10 . In addition, an isotropic etch (reactive ion etch or wet chemical etch) is performed to remove the residual liner dielectric on the exposed silicon extensions of the SOI trench.

Then, as shown in FIG. 12 , the present invention forms source/drain regions 11 . This step is achieved by first depositing amorphous silicon or polysilicon 11 in the etched area 8 . As shown in FIG. 12, amorphous silicon is deposited until the height of the amorphous silicon is higher than the upper surface of the nitride 7. As shown in FIG. Second, chemical mechanical polishing (CMP) is used to planarize the upper surface. The CMP process mainly removes amorphous Si and is selective to nitride 7. Then, as shown in FIG. 13 , recesses 12 are formed in source/drain regions 11 using reactive ion etching. Finally, as shown in FIG. 14 , a dielectric 13 (such as oxide) is deposited on the depressed region 12 so that the dielectric is completely consistent with the depressed region 12 . Then, the media is planarized by CMP.

In addition, the upper part of the reshaped structure of the present invention is shown in FIG. 15 . First, the upper nitride 7 is removed by wet chemical etching (eg hot phosphoric acid). Second, as shown in FIG. 16, side walls 14 are formed. The sidewalls are obtained by conformally depositing a dielectric over the entire structure and then etching the dielectric to form the sidewalls. The thickness of the medium determines the thickness of the sidewall 14 . Third, wet chemical etching (eg hydrofluoric acid) removes the upper sacrificial pad oxide 6 . Then, on the upper surface of the SOI channel 5, a top gate dielectric 15 is grown, as shown in FIG. 17 . A top gate material 16 (eg, doped polysilicon or tungsten) is conformally deposited to form the gate, as shown in FIG. 18 . Finally, chemical mechanical polishing planarizes the upper surface. The CMP process primarily removes the top gate material using a slurry that is selective to nitride 7 . Then, a mesa hardmask 17 is provided on the structure, as shown in FIGS. 19 and 20 . The mesa hardmask consists of a deposited nitride film preferably 100 nm thick and subsequently patterned. 22, 24, 26, 28, 30, 32, 42, 44, 46 and 48 are all sectional views taken along line W-W shown in FIG.

More specifically, the present invention utilizes a mesa hardmask 17 to isolate devices. The patterning method of this structure is as follows: (1) reactive etch etch (RIE) through the SOI film, stopping at the nitride film, as shown in Figures 21 and 22; (2) on the entire structure, conformally deposit such as Thickness is preferably 75nm low-temperature oxide (LTO) and other medium, and then corrode the medium to form sidewall 18, as shown in Figures 23 and 24; (3) by etching to a certain distance in BOX 3, complete the mesa etching, as shown in Figure 25 and 26. During this process, the sidewalls of the bottom nitride 2 are also exposed.

As shown in FIGS. 27 and 28 , the present invention grows thermal oxide 19 to isolate exposed source and drain sidewalls. Then, as shown in FIGS. 29 and 30 , a wet chemical etch (eg, hot phosphoric acid) removes the bottom nitride 2 and upper nitride hardmask 17 . As a result of removing the bottom nitride 2, tunnels 20 are formed along the width of the device and suspended bridges are formed along the length. In addition, wet chemical etching (eg, hydrofluoric acid) removes the bottom sacrificial pad oxide 1 .

Then, as shown in FIGS. 31 and 32 , the present invention forms the bottom gate 22 . The method of forming the bottom gate 22 is as follows. First, a bottom gate dielectric 21 is formed on the lower surface of the SOI channel 5 . A bottom gate material 22 (eg, doped polysilicon, tungsten, etc.) is conformally deposited to form the bottom gate. Then, CMP planarizes the upper surface. The CMP process primarily removes the bottom gate material, which is selective to LTO.

As shown in Figure 33, etch source/drain cap dielectric LTO 13. Dielectric is deposited conformally over the entire structure forming sidewalls 23 as shown in FIG. 34 . Again, the thickness of the media determines the thickness of the resulting pad. The dielectric is then etched to form the final sidewall structure 23 .

Then, the source/drain region 11 is doped by self-aligned ion implantation 24, thereby heavily doping the silicon 11, as shown in FIG. 35 . For masking the SOI channel region and ion implantation, the top polysilicon gate 16 is used as a self-aligned implant mask. Sidewall pads 23 offset the source/drain implants from the channel region. This implant is followed by a rapid thermal anneal to activate the dopants.

Then, a salicide process is performed to form a silicide 26 on the source/drain and gate 11, as shown in FIG. 37. This step can be performed by any standard process known to those skilled in the art. For example, in silicide fabrication, a metal such as cobalt (Co) or titanium (Ti) is conformally deposited over the entire structure, as shown in Figure 36, and the structure is then heated. After depositing the silicide, a dielectric such as LTO is conformally deposited on the silicide to form an LTO cap 27, as shown in FIG. 38 . This is followed by CMP to planarize the upper surface. The CMP process mainly removes dielectric material 27 , and is selective to silicide 26 and/or gate materials 16 and 22 .

Due to the limited selectivity of the CMP process, some or all of gate silicide 26 may be removed. In this case, the salicide process can be repeated to form a new gate silicide. Then, the bottom gate 22 is completed. First, a nitride or LTO film 27 of preferably about 100 nm is deposited, and then patterned by photolithography to form a hard mask defining the bottom gate region 28, as shown in the top view of FIG. 39 and the cross-sectional view along line L-L in FIG. 40 . Second, the excess bottom gate material is etched down to BOX 3, and a thick passivation dielectric 29 is deposited, as shown in Figures 41 and 42. The upper surface is then planarized using CMP. The CMP process that primarily removes the dielectric material 29 selectively does not remove the nitride hard mask 28 . A second passivation dielectric 30 is then deposited, as shown in FIGS. 43 and 44 .

Then, contact holes 31 are formed on the source and drain 11, and contact holes 32 are etched on the two gates 16, 22 by photolithographic patterning and etching, as shown in FIGS. 45 and 46 . Metal 33 is then deposited and patterned to form electrical contacts to the source, drain and bottom and top gates, as shown in FIGS. 47 and 48 . If the gate length is very short, apply two layers of metal to allow for looser design rules for the top gate contact. Figure 49 is a top view of the completed structure. Certain improvements of the present invention can achieve many advantages over the prior art. First, the present invention deposits the top and bottom gates in two different steps, forming electrically separated top and bottom gates, which yields many advantages. For example, the bottom gate can be used to control the threshold voltage, allowing mixed threshold voltage (Vt) circuits for low power applications.

This structure also enables increased circuit density. A dual-gate MOSFET is a four-terminal device with two input gates when the gates are electrically separated. Therefore, a single device can be used to implement binary logic operations, such as NOR (nFET) or NAND (pFET) cells. Implementation of these binary logic functions typically requires two standard MOSFETs per cell. This increase in circuit density can also be applied to analog circuits, for example, by applying an oscillating voltage to one gate and a signal (data) voltage to the other gate, a mixer can be realized.

Since the present invention grows the top gate, the bottom gate and their respective gate dielectrics separately, each gate and gate dielectric can be made of different materials and have different thicknesses. In addition, different doping concentrations and doping elements can be introduced in each gate. Therefore, an asymmetric grid can be formed. Asymmetric dual-gate MOSFETs are most beneficial for hybrid applications where the gates are used together for speed and two gates are used separately for low power and high density, such as in static random access memory (SRAM).

In addition, the present invention provides a planar structure for easier connection of devices. Devices with very thin channels around 3-5 nm thick may be required to achieve good threshold voltage characteristics. Fabricating suspended silicon bridges with thin layers may reduce overall yield. The present invention supports channels with thick layers 22 . Therefore, the present invention can manufacture devices with very thin channels, and can realize good threshold voltage characteristics of such devices. The present invention also utilizes the self-aligned silicide process that reduces series resistance.

While the invention has been described in connection with a preferred embodiment, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.

Claims (34)

1. A transistor, comprising: channel area; a first gate on top of said channel region; a second gate below the channel region; and source and drain regions adjacent to said channel region; wherein said channel region includes extensions extending into said source and drain regions, wherein said first gate has a material different from said second gate. 2. The transistor of claim 1, wherein said first gate has a different doping concentration than said second gate. 3. The transistor of claim 1, wherein said first gate includes a different dopant species than said second gate. 4. The transistor of claim 1, further comprising a first gate dielectric below said first gate and a second gate dielectric above said second gate. 5. The transistor of claim 1, wherein said first gate has a first conductive contact, said second gate has a second conductive contact, said first conductive contact and said second conductive contact are coplanar. 6. The transistor of claim 1, wherein said first gate has a different thickness than said second gate. 7. The transistor of claim 1, wherein said first gate, said second gate and said channel region form a planarized structure. 8. The transistor of claim 4, wherein said first gate dielectric is of a different material than said second gate dielectric. 9. The transistor of claim 4, wherein said first gate dielectric has a different thickness than said second gate dielectric. 10. A semiconductor chip having at least one transistor, said transistor comprising: channel area; a first gate on top of said channel region; a second gate below the channel region; and source and drain regions adjacent to said channel region; wherein said source region and drain region are self-aligned with said first gate and said second gate, said source region and drain region do not overlap with said first gate and said second gate; and wherein said channel region includes extensions extending into said source and drain regions, wherein said first gate has a material different from said second gate. 11. The semiconductor chip of claim 10, wherein said first gate and said second gate have different dopant concentrations. 12. The semiconductor chip of claim 10, wherein said first gate and said second gate have different dopant species. 13. The semiconductor chip of claim 10, further comprising a first gate dielectric below said first gate and a second gate dielectric above said second gate. 14. The semiconductor chip of claim 13, wherein said first gate dielectric has a material different from that of said second gate dielectric. 15. The semiconductor chip of claim 13, wherein said first gate dielectric has a different thickness than said second gate dielectric. 16. The semiconductor chip of claim 10, wherein said first gate has a first conductive contact, said second gate has a second conductive contact, said first conductive contact and said second conductive contact are coplanar. 17. The semiconductor chip of claim 10, wherein said first gate and said second gate are electrically separated. 18. The semiconductor chip of claim 10, wherein said first gate and said second gate have different thicknesses. 19. The semiconductor chip of claim 10, wherein said first gate, said second gate and said channel region form a planarized structure. 20. A method of fabricating a double gate transistor comprising: forming a stacked structure having a channel layer and insulating layers on upper and lower surfaces of said channel layer; forming an opening in the stacked structure, exposing the insulating layer on the lower surface of the channel layer at the opening; forming drain and source regions in said opening, selectively growing an epitaxial layer from the channel layer, extending into said opening region; removing the insulating layer of the stacked structure on the upper surface of the channel layer, exposing the upper surface of the channel layer; forming a first gate dielectric layer on the channel layer; forming a first gate on the first gate dielectric layer; removing the insulating layer of the stacked structure on the lower surface of the channel layer, exposing the lower surface of the channel layer; forming a second gate dielectric layer on the lower surface of the channel layer; forming a second gate on the second gate dielectric layer; doping the drain and source regions, Wherein the first gate and the second gate are formed separately from each other and have different materials. 21. The method of forming a transistor of claim 20, wherein said first gate has a different doping concentration than said second gate. 22. The method of forming a transistor of claim 20, further comprising doping said first gate and said second gate with different dopants. 23. The method of forming a transistor of claim 20, wherein said first gate dielectric has a different thickness than said second gate dielectric. 24. The method of forming a transistor of claim 20, further comprising forming a first gate oxide below said first gate and forming a second gate oxide above said second gate. 25. The method of forming a transistor of claim 20, wherein said first gate has a first conductive contact, said second gate has a second conductive contact, said first conductive contact and said second conductive contact are coplanar . 26. The method of forming a transistor of claim 20, wherein said first gate has a different thickness than said second gate. 27. The method of forming a transistor of claim 20, wherein said first gate, said second gate and said channel region form a planarized structure. 28. The method of claim 20, wherein said first and second gates are electrically separated. 29. The method of claim 20, wherein said doping of said drain and source regions comprises self-aligned ion implantation. 30. The method of claim 20, wherein said method further comprises forming said first gate to have a thickness greater than that of said second gate. 31. The method of claim 20, wherein said method further comprises forming said first gate to have a width greater than that of said second gate. 32. The method of claim 20, wherein said method further comprises forming said first gate dielectric to have a width greater than that of said second gate dielectric. 33. The method of claim 20, wherein said step of removing a portion of said stacked structure to expose a second portion of said channel layer forms a tunnel in said stacked structure for forming a second portion in a subsequent step. Two gates. 34. The method of claim 20, wherein said first gate dielectric comprises a different material than said second gate dielectric.

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