CN1272855C - Double gated transistor and method of manufacturing the same - Google Patents
Double gated transistor and method of manufacturing the same Download PDFInfo
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- CN1272855C CN1272855C CNB028122984A CN02812298A CN1272855C CN 1272855 C CN1272855 C CN 1272855C CN B028122984 A CNB028122984 A CN B028122984A CN 02812298 A CN02812298 A CN 02812298A CN 1272855 C CN1272855 C CN 1272855C
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a trThe preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved.ansistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and -0.5V for pFETs.
Description
Technical field
The present invention relates generally to field of semiconductor manufacture, and relates to a kind of method that forms FET dual gate more especially.
Background technology
In the manufacturing of semiconductor device, caused the sustainable growth of device density in the integrated circuit for the emulative needs that keep cost and performance.In order to promote the growth of device density, need new technology to reduce the characteristic size of these semiconductor device all the time.
In the CMOS technology,, strong especially for the ever-increasing promotion of device density such as in the design and manufacturing of field-effect transistor (FET).FET just is being applied in the integrated circuit (IC) design of nearly all type (that is, microprocessor, memory etc.).Unfortunately, the device density that increases among the CMOS FET causes the deterioration of performance and/or reliability usually.
One type the FET that has put forward to be used to promote device density to increase is a FET dual gate.FET uses Last two grids of each side of matrix, and the size of helping dwindle CMOS keeps acceptable performance simultaneously.Particularly, two grid use has increased gate area, and it makes transistor have better Current Control, and does not increase the grid length of device.Similarly, FET can have the more Current Control of megacryst pipe, and need not to take this more device space of megacryst pipe.
Unfortunately, in the transistorized design of dual gate cmos and in making several difficulties have appearred.At first, the relative size of double gate transistor makes and is difficult to stably make the transistor with unfailing performance and minimum feature size dimensions.The second, the threshold voltage of double gate transistor depends on the material as these two grids largely.Particularly, present manufacturing technology generally can produce the double gate transistor that had high threshold voltage or crossed low threshold voltage.For example, if use the polarity doping grid identical with source electrode, then threshold voltage approaches zero usually.On the contrary, if use the polarity doping grid opposite with source electrode, then threshold voltage will approach 1 volt.It is desired during most of CMOS use not having a kind of result.
Therefore, produced the needs for device architecture that improves and manufacturing dual gate cmos device method, it can provide the threshold voltage of improvement for the dual gate cmos of gained, and does not excessively increase the complexity of making.
Summary of the invention
Therefore, the invention provides a kind of double gate transistor and manufacture method thereof, it has produced device performance and the density improved.The preferred embodiments of the present invention are that double gate transistor is provided with the asymmetric gate doping, and wherein in the bigrid is doped to the n type diminuendo, and another is the p type.By being doped to the n type with one in the grid, another is doped to the p type, the threshold voltage of obtained device is improved.Particularly, by two grids that asymmetricly mix, the transistor of gained can have the threshold voltage ranges that can carry out low voltage CMOS work under the situation that matrix suitably mixes.For example, can form for the nFET threshold voltage between the 0V to 0.5V and for the transistor of pFET threshold voltage between 0 to-0.5V.
The preferred embodiments of the present invention utilize the fin-type double-grid structure to realize.In the fin-type structure, bigrid is formed on each side of matrix, and matrix is flatly between grid.The method for optimizing that is used to form this double gate transistor allows the grid length of device to have minimum characteristic size, allows the thickness of matrix more much smaller than grid length simultaneously.This has improved the control to the obtained device threshold voltage.By using image enhancement technique, the method for optimizing that is used to form double gate transistor is finished sidewall image transfer, thereby limits the thickness of semiconductor body, allows its following minimum feature size to form reliably.
The invention provides a kind of method that forms field-effect transistor, the method comprising the steps of: the Silicon-On-Insulator substrate a) is set, and the Silicon-On-Insulator substrate comprises the silicon layer on the dielectric layer of imbedding; B) on silicon layer, form sandwich layer; Thereby the composition sandwich layer limits the sandwich layer edge; C), the composition of silicon layer is provided with first matrix border with sandwich layer edge composition silicon layer; D) on first matrix border, form the first grid dielectric; E) on the first grid dielectric, be close to the first grid structure that first matrix border is provided with first Fermi level; F) thus the composition sandwich layer exposes first edge of first grid structure; G) first edge that is close to the first grid structure forms lateral wall bulkhead, and lateral wall bulkhead has first edge and second edge; H) with the second edge composition silicon layer of lateral wall bulkhead, the composition of silicon layer is provided with second matrix border, wherein first and second matrix borders of the silicon layer crossed of composition define semiconductor body; I) the second grid dielectric is set on second matrix border; And j) on the second grid dielectric, is close to the second grid structure that second matrix is provided with second Fermi level.
Aforementioned and other advantage of the present invention and feature will by below in conjunction with shown in the accompanying drawing, preferred embodiment of the present invention more specific description become to be become apparent.
Description of drawings
Introduce preferred exemplary embodiments of the present invention below in conjunction with accompanying drawing, wherein identical Reference numeral is represented components identical, and wherein:
Fig. 1 is the flow chart that first kind of manufacture method is shown;
Fig. 2 to 10 is for during making, the side cross-sectional view of typical double gate transistor;
Figure 11 to 15 is for during making, the perspective view of typical double gate transistor;
Figure 16 is the flow chart that second kind of manufacture method is shown;
Figure 17 to 24 is for during making, the side cross-sectional view of second kind of typical double gate transistor; And
Figure 25 is the curve chart of threshold voltage to matrix thickness.
Embodiment
Therefore, the invention provides a kind of double gate transistor and manufacture method thereof, this double gate transistor provides device performance and the density improved.The preferred embodiment of the present invention provides has the double gate transistor that asymmetric gate is mixed, and wherein in this bigrid is doped to the n type diminuendo, and another then is the p type of diminuendo.By being doped to the n type with one in the grid, and another is doped to the p type, the threshold voltage of obtained device improves.Particularly, by two grids that asymmetricly mix, the transistor of gained can have the threshold voltage in the scope that can carry out the low voltage CMOS operation under the situation of the matrix that suitably mixes.For example, but shape then has the transistor of 0V to the threshold voltage of-0.5V for the threshold voltage that nFET has between the 0V to 0.5V for pFET.
The preferred embodiments of the present invention utilize fin-type (fin type) double-grid structure to realize.In the fin-type structure, bigrid is formed on each side of matrix, and matrix is in the horizontal direction between grid.The method for optimizing that is used to form this double gate transistor allows the grid length of device to have minimum feature size, allows the thickness of matrix more much smaller than grid length simultaneously.This has improved the control to the threshold voltage of obtained device.By using image enhancement technique (image enhancement technique), the method for optimizing that is used to form double gate transistor is finished sidewall image transfer (sidewall image transfer), thereby limit the thickness of semiconductor body, allow its following minimum feature size (sub minimum feature size) to form reliably.
Multiple electric conducting material is associated with The built-in electromotive force (so-called Fermi level), and built-in electromotive force has been determined the relative affinity of conductor for electronics (or hole) together with applied voltage.In metal, Fermi level is intrinsic for material, and in semiconductor (for example silicon), and this Fermi level can provide the impurity of unnecessary hole or electronics to be adjusted into value between valence band and the conduction band by introducing.In the asymmetric double gated FET of preferred embodiment, two gate electrodes are doped to opposite polarity, and a grid doping is the n type, and another grid then is doped to the p type.Therefore, two gate electrodes have different Fermi levels, and gate electrode (strong grid thus, for nFET, be the n grid) have stronger affinity for being inverted charge carrier (inversion carrier), and another grid (weak grid is the p grid for nFET) has more weak affinity for being inverted charge carrier.As a result, inversion channel will be formed on more in the semiconductor substrate near " by force " gate location place, and make two gate electrodes all produce contribution to being inverted electromotive force, thereby cause relatively low threshold voltage (for example, between 0 to 0.5 volt).
Referring now to Fig. 1, the method 100 that is used to form according to the double gate transistor of preferred embodiment is described.Method 100 keeps the reliability made and the mode of simplicity to form double gate transistor according to improving transistorized threshold voltage simultaneously.
The first step 101 of method 100 deposits each etching stopping layer for suitable wafer to be set, and deposition sandwich layer (mandrel layer).In a preferred embodiment, employed wafer comprises Silicon-On-Insulator (SOI:silicon on insulator) wafer.Similarly, this wafer comprises the oxide layer of imbedding under the soi layer.For clarity sake, use soi layer to form the matrix of double gate transistor.Similarly, preferred usually the use has p type (for NFET) doping content 3 * 10
18Cm
-3To 8 * 10
18Cm
-3SOI in the scope is to provide good transistor threshold voltage centralized positioning and control.Yet among another embodiment that will introduce below, the doping of soi layer utilizes angled injection (angled implant) to finish, so that realize uniform concentration on whole substrate.
Yet, also can use non-SOI wafer.When using non-SOI wafer, remove dated, remaining PROCESS FOR TREATMENT is consistent with the situation of SOI wafer.
For the situation that the SOI wafer is provided, on wafer, form three layers of etching stopping layer, preferably include silicon dioxide layer, silicon nitride layer and second layer silicon oxide layer.Run through during the manufacturing process, when the suitable etching of needs stops, will utilizing these etching stopping layers.
Then, form sandwich layer.Sandwich layer preferably includes the layer of oxide or other suitable material.As will be in the back introducing more in detail, sandwich layer is a part that is used to limit the sidewall image transfer of double gate transistor matrix.Therefore, sandwich layer is used to form lateral wall bulkhead (sidewall spacer), and it is used to limit semiconductor body subsequently.In a preferred embodiment, sandwich layer has the thickness between 10nm and the 100nm, yet this thickness can change according to desired matrix thickness.
Referring now to Fig. 2, it shows the wafer part 200 behind formation etching stopping layer and the sandwich layer.The wafer part 200 of preferred embodiment comprises the SOI wafer, and comprises soi layer 202 therefrom and imbed oxide layer 204.On the soi layer top, form oxide layer 206, nitration case 208 and oxide layer 210.These layers play etching stopping layer.On the top of oxide layer 210, form sandwich layer 212.
Get back to Fig. 1, following step 102 stops layer for composition sandwich layer, formation lateral wall bulkhead and patterned etch.Sandwich layer is patterned to open one the zone that wherein will form in the bigrid.Lateral wall bulkhead is preferably by deposited silicon nitride, then carries out suitable directional etch and forms.As follows, the thickness of lateral wall bulkhead will limit the matrix region of double gate transistor with sidewall image transfer.
With reference to Fig. 3, it shows composition sandwich layer 212, the wafer part 200 after forming lateral wall bulkhead 214 and removing the expose portion of etching stopping layer.
Get back to Fig. 1, following step 104 is come the composition soi layer for the core material that uses lateral wall bulkhead and reservation as mask, and forms gate oxide on the side that soi layer exposes.This preferably uses suitable reactive ion etching to finish.Gate oxide preferably forms by thermal oxidation (general under 750 to 800 ℃ temperature).In addition, during this step, can finish the injection in semiconductor body.This will be preferably included in and form the angled injection of finishing before the gate oxide in the exposed sidewalls of soi layer.This will help through the suitable doping to semiconductor body.As be described in greater detail below, this angled injection can be carried out according to the mode that realizes uniform concentration, thereby helps to compensate variations in threshold voltage.
Referring now to Fig. 4, it shows composition soi layer 202 and the wafer part 200 after the formation gate oxide 216 on the side of soi layer 202.Again, can also carry out angled matrix before forming gate oxide injects.
Get back to Fig. 1, following step 106 is deposition and leveling grid material.As mentioned above, in a preferred embodiment, a grid of double gate transistor forms n
+And another grid forms p
+Shown in injection, at first form n
+Grid.With reference to Fig. 5, it shows deposition and leveling n
+Wafer part 200 behind the polysilicon 218.For clarity sake, n
+Polysilicon 218 will be used to form in the grid in the double gate transistor preferred embodiment.
The sandwich layer of following step 108 for optionally going to keep.This preferably has optionally the sandwich layer reactive ion etching to nitride sidewall spacers wall, nitride etch stop layer and grid polycrystalline silicon and finishes by carrying out.Then, on the polysilicon gate material,, form intermediate oxide layer preferably by the thermal oxide of on polysilicon gate, growing.Referring now to Fig. 6, it shows and remove sandwich layer 212, removes, and oxide etching stops layer 210 and the wafer part 200 after the formation thermal oxide layer 220 on grid polycrystalline silicon 218.With oxide 220 nitration case 208 under the sandwich layer that keeps of etching optionally, then, carry out of short duration HF etching, be positioned at the remaining oxide layer 206 under the sandwich layer of reservation with removal.
Following step 110 is the soi layer of etch exposed.This preferably finishes by using the etching soi layer and stopping at the reactive ion etching of imbedding on the oxide layer.So just finish the composition of soi layer, thereby defined the thickness of double gate transistor matrix.On the side that semiconductor body exposes, form gate oxide then.
In addition, during this step, can carry out another time injection in semiconductor body.This will be preferably included in the sidewall that exposes to soi layer before the formation gate oxide once more and be carried out to the angle injection.
With reference to Fig. 7, it shows the wafer part 200 after the composition soi layer 202.The reserve part of soi layer 202 comprises the matrix of double gate transistor.Gate oxide 221 utilizes thermal oxidation or is formed on by the deposit dielectric film on the soi layer 202 of exposure.
When using non-SOI wafer, at the etching silicon fin to the degree of depth (be generally under the initial silicon surface 100 to 200nm) of expectation, utilize the technology of deposition/etching oxide to come deposition of silica, remove the bottom level surface at etched silicon, thickness is near one and one-quarter of the fin height that etches.Oxide available boron under the situation of nFET mixes, and perhaps available phosphorus doping under the situation of pFET, and part dopant spreads outward in the part fin of next-door neighbour's doping oxide.This has played the effect that suppresses to become the leakage from source electrode to drain electrode that will occur in the non-grid surface of fin.
Get back to the embodiment of SOI, it should be noted, the composition of soi layer defines the matrix of double gate transistor.Usually expect to have to compare very narrow matrix thickness, as T with grid length
SIShown in.Usually, matrix thickness will be controlled thereby provide good threshold voltage less than one and one-quarter of grid length.In addition, expect that usually matrix thickness should be greater than 2.5nm, thereby avoid because the mobility that quantum limitation effect causes descends.Because grid length is made minimum feature size usually, therefore use sidewall image transfer to realize the inferior minimum feature size of matrix.Thus, as shown abovely go out and illustrate that the width of lateral wall bulkhead has been determined matrix thickness.
Following step 112 is used for the grid material of second grid for deposition and leveling.As mentioned above, preferred embodiment adopts the grid material of phase contra-doping to form two grids.Therefore, preferred embodiment adopts p
+The polysilicon that mixes forms second in two grids.p
+The leveling of polysilicon gate material stops at and is pre-formed at n
+On the thermal growth oxide on the polysilicon gate.Leveling p
+Behind the polysilicon gate material, form second layer thermal growth oxide.Referring now to Fig. 8, it shows deposition and leveling p
+Thereby the polysilicon that mixes 226 forms the wafer part 202 behind the second grid.Thermal growth oxide 228 is formed on the polysilicon 226 that is deposited subsequently.
Following step 114 is for removing lateral wall bulkhead, and with intrinsic polysilicon filled sidewall spaced walls, thereby the silicide that forms in this zone after a while in the technology is maximized.Optionally, obtain separation, independently grid contact as expectation, then lateral wall bulkhead can suitably keep.Then, use CMP method leveling intrinsic polysilicon, CMP technology stops on the two-layer thermal growth oxide.This planarization process need not the selectivity of height, and this is because only very a spot of unnecessary intrinsic polysilicon will be removed.Then, utilize similar planarization process to remove exposure thermal growth oxide on two grids.Again, this handles the selectivity that step need not height.Referring now to Fig. 9, it shows the reserve part of removing lateral wall bulkhead 214, and subsequently with the wafer part 220 behind the intrinsic polysilicon 230 filling spaces.Figure 10 shows subsequently by CMP and removes unnecessary polysilicon 230 and thermal growth oxide 220 and 228 wafer part 200 afterwards.This will only keep fraction intrinsic polysilicon 230 in the position of the initial lateral wall bulkhead that forms.This part intrinsic polysilicon 230 will be used for the subsequent technique flow process and connect p
+With n
+The formation of the silication bridge of polysilicon gate (silicide bridge).
Get back to method 100, following step 116 is the composition grid.This comprises the part of optionally removing grid material adjacent transistors source electrode and drain region.It preferably utilizes the photoetching technique of standard to finish, for example the deposition and the hard mask of composition, and subsequently during the etching grid material the hard mask with etching stop as etching.Hard mask is preferably nitride hardmask, as the etching stopping layer that is formed on the matrix.
Referring now to Figure 11, its form with perspective shows wafer part 200.Nitride hardmask 232 strides across two grids and is formed extended at both sides, and these two grids comprise n
+Grid polycrystalline silicon 218 and p
+Grid polycrystalline silicon 226.Referring now to Figure 12, it shows utilization hard mask is had optionally etching composition grid polycrystalline silicon 218 and grid polycrystalline silicon 226 wafer part 200 afterwards.Composition has preferably been removed downwards until all grid polycrystalline silicons of imbedding oxide layer 204.The composition of grid preferably uses to has optionally directional etch to nitride and finishes.Thus, composition is not removed the part of SOI matrix 202 by the previous nitride etch stop layer that forms 208 protections.Composition has stayed the n of part
+Polysilicon 218 and p
+Polysilicon 226, it defines two grids of double gate transistor.
In a preferred embodiment, carrying out buffered HF and clean, then is to be designed for that the used heat of grow oxide reoxidizes on all exposed silicon surface.It has been preferably formed the thin-oxide film of 50 dusts, when this film contacts with matrix at grid, provides good interface.
Following step 118 is for forming source electrode, drain electrode and the ring injection region in the transistor in the method 100.Preferred these injections are all carried out all four directions of matrix, produce uniformly with the both sides of guaranteeing matrix and inject.Particularly, the injection of source electrode and drain electrode all is to carry out from the source electrode of matrix and the side of drain electrode part.Then, carry out another time injection, thereby form the ring injection region (halo implant) that to improve short-channel effect with different injection energy and angle.Ring is infused under the higher energy and with the angle sharper with respect to fin and carries out, and is provided with to such an extent that be in the more following position of gate electrode than source/drain impurity thereby guarantee to encircle impurity.For nFET, usually in 1 to 5keV scope, 5 * 10
14To 2 * 10
15Cm
-3Dosage under, inject to become angle between 75 ° to 80 ° that arsenic is used for source/drain with respect to fin, and with the boron of energy in 5 to 15keV scopes, with 1 * 10
13 to 8 * 10
13Cm
-3Dosage be used for ring and inject, ring is oriented between 20 ° to 30 ° with respect to fin.Similarly, for pFET, usually in 0.5 to 3keV scope, 5 * 10
14To 2 * 10
15Cm
-3Dosage under, inject to become angle between 75 ° to 80 ° that boron is used for source/drain with respect to fin, and with the arsenic of energy in 20 to 45keV scopes, with 1 * 10
13To 8 * 10
13Cm
-3Dosage be used for ring and inject, ring is oriented between 20 ° to 30 ° with respect to fin.In addition, all above-mentioned injections must become suitable angle with the wafer orientation angle, become the angle between 7 ° to 30 ° usually with wafer orientation.
Following step 120 is the gate electrode of deposition rate combination and the thicker dielectric of height of the hard mask on the BOX, cover the fin of whole gate electrode and exposure, leveling is also partly caved in until the hard mask and the gate electrode of (being generally 10 to 50nm) that expose part, but does not expose any part in source/drain fin zone.For the sake of clarity, this step is the part of formation of the lateral wall bulkhead of transistor gate edge part office.Employed dielectric preferably includes oxide, and it can be had optionally etching to established nitride hardmask.Referring now to Figure 13, it shows around transistor gate electrodes deposition, leveling dielectric 240, and forms the wafer part 200 after the depression.Dielectric preferably utilizes the nitride hardmask 232 for previous setting to have optionally, and directional etch caves in.
Following step 122 is for forming lateral wall bulkhead and etching deposits dielectric in advance on the edge of grid.This preferably utilizes the conformal deposit of dielectric material, then finishes by directional etch.Lateral wall bulkhead is preferably formed by nitride.The nitride sidewall spacers wall can be used for covering directional etch subsequently together with nitride hardmask, and removes the oxide except that adjacent gate thus.
Referring now to Figure 14, it shows and forms nitride sidewall spacers wall 242, and etches away dielectric 240, only keeps the wafer part 200 behind the sidewall sections 244 of adjacent transistors grid.Hard mask 232, lateral wall bulkhead 242 and sidewall sections 244 combine, and keep apart thereby effectively grid is contacted with drain electrode from the source electrode that forms subsequently.
Following step 124 contacts with drain electrode for forming source electrode.This preferably finishes by filling the zone that before had been removed with contact material.Contact material is depositing silicon, tungsten or other electric conducting material optionally, itself and n
+And/or p
+Silicon forms low resistance contact.If use silicon, then it is doped to n respectively diminuendo for nFET or pFET
+Or p
+This material can deposit until its cover wafers to the height more than the height of nitride hardmask, and subsequently by RIE and/or chemico-mechanical polishing leveling, comes out fully until nitride hardmask.Then, as shown in figure 15, utilize the mask patterned wafers, it is used for the unnecessary part of etching source/drain contact material, thereby both source electrode and drain electrode is kept apart, and again a plurality of FET is isolated from each other.At last, (for example can pass through RIE or other etching technique, hot phosphoric acid) optionally remove hard mask, and on grid (, then being in source electrode and drain electrode) deposition and form metal silicide at the metal of about 700 ℃ of following sintering such as cobalts or titanium for silicon contact.
Referring now to Figure 16, it shows another preferred embodiment method 300.Because spaced walls only is exposed to reactive ion etching once at present, therefore, the method has being used to limit the minimum advantage that corrodes of lateral wall bulkhead generation of semiconductor body.Therefore, the silicon etch profile of this embodiment acquisition has obtained good control.In step 301, ground prepares wafer, forms etching stopping layer and sandwich layer as in the step 101 of above-mentioned method 100.Then, in step 302, composition sandwich layer, and direct those etching stopping layers of etching.This and method 100 are different from, and do not form lateral wall bulkhead before patterned etch stops layer on sandwich layer.With reference to Figure 17, it shows and forms etching stopping layer, sandwich layer, and the wafer part 200 after direct etching sandwich layer and the etching stopping layer.
Following step 304 is to use the sandwich layer that keeps as mask composition soi layer, and forms gate oxide on the side that soi layer exposes.This is the reactive ion etching by use being fit to preferably, then deposits by the thermal oxidation between 750 ℃ and 800 ℃ usually or by CVD and finishes such as the high k material of aluminium oxide.In addition, during this step, can finish the injection in semiconductor body.This will be preferably included in and form before the gate oxide, finish the angled injection of carrying out in the sidewall that soi layer exposes.This injection will help through the suitable doping of semiconductor body.As introducing more in detail below, this injection can be carried out according to the mode that realizes uniform concentration, thereby helps to compensate variations in threshold voltage, and this variation results from the variation of matrix thickness.
Referring now to Figure 18, it shows composition soi layer 202 and the wafer part 200 after the formation gate oxide 216 on the side of soi layer 202.Again, can also carry out angled matrix before forming gate oxide injects.
Get back to Figure 16, following step 306 is deposition and leveling grid material.As mentioned above, in a preferred embodiment, a grid of double gate transistor forms n
+And another grid forms p
+In an illustrated embodiment, at first form n
+Grid.With reference to Figure 19, it shows deposition and leveling n
+Wafer part 200 behind the polysilicon 218.For clarity sake, n
+Polysilicon will be used to form in the grid of double gate transistor preferred embodiment.
Following step 308 along the edge formation lateral wall bulkhead of the first grid material that keeps, and forms intermediate oxide layer for removing the core material that keeps on the polysilicon gate material.Intermediate oxide layer forms by growth thermal oxide on polysilicon gate.Referring now to Figure 20, it shows removes sandwich layer 212, the wafer part 200 after forming lateral wall bulkhead 302 on the first grid material sidewall and form thermal oxide layer 220 on grid polycrystalline silicon 218.With oxide 220 nitration case 208 under the remaining sandwich layer of etching optionally, then, remove remaining oxide layer 206 under the remaining sandwich layer by of short duration HF etching.
Following step 310 is the soi layer of etch exposed.This preferably finishes by using the etching soi layer and stopping at the reactive ion etching of imbedding on the oxide layer.So just finish the composition of soi layer, thereby defined the thickness of double gate transistor matrix.On the side that semiconductor body exposes, form gate oxide then.Again, during this step, can carry out injection in semiconductor body.This will be preferably included in again and form before the gate oxide, and the sidewall that exposes to soi layer carries out angled injection.
Referring now to Figure 21, it shows the wafer part 200 behind the composition soi layer 202.The reserve part of soi layer 202 comprises the matrix of double gate transistor.Gate oxide 221 utilizes thermal oxidation or deposit dielectric film and is formed on the soi layer 202 of exposure.
Following step 312 is used for the grid material of second grid for deposition and leveling.As mentioned above, preferred embodiment uses the grid material of phase contra-doping to form two grids.Thus, preferred embodiment uses p
+The polysilicon that mixes forms second in two grids.To p
+The leveling of polysilicon gate material stops at and is pre-formed at n
+On the thermal growth oxide on the polysilicon gate.Leveling p
+Behind the polysilicon, form second layer thermal growth oxide.Referring now to Figure 22, it shows deposition and leveling p
+Thereby the polysilicon that mixes 226 forms the wafer part 202 behind the second grid.Thermal growth oxide 228 is formed on the polysilicon 226 of deposition subsequently.
Following step 314 is for removing lateral wall bulkhead, and with intrinsic polysilicon filled sidewall spaced walls opening, thereby the silicide that forms in this zone after a while in the technology is maximized.Optionally, obtain separation, independently grid contact as expectation, then lateral wall bulkhead can suitably keep.Then, use CMP method leveling intrinsic polysilicon, CMP technology stops on the two-layer thermal growth oxide.This planarization process need not the selectivity of height, and this is because only very a spot of unnecessary intrinsic polysilicon will be removed.Then, utilize similar planarization process to remove exposure thermal growth oxide on two grids.Again, this handles the selectivity that step need not height.Referring now to Figure 23, it shows the reserve part of removing lateral wall bulkhead 302, and subsequently with the wafer part 200 behind the intrinsic polysilicon 230 filling spaces.Figure 24 shows subsequently by CMP and removes unnecessary polysilicon 230 and thermal growth oxide 220 and 228 wafer part 200 afterwards.This will only keep fraction intrinsic polysilicon 230 in the position of the initial lateral wall bulkhead that forms.This part intrinsic polysilicon 230 will be used for the subsequent technique flow process and connect p
+With n
+The formation of the silication bridge of polysilicon gate.
Get back to method 300, remaining step 316 to 326 with method 100 in the step 116 introduced to 126 consistent.Again, method 300 has to the minimum advantage that corrodes of the generation of the lateral wall bulkhead that is used to limit semiconductor body, because spaced walls only is exposed to reactive ion etching once now.Therefore, the silicon etch profile of this embodiment acquisition has obtained good control.
In another embodiment of the present invention, adopt some steps to compensate usually the variations in threshold voltage that the variation owing to matrix thickness produces.Particularly, threshold voltage depends on the thickness of matrix at least in part.As mentioned above, the thickness of matrix is mainly determined by the thickness of the lateral wall bulkhead that is used to limit matrix during sidewall image transfer.Usually, be used to form some variation that the technology of lateral wall bulkhead can produce the sidewall spacers wall thickness.Similarly, also can there be some variation in the threshold voltage of obtained device.Under many circumstances, this variations in threshold voltage will be in the scope that can tolerate.Yet in some cases, expectation compensates these variations.
In this embodiment, matrix is mixed uniformly, with the difference of compensation thickness.In this embodiment, be desirably in usually all to produce on three dimensions uniformly and mix, opposite with the doping way that produces the even impurity level that density changes along with matrix thickness.This finishes by carrying out the injection that produces fixing, uniform impurity concentration in matrix.Preferably, this finishes by carrying out angled several times injection during thin revealing in a side of matrix in matrix.For example, when a side of matrix exposes (as shown in Figure 4) can inject, and when opposite side exposes (as shown in Figure 7) carry out the injection second time.For example, can realize that to inject uniform fin mixes by just before gate oxidation with respect to angle of inclination (tilting 40 ° with respect to vertical fins therefrom) exposed sidewalls of silicon in Fig. 4 of 45 ° of wafer surface.Will be with the dosage that changes, use injection that a series of energy carries out to form the uniform foreign atom mode of (as shown in figure 25) of distributing to be used in combination according to the width that runs through fin, wherein respectively with the energy of 0.6keV, 1.2keV, 2.4keV and 9.6keV with boron according to 2.1,4.4,9.3,19.5 and 40.8 * 10
12Atom/cm
2Dosage be injected in the sidewall silicon.
In another approach, this uniform concentration is to form by carried out vertical injection before forming etching stopping layer and sandwich layer.When carrying out this injection, then carry out large tracts of land annealing, realized basic doping content uniformly thus.In addition, can realize this uniformity with repeatedly vertically injecting.
In all these embodiment, pFET and nFET need distinguish masked and inject, and wherein phosphorus or arsenic are used for pFET and boron is used for nFET.
The threshold voltage that matrix is doped to the asymmetric double gated FET of Na is provided approx by following formula:
Wherein, ε
SiBe the dielectric constant of silicon, Eg is the band-gap energy (≈ 1.1eV) of silicon, T
SiBe matrix thickness, λ is for being inverted the degree of depth (≈ 1nm) of the electric charge barycenter (charge centroid) of layer, Q in subsurface silicon substrate of contiguous strong grid
eBe electron charge, N
ABe the doping content of matrix (or fin), φ
MsGate electrode is with respect to the Fermi level of being inverted layer when forming, and ε
OxBe the dielectric constant of gate-dielectric, Toxs is that the gate electrode that has the stronger Fermi level of the charge carrier attraction of inversion channel (is n in nFET
+Electrode is p in pFET
+The thickness of insulator electrode), and Toxw is that the gate electrode that has the more weak Fermi level of the charge carrier attraction of inversion channel (is p in nFET
+Electrode is n in pFET
+The thickness of insulator electrode).This equation can show from mathematics, and to mixing, i.e. the selection of Na is that equation is differentiated to Na, solves under this condition, and consequent reduction has then provided the Vt for the doping relative insensitivity.Obviously, be chosen as approximate during as matrix doping Na as equation 2:
Then, Vt will be for the variation relative insensitivity in the silicon substrate thickness.
By in matrix, carrying out angled several times injection, carry out several times and vertically inject, or use large tracts of land annealing, will realize more uniform concentration of dopant.No matter how and have uniform concentration and will produce different total doping for different thickness matrix thickness.For example, when setting up uniform doping content, thicker matrix has the relatively thinner bigger total doping of matrix.The change of doping has compensated the difference of matrix thickness, and produces lower threshold voltage variation, and it occurs along with the variation of matrix thickness usually.With reference to Figure 25, it shows for rectangle, non-compensation double gate transistor and the double gate transistor by providing more uniform doping content to compensate threshold voltage variation, threshold voltage (V
T) to matrix thickness (T
SI) view.
As shown in the figure, the threshold voltage of the double gate transistor that matrix evenly mixes as the function of matrix thickness, shows littler variation.Thus, the uniform concentration of matrix mix to help to have compensated and will obviously influence the variation of the matrix thickness of threshold voltage usually.
Thus, the invention provides a kind of double gate transistor and manufacture method thereof, it has produced device performance and the density improved.The preferred embodiments of the present invention are mixed for double gate transistor provides asymmetric gate, and wherein in the bigrid is doped to the n type diminuendo, and another is doped to the p type diminuendo.By being doped to the n type with one in the grid, another is doped to the p type, the threshold voltage of obtained device is improved.Particularly, by two grids that asymmetricly mix, the transistor of gained can have the threshold voltage ranges that can carry out low voltage CMOS work under the situation that matrix suitably mixes.
Though with reference to exemplary embodiments, use fin-type FET dual gate is demonstrated particularly and has been introduced the present invention, those skilled in the art will recognize that, preferred embodiment can be applied on the double gate transistor of other type, and the variation on the implementation detail can be carried out under the situation that does not break away from the spirit and scope of the invention.For example, those skilled in the art also will understand, and the present invention can be applicable to different isolation technology (for example, LOCOS, concealed oxide (ROX:recessed oxide) or the like), trap and substrate technology, dopant type, energy and kind.It will also be understood that essence of the present invention can be applicable to other semiconductor technology (for example, BICMOS, bipolar, Silicon-On-Insulator (SOI), germanium silicon (SiGe)).
Claims (26)
1. method that forms field-effect transistor, the method comprising the steps of:
A) the Silicon-On-Insulator substrate is set, the Silicon-On-Insulator substrate comprises the silicon layer on the dielectric layer of imbedding;
B) on silicon layer, form sandwich layer; Thereby the composition sandwich layer limits the sandwich layer edge;
C), the composition of silicon layer is provided with first matrix border with sandwich layer edge composition silicon layer;
D) on first matrix border, form the first grid dielectric;
E) on the first grid dielectric, be close to the first grid structure that first matrix border is provided with first Fermi level;
F) thus the composition sandwich layer exposes first edge of first grid structure;
G) first edge that is close to the first grid structure forms lateral wall bulkhead, and lateral wall bulkhead has first edge and second edge;
H) with the second edge composition silicon layer of lateral wall bulkhead, the composition of silicon layer is provided with second matrix border, wherein first and second matrix borders of the silicon layer crossed of composition define semiconductor body;
I) the second grid dielectric is set on second matrix border; And
J) on the second grid dielectric, be close to the second grid structure that second matrix is provided with second Fermi level.
2. the method for claim 1, wherein the first grid structure of first Fermi level comprises p type polycrystalline silicon material, and wherein the second grid structure of second Fermi level comprises n type polycrystalline silicon material.
3. the method for claim 1, wherein the first grid structure of first Fermi level comprises n type polycrystalline silicon material, and wherein the second grid structure of second Fermi level comprises p type polycrystalline silicon material.
4. the method for claim 1 also comprises by carry out the angled step that forms the source/drain injection region in the transistorized matrix that is infused in semiconductor body.
5. the method for claim 1, the step that wherein forms lateral wall bulkhead is included in and forms sidewall oxide in the lateral wall bulkhead groove, forms nitration case on described sidewall oxide, and fills described lateral wall bulkhead groove with oxidate.
6. the method for claim 1 also is included in the step that forms uniform concentration of dopant in the semiconductor body.
7. method as claimed in claim 6, the step that wherein forms uniform concentration of dopant in semiconductor body comprise carries out repeatedly angled injection in matrix.
8. method as claimed in claim 6, the step that wherein forms uniform concentration of dopant in semiconductor body is included in carries out angled injection for the first time when exposing first matrix border, and carries out angled injection for the second time when exposing second matrix border.
9. method as claimed in claim 8, wherein angled injection for the first time comprises with the angle injection at 45 with respect to the Silicon-On-Insulator substrate, and wherein angled injection for the second time comprises with the angle injection at 45 with respect to the Silicon-On-Insulator substrate.
10. method that forms field-effect transistor, the method comprising the steps of:
A) the Silicon-On-Insulator substrate is set, the Silicon-On-Insulator substrate comprises the silicon layer on the dielectric layer of imbedding;
B) on silicon layer, form sandwich layer; Thereby the composition sandwich layer limits the sandwich layer edge;
C), the composition of silicon layer is provided with first matrix border with sandwich layer edge composition silicon layer;
D) on first matrix border, form the first grid dielectric;
E) on the first grid dielectric, be close to the first grid structure that first matrix border is provided with first Fermi level;
F) thus the composition sandwich layer exposes first edge of first grid structure;
H) composition to silicon layer provides second matrix border, and wherein first and second matrix borders of the silicon layer crossed of composition define semiconductor body;
I) the second grid dielectric is set on second matrix border; And
J) on the second grid dielectric, be close to the second grid structure that second matrix is provided with second Fermi level.
11. a field-effect transistor comprises:
A) be formed on semiconductor body on the substrate, semiconductor body has first vertical edge and second vertical edge;
B) the first grid structure of adjacent transistors matrix first vertical edge, the first grid structure has first Fermi level; And
C) the second grid structure of adjacent transistors matrix second vertical edge, the second grid structure has second Fermi level.
12. transistor as claimed in claim 11, wherein the first grid structure comprises p section bar material, and wherein the second grid structure comprises n section bar material.
13. transistor as claimed in claim 11, wherein the first grid structure comprises n section bar material, and wherein the second grid structure comprises p section bar material.
14. transistor as claimed in claim 11, wherein semiconductor body comprises the SI semi-insulation silicon layer.
15. transistor as claimed in claim 11, wherein first and second grid structures comprise polysilicon.
16. transistor as claimed in claim 11 also comprises the first grid dielectric between semiconductor body first matrix border and the first grid structure, and the second grid dielectric between semiconductor body second matrix border and the second grid structure.
17. transistor as claimed in claim 11, wherein semiconductor body comprises the source/drain injection region of semiconductor body inside.
18. transistor as claimed in claim 11, wherein semiconductor body has uniform concentration of dopant.
19. transistor as claimed in claim 18, wherein concentration of dopant comprises the repeatedly angled injection in selected transistor uniformly, to produce uniform concentration of dopant.
20. transistor as claimed in claim 18, wherein concentration of dopant comprises 0.3N uniformly
AWith 3N
ABetween concentration of dopant, N wherein
ABe defined as:
21. transistor as claimed in claim 11, wherein semiconductor body first matrix border is relative with semiconductor body second matrix border, and wherein semiconductor body first matrix border and semiconductor body second matrix border perpendicular to the end face of substrate.
22. a FET dual gate comprises:
A) semiconductor body, semiconductor body forms from the silicon layer that is formed on the insulating barrier top, semiconductor body has first vertical matrix border and the second vertical matrix border, wherein second matrix border of first matrix border of semiconductor body and semiconductor body toward each other, and perpendicular to insulating barrier;
B) first grid dielectric layer is formed on first matrix border of semiconductor body;
C) second grid dielectric layer is formed on second matrix border of semiconductor body;
D) first grid structure is formed on the first grid dielectric layer of first matrix border of adjacent transistors matrix, and the first grid structure comprises p type polysilicon; And
E) second grid structure is formed on the second grid dielectric layer of second matrix border of adjacent transistors matrix, and the second grid structure comprises n type polysilicon.
23. FET dual gate as claimed in claim 22 also comprises in the semiconductor body by carry out the source/drain injection region that angled injection forms in semiconductor body.
24. FET dual gate as claimed in claim 22, wherein matrix comprises uniform concentration of dopant.
25. FET dual gate as claimed in claim 24, wherein concentration of dopant forms by carry out repeatedly angled injection in semiconductor body uniformly.
26. FET dual gate as claimed in claim 22 also comprises the polysilicon plugs that is used for first grid structure and second grid structure electric coupling.
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| US09/886,823 | 2001-06-21 | ||
| US09/886,823 US6960806B2 (en) | 2001-06-21 | 2001-06-21 | Double gated vertical transistor with different first and second gate materials |
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| US6960806B2 (en) | 2005-11-01 |
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| TW578295B (en) | 2004-03-01 |
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