CN105990344B - A kind of CMOS integrated circuits - Google Patents
A kind of CMOS integrated circuits Download PDFInfo
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- CN105990344B CN105990344B CN201510090701.3A CN201510090701A CN105990344B CN 105990344 B CN105990344 B CN 105990344B CN 201510090701 A CN201510090701 A CN 201510090701A CN 105990344 B CN105990344 B CN 105990344B
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Abstract
The present invention provides a kind of CMOS integrated circuits, which includes：Asymmetric high pressure NMOS, symmetric form high pressure NMOS, asymmetric high voltage PMOS, symmetric form high voltage PMOS, wherein the grid of the asymmetric high pressure NMOS is N-type polycrystalline silicon；The grid of the symmetric form high pressure NMOS is p-type polysilicon；The grid of the asymmetric high voltage PMOS is p-type polysilicon；The grid of the symmetric form high voltage PMOS is N-type polycrystalline silicon.CMOS integrated circuits provided by the invention solve the threshold voltage imbalance problem of high-pressure MOS of all categories present in CMOS integrated circuits by the way that the grid material of different classes of high-pressure MOS structure is respectively set.
Description
Technical field
The present invention relates to semiconductor integrated circuit field more particularly to a kind of CMOS integrated circuits.
Background technology
Mos field effect transistor (Metal Oxide Semiconductor Field Effect
Transistor, abbreviation MOS), it can be divided into N-channel MOS (abbreviation NMOS) and P-channel MOS (letters according to its conducting channel type
Claim PMOS).MOS integrated circuits are known as by the integrated circuit that metal-oxide-semiconductor is constituted, and the complementation collectively formed by PMOS tube and NMOS tube
Type integrated circuit is complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, letter
Claim CMOS) integrated circuit.
CMOS can be divided into low voltage CMOS and high-voltage CMOS according to the height of its operating voltage, be integrated wherein in high-voltage CMOS
NMOS and PMOS can be operated in 12 volts or more, referred to as high pressure NMOS and high voltage PMOS.Classify according to device architecture, high pressure
NMOS and high voltage PMOS all include asymmetric and two kinds of symmetric form, wherein the drain electrode of asymmetric high pressure N/PMOS can be held
By high pressure, the drain electrode of symmetric form high pressure N/PMOS and source electrode can bear high pressure.That is, in high-voltage CMOS integrated circuit
Usually all it is integrated with the high-pressure MOS of asymmetric high pressure N/PMOS, symmetric form high pressure N/PMOS totally four kinds of structures.
In the prior art, all there are one common ground for the structure of high-voltage CMOS integrated circuit, that is, above-mentioned four kinds of structures
The grid of high-pressure MOS is all the polycrystalline silicon material of N-type heavy doping.However, due to symmetric form high-pressure MOS and asymmetric high pressure
There is no doubt difference in the structure of MOS, imbalance occurs in the threshold voltage so as to cause the high-pressure MOS of above-mentioned four kinds of structures, most
A kind of typical phenomenon is exactly that the threshold voltage of asymmetric high pressure NMOS is more much larger than the threshold voltage of symmetric form high pressure NMOS,
The threshold voltage of asymmetric high voltage PMOS is more much larger than the threshold voltage of symmetric form high voltage PMOS.
Invention content
The present invention provides a kind of CMOS integrated circuits, to solve high pressure of all categories present in existing CMOS integrated circuits
The threshold voltage imbalance problem of MOS.
The present invention provides a kind of CMOS integrated circuits, including：
Asymmetric high pressure NMOS, symmetric form high pressure NMOS, asymmetric high voltage PMOS, symmetric form high voltage PMOS, wherein
The grid of the asymmetric high pressure NMOS is N-type polycrystalline silicon；
The grid of the asymmetric high voltage PMOS is p-type polysilicon；
The grid of the symmetric form high voltage PMOS is N-type polycrystalline silicon.
CMOS integrated circuits provided by the invention, according to N-type polycrystalline silicon this machine different from the work function of p-type polysilicon
Reason uses N-type polycrystalline silicon, the grid of symmetric form high pressure NMOS to use p-type polysilicon by the grid of asymmetric high pressure NMOS,
The imbalance of asymmetric high pressure NMOS and symmetric form high pressure NMOS structure threshold voltage can be alleviated；Pass through asymmetric high pressure
The grid of PMOS uses p-type polysilicon, the grid of symmetric form high voltage PMOS to use N-type polycrystalline silicon, can alleviate asymmetric high pressure
The imbalance of PMOS and symmetric form high voltage PMOS structure threshold voltage.
Description of the drawings
Fig. 1 is the structural schematic diagram for the CMOS integrated circuits that the embodiment of the present invention one provides.
Specific implementation mode
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
The every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
Fig. 1 is the structural schematic diagram for the CMOS integrated circuits that the embodiment of the present invention one provides, as shown in Figure 1, the CMOS
Integrated circuit, including NMOS and PMOS.NMOS includes：Asymmetric high pressure NMOS 11 and symmetric form high pressure NMOS 12；PMOS packets
It includes：Asymmetric high voltage PMOS 13 and symmetric form high voltage PMOS 14.Wherein, the grid of asymmetric high pressure NMOS 11 is that N-type is more
Crystal silicon；The grid of symmetric form high pressure NMOS 12 is p-type polysilicon；The grid of asymmetric high voltage PMOS 13 is p-type polysilicon；It is right
The grid of type high voltage PMOS 14 is referred to as N-type polycrystalline silicon.
Specifically, the structure of MOS may include gate oxide, source (Source), leakage (Drain), grid (Gate) and substrate,
The grid generally use metal or polysilicon structure of MOS.Further, according to the conduction type of conducting channel, MOS can be classified
It is further " to exhaust according to the principle of conducting, and by MOS points for N-channel MOS (NMOS) and P-channel MOS (PMOS)
Type " and two kinds of " enhanced ", specifically, the MOS in the present embodiment can be enhanced MOS.
In practical application, by mixing impurity element in a semiconductor material, its conduction can be made, correspondingly, according to partly leading
The conduction type of body can be classified as N-type semiconductor and P-type semiconductor.It is N specifically, being mixed with the semiconductor of group-v element
Type semiconductor is mixed with the semiconductor of group iii elements, is P-type semiconductor.Specifically, in the present embodiment, the N-type polycrystalline silicon
The impurity element of middle incorporation may include the polysilicon of phosphorus atoms, arsenic atom or antimony atoms, and optionally, doping concentration can be
1×1019~1 × 1023Atom/cubic centimetre.Again specifically, the impurity element mixed in the p-type polysilicon can be that boron is former
Son, optionally, doping concentration can be 1 × 1019~1 × 1023Atom/cubic centimetre.
Again specifically, the characterisitic parameter of MOS may include threshold voltage, operating voltage (operating voltage for refering in particular to drain-source)
Deng.Wherein, the threshold voltage of NMOS and operating voltage are positive value, and the threshold voltage and operating voltage of PMOS are negative value, for table
It is absolute value to state the threshold voltage and operating voltage conveniently, referred in the present embodiment.In the present embodiment, asymmetric high pressure
The drain electrode maximum operating voltage of NMOS11 and asymmetric high voltage PMOS 13 is more than 12 volts, symmetric form high pressure NMOS 12 and symmetric form
The maximum operating voltage of the source electrode and drain electrode of high voltage PMOS 14 is both greater than 12 volts.
It is in order to be better understood from the scheme of the present embodiment, the principles and methods of this programme are as follows：When other physical arrangement phases
Meanwhile grid uses the threshold voltage of the NMOS of N-type polycrystalline silicon using the threshold voltage of the NMOS of p-type polysilicon more than grid
Greatly, then it is based on this, N-type polycrystalline silicon, symmetric form high pressure are used by the grid of asymmetric high pressure NMOS 11 in the present embodiment
The grid of NMOS12 uses p-type polysilicon, can alleviate asymmetric high pressure NMOS 11 and 12 architectural difference of symmetric form high pressure NMOS
The imbalance of caused threshold voltage；When other physical arrangements are identical, grid uses the threshold voltage of the PMOS of p-type polysilicon
Absolute value than grid using N-type polycrystalline silicon PMOS threshold voltage absolute value smaller, then be based on this, in the present embodiment lead to
The grid for crossing asymmetric high voltage PMOS 13 uses p-type polysilicon, the grid of symmetric form high voltage PMOS 14 to use N-type polycrystalline silicon,
The imbalance of asymmetric high voltage PMOS 13 and threshold voltage caused by 14 architectural difference of symmetric form high voltage PMOS can be alleviated.
For example, when certain asymmetric high pressure NMOS 11 in the present embodiment is on shape with symmetric form NMOS12
State, the present embodiment reduce asymmetric high pressure using N-type polycrystalline silicon by the grid to asymmetric high pressure NMOS 11
The threshold voltage of NMOS11 improves symmetric form high pressure by the grid to symmetric form high pressure NMOS 12 using p-type polysilicon
The threshold voltage of NMOS12, to compensate for the threshold voltage difference of asymmetric high pressure NMOS 11 and symmetric form high pressure NMOS 12,
Balance the threshold voltage of both NMOS structures.
Again for example, it is led when certain asymmetric high voltage PMOS 13 in the present embodiment is in symmetric form high voltage PMOS 14
Logical state, the present embodiment reduce asymmetric high pressure using p-type polysilicon by the grid to asymmetric high voltage PMOS 13
The threshold voltage absolute value of PMOS13 increases symmetric form by the grid to symmetric form high voltage PMOS 14 using N-type polycrystalline silicon
The threshold voltage of high voltage PMOS 14, to compensate for the threshold voltage of asymmetric high voltage PMOS 13 and symmetric form high voltage PMOS 14
Difference balances the threshold voltage of both PMOS structures.
CMOS integrated circuits provided in this embodiment, according to N-type polycrystalline silicon this machine different from the work function of p-type polysilicon
Reason uses N-type polycrystalline silicon, the grid of symmetric form high pressure NMOS to use p-type polysilicon by the grid of asymmetric high pressure NMOS,
The imbalance of asymmetric high pressure NMOS and symmetric form high pressure NMOS structure threshold voltage can be alleviated；Pass through asymmetric high pressure
The grid of PMOS uses p-type polysilicon, the grid of symmetric form high voltage PMOS to use N-type polycrystalline silicon, can alleviate asymmetric high pressure
The imbalance of PMOS and symmetric form high voltage PMOS structure threshold voltage.
Finally it should be noted that：The above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Present invention has been described in detail with reference to the aforementioned embodiments for pipe, it will be understood by those of ordinary skill in the art that：Its according to
So can with technical scheme described in the above embodiments is modified, either to which part or all technical features into
Row equivalent replacement；And these modifications or replacements, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (10)
1. a kind of CMOS integrated circuits, which is characterized in that including：
Asymmetric high pressure NMOS, symmetric form high pressure NMOS, asymmetric high voltage PMOS, symmetric form high voltage PMOS, wherein
The grid of the asymmetric high pressure NMOS is N-type polycrystalline silicon；
The grid of the asymmetric high voltage PMOS is p-type polysilicon；
The grid of the symmetric form high voltage PMOS is N-type polycrystalline silicon.
2. CMOS integrated circuits according to claim 1, which is characterized in that the grid of the symmetric form high pressure NMOS is P
Type polysilicon.
3. CMOS integrated circuits according to claim 1, which is characterized in that the N-type polycrystalline silicon be mixed with phosphorus atoms,
The polysilicon of arsenic atom or antimony atoms.
4. CMOS integrated circuits according to claim 3, which is characterized in that the doping concentration of the N-type polycrystalline silicon be 1 ×
1019~1 × 1023Atom/cubic centimetre.
5. CMOS integrated circuits according to claim 1, which is characterized in that the p-type polysilicon is to be mixed with boron atom
Polysilicon.
6. CMOS integrated circuits according to claim 5, which is characterized in that the doping concentration of the p-type polysilicon be 1 ×
1019~1 × 1023Atom/cubic centimetre.
7. CMOS integrated circuits according to claim 1, which is characterized in that the asymmetric high pressure NMOS drain electrode is most
High working voltage is more than 12 volts.
8. CMOS integrated circuits according to claim 1, which is characterized in that the source electrode of the symmetric form high pressure NMOS and leakage
The maximum operating voltage of pole is more than 12 volts.
9. CMOS integrated circuits according to claim 1, which is characterized in that the asymmetric high voltage PMOS drain electrode is most
The absolute value of high working voltage is more than 12 volts.
10. CMOS integrated circuits according to claim 1, which is characterized in that the source electrode of the symmetric form high voltage PMOS and
The absolute value of the maximum operating voltage of drain electrode is more than 12 volts.
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| CN201510090701.3A CN105990344B (en) | 2015-02-28 | 2015-02-28 | A kind of CMOS integrated circuits |
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| CN105990344B true CN105990344B (en) | 2018-10-30 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1359156A (en) * | 2000-09-01 | 2002-07-17 | 精工电子有限公司 | CMOS semiconductor device and making method |
| CN1497724A (en) * | 2002-08-27 | 2004-05-19 | ���ش�洢����ʽ���� | Semiconductor device and its production method |
| CN1518772A (en) * | 2001-06-21 | 2004-08-04 | �Ҵ���˾ | Double gated transistor and method of manufacturing the same |
| CN1870298A (en) * | 2006-06-09 | 2006-11-29 | 北京大学 | Preparation method of NROM flash control grid and flash unit |
| CN101740627A (en) * | 2008-11-26 | 2010-06-16 | 阿尔特拉公司 | Asymmetric metal-oxide-semiconductor transistors |
| CN103035548A (en) * | 2011-10-10 | 2013-04-10 | 上海华虹Nec电子有限公司 | Method of judging whether boron penetrates through P-type metal-oxide-semiconductor field-effect transistor (PMOSFET) device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8399934B2 (en) * | 2004-12-20 | 2013-03-19 | Infineon Technologies Ag | Transistor device |
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- 2015-02-28 CN CN201510090701.3A patent/CN105990344B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1359156A (en) * | 2000-09-01 | 2002-07-17 | 精工电子有限公司 | CMOS semiconductor device and making method |
| CN1518772A (en) * | 2001-06-21 | 2004-08-04 | �Ҵ���˾ | Double gated transistor and method of manufacturing the same |
| CN1497724A (en) * | 2002-08-27 | 2004-05-19 | ���ش�洢����ʽ���� | Semiconductor device and its production method |
| CN1870298A (en) * | 2006-06-09 | 2006-11-29 | 北京大学 | Preparation method of NROM flash control grid and flash unit |
| CN101740627A (en) * | 2008-11-26 | 2010-06-16 | 阿尔特拉公司 | Asymmetric metal-oxide-semiconductor transistors |
| CN103035548A (en) * | 2011-10-10 | 2013-04-10 | 上海华虹Nec电子有限公司 | Method of judging whether boron penetrates through P-type metal-oxide-semiconductor field-effect transistor (PMOSFET) device |
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| CN105990344A (en) | 2016-10-05 |
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Effective date of registration: 20220728 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District, Cheng Fu Road, No. 298, Zhongguancun Fangzheng building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |
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Effective date of registration: 20230828 Address after: Building 2, Building A, Shenzhen Bay Innovation Technology Center, No. 3156 Keyuan South Road, Gaoxin District, Yuehai Street, Nanshan District, Shenzhen City, Guangdong Province, 518000, 3901 Patentee after: Shenzhen Major Industry Investment Group Co.,Ltd. Address before: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |