CN117316960A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN117316960A CN117316960A CN202311442834.3A CN202311442834A CN117316960A CN 117316960 A CN117316960 A CN 117316960A CN 202311442834 A CN202311442834 A CN 202311442834A CN 117316960 A CN117316960 A CN 117316960A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 96
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 239000000463 material Substances 0.000 claims abstract description 122
- 239000000758 substrate Substances 0.000 claims abstract description 108
- 238000005530 etching Methods 0.000 claims abstract description 35
- 230000001590 oxidative effect Effects 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 30
- 239000011810 insulating material Substances 0.000 claims description 13
- 238000002955 isolation Methods 0.000 claims description 6
- 230000005669 field effect Effects 0.000 abstract description 17
- 230000003647 oxidation Effects 0.000 abstract description 7
- 238000007254 oxidation reaction Methods 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000101 transmission high energy electron diffraction Methods 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- Thin Film Transistor (AREA)
Abstract
The application discloses a semiconductor device and a manufacturing method thereof, comprising the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first area and a second area which are adjacent to each other, etching the semiconductor substrate in the first area to form a first opening, sequentially filling a first material and a second material in the first opening, etching the second material at least to reach the first material, forming a fin channel in the first area, oxidizing the first material to form an oxidation insulating layer, and doping the second area to form a source electrode and a drain electrode of the planar device. According to the manufacturing method, the first opening is formed in the first area of the semiconductor substrate with low cost by etching, then the first opening is filled with the first material and the second material, the SOI substrate is formed in the first area, the second material is etched, the fin structure of the fin field effect transistor is formed in the first area, and the manufacturing cost is reduced on the basis that the fin field effect transistor based on the SOI substrate and the planar device based on the semiconductor substrate are manufactured simultaneously by utilizing the semiconductor substrate.
Description
Technical Field
The present disclosure relates to the field of semiconductors, and more particularly, to a semiconductor device and a method of manufacturing the same.
Background
With the development of semiconductor related technology, researchers have found that devices fabricated On Silicon-On-Insulator (SOI) substrates have smaller parasitic capacitance and leakage current, and better device performance. The SOI substrate comprises a top silicon layer, a back substrate and a buried oxide layer therebetween.
In practice, there is a need to integrate different semiconductor devices on the same wafer at the same time, such as Fin Field-Effect Transistor (FinFET) devices based on SOI substrates and Planar (Planar) devices based on semiconductor substrates at the same time.
Since the SOI substrate is expensive, when two devices of the FinFET based on the SOI substrate and the planar device based on the semiconductor substrate are integrated at the same time, the manufacturing cost is high, and the requirement of low-cost manufacturing cannot be satisfied.
Disclosure of Invention
In view of this, the present application provides a semiconductor device and a method of manufacturing the same capable of reducing manufacturing costs of two devices that simultaneously integrate a FinFET based on an SOI substrate and a planar device based on a semiconductor substrate.
The application provides a method for manufacturing a semiconductor device, which comprises the following steps:
providing a semiconductor substrate comprising adjacent first and second regions;
etching the semiconductor substrate of the first region to form a first opening;
sequentially filling a first material and a second material in the first opening to fill the first opening;
etching the second material at least to the first material, and forming a fin channel in the first region;
oxidizing the first material to form an oxide insulating layer in the first region;
and doping the second region to form a source electrode and a drain electrode.
Optionally, before etching the semiconductor substrate of the first region, the method further comprises:
covering a hard mask layer on the surface of the second region;
the etching the semiconductor substrate of the first region to form a first opening includes:
etching the semiconductor substrate of the first area by taking the hard mask layer as a mask to form a first opening;
before etching the second material at least to the first material, the method further comprises:
and removing the hard mask layer.
Optionally, the sequentially filling the first opening with the first material and the second material includes:
and sequentially growing a first material and a second material in the first opening.
Optionally, the etching the second material at least reaches the first material, and forming a fin channel in the first region includes:
and etching the second material at least to the first material by utilizing a self-aligned double pattern or self-aligned quadruple pattern process, and forming a fin channel in the first region, wherein the fin channel does not penetrate through the first material.
Optionally, the method further comprises:
forming a groove between the first region and the second region;
filling insulating materials in the grooves;
and etching the insulating material filled in the groove to form a shallow trench isolation layer between the first region and the second region.
Optionally, the depth of the recess is greater than the depth of the fin channel.
Optionally, the etching the second material at least reaches the first material, and forming a fin channel in the first region includes:
etching the second material at least to the first material, and forming a fin channel and a fin structure in the first region;
the method further comprises the steps of:
and forming a gate oxide layer and a gate sequentially between the fin structure and the source electrode and the drain electrode.
Optionally, the first material is Si.
Optionally, the thickness of the first material ranges from 0.002 to 2 microns.
The present application also provides a semiconductor device including:
a semiconductor substrate having formed thereon adjacent first and second devices;
the first device includes an oxide insulating layer and a fin structure covering the oxide insulating layer;
the second device includes a source and a drain within the semiconductor substrate.
Compared with the prior art, the application has at least the following advantages:
the application provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region which are adjacent, the semiconductor substrate has lower cost compared with an SOI substrate, etching the semiconductor substrate of the first region to form a first opening, sequentially filling a first material and a second material in the first opening to fill the first opening, forming a buried oxide layer in the SOI substrate by the first material, etching the second material of the first opening until the second material of the first opening reaches at least the first material, forming a first fin channel in the first region, namely forming a fin structure of a fin field effect transistor and a fin channel between the fin structures in the first region, oxidizing the first material of the first region, forming an oxidation insulating layer in the first region, namely forming the buried oxide layer in the SOI substrate, and then doping the second region to form a source electrode and a drain electrode of a planar device. Therefore, according to the embodiment of the application, the first opening is formed on the first area of the semiconductor substrate with lower cost by etching, then the first material and the second material are filled in the first opening, the first material is oxidized subsequently, the SOI substrate is formed in the first area, the semiconductor substrate is etched, the fin structure of the fin field effect transistor is formed in the first area, and the manufacturing cost is reduced on the basis that the fin field effect transistor based on the SOI substrate and the plane device based on the semiconductor substrate are manufactured simultaneously by using the semiconductor substrate.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of an embodiment of a method for manufacturing a semiconductor device provided in the present application;
fig. 2 to 9 are block diagrams of a semiconductor device manufactured according to a manufacturing method of the present application;
fig. 10 is a block diagram of a semiconductor device according to an embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
In describing embodiments of the present application in detail, the cross-sectional views illustrating the structure of the device are not to scale locally for ease of illustration, and the schematic is merely exemplary and should not limit the scope of protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
With the development of semiconductor related technology, researchers have found that devices fabricated On Silicon-On-Insulator (SOI) substrates have smaller parasitic capacitance and leakage current, and better device performance. The SOI substrate comprises a top silicon layer, a back substrate and a buried oxide layer therebetween.
In practice, there is a need to integrate different semiconductor devices on the same wafer at the same time, such as Fin Field effect transistors (FinFETs) based on SOI substrates and planar devices based on semiconductor substrates at the same time. Among them, the fin field effect transistor based on the SOI substrate may be simply referred to as SOI-FinFET, and the Planar device based on the semiconductor substrate may be simply referred to as Planar, e.g., metal-Oxide-semiconductor field effect transistor (MOSFET) Semiconductor Field-Effect Transistor.
Typically, SOI-finfets are fabricated on an SOI substrate, after which the top silicon and buried oxide layer of the SOI substrate are removed, planar is formed on a back substrate. Since the SOI substrate is expensive, when Planar is manufactured on the SOI substrate, the top silicon and the buried oxide layer of the SOI substrate need to be removed, resulting in a waste of cost of the part of the SOI substrate, that is, when two devices, i.e., the SOI-FinFET and Planar, are integrated at the same time, the manufacturing cost is high, and the requirement of low-cost manufacturing cannot be satisfied.
Based on this, the present application provides a method of manufacturing a semiconductor device, including: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first area and a second area which are adjacent, compared with an SOI substrate, the semiconductor substrate is low in cost, the semiconductor substrate of the first area is etched to form a first opening, a first material and a second material are sequentially filled in the first opening to fill the first opening, the first material can be used for subsequently forming a buried oxide layer in the SOI substrate, the second material after the first material is completely filled reaches at least the first material, fin channels are formed in the first area, namely fin structures of a fin field effect transistor and fin channels between the fin structures are formed in the first area, the first material of the first area is oxidized, an oxidation insulating layer is formed in the first area, namely the buried oxide layer in the SOI substrate is formed, then the second area is doped, and a source electrode and a drain electrode of a planar device are formed. Therefore, according to the embodiment of the application, the first opening is formed on the first area of the semiconductor substrate with lower cost by etching, then the first opening is filled with the first material and the second material, the first material is oxidized subsequently, the SOI substrate is formed in the first area, the second material is etched, the fin structure of the fin field effect transistor is formed in the first area, and the manufacturing cost is reduced on the basis that the fin field effect transistor based on the SOI substrate and the plane device based on the semiconductor substrate are manufactured simultaneously by using the semiconductor substrate.
For a better understanding of the technical solutions and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.
Referring to fig. 1, a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application is shown. The semiconductor device provided by the embodiment can integrate the fin field effect transistor based on the SOI substrate and the plane device based on the semiconductor substrate at the same time.
The manufacturing method of the semiconductor device provided in the embodiment includes the following steps:
s101, a semiconductor substrate 100 is provided, as shown with reference to fig. 2.
In the embodiments of the present application, the semiconductor substrate 100 may be utilized as a substrate for manufacturing a FinFET, which is inexpensive and has a better cost advantage than an SOI substrate. The semiconductor substrate 100 may be, for example, a silicon substrate.
The semiconductor substrate 100 includes at least a first region 101 and a second region 102 adjacent thereto, wherein the first region 101 may be subsequently used for fabricating SOI-finfets and the second region 102 may be subsequently used for fabricating Planar.
S102, etching the semiconductor substrate 100 of the first region 101 to form a first opening 110, as shown with reference to fig. 3.
In the embodiment of the present application, the semiconductor substrate 100 of the first region 101 is etched, and the first opening 110 is formed in the first region 101.
Specifically, before etching the semiconductor substrate 100 of the first region 101, damage to the semiconductor substrate of the second region 102 is avoided, and the surface of the second region 102 may be covered with the hard mask layer 103, as shown in fig. 3. The semiconductor substrate 100 of the first region 101 may then be etched with the hard mask layer 103 as a mask to form a first opening 110.
The etch depth of the first opening 110 may be slightly greater than the depth of the subsequently formed fin structure.
S103, sequentially filling the first material 120 and the second material 130 in the first opening 110 to fill the first opening 110, as shown with reference to fig. 4.
In an embodiment of the present application, after the first opening 110 is etched, the first material 120 and the second material 130 may be sequentially filled in the first opening 110.
Specifically, the first material 120 and the second material 130 are sequentially grown in the first opening 110, and the second material 130 covers the surface of the first material 120. The second material 130 may be silicon.
The first material 120 may be Si and the thickness of the first material 120 may range from 0.002 to 2 microns.
Specifically, the thickness of the second material 130 may be greater than the thickness of the first material 120 for subsequent fin structure formation.
The growth process of the second material 130 and the first material 120 is different so that the properties of the resulting film layer are different even if the same material is grown. This may facilitate subsequent oxidation of the first material 120 without affecting the second material 130.
At S104, the second material 130 is etched at least to the first material 120, and fin channels 140 are formed in the first region 101, as shown with reference to fig. 5.
In embodiments of the present application, the second material 130 may be etched to a depth at least up to the surface of the first material 120 to form fin channels 140 in the first region 101.
Simultaneously with the formation of the fin channel 140, a fin structure 150 is also formed in the first region 101.
Specifically, the second material 130 may be etched using a Self-aligned double pattern (Self-aligned Double Patterning, SADP) or Self-aligned quad pattern (Self-aligned Quadruple Pattern, SADP) process at least to the first material 120, forming the fin channel 140 and the fin structure 150 in the first region 101, wherein the fin channel 140 does not penetrate the first material 120, to avoid that subsequently formed FinFET devices are not based on SOI substrates.
In an embodiment of the present application, the hard mask layer 103 formed on the surface of the second region 102 is removed before etching the second material 130 to form the fin channel 140 and the fin structure 150.
In the embodiment of the present application, when the fin channel 140 and the fin structure 150 are formed by etching the second material 130, the semiconductor substrate 100 may also be etched, a groove 104 is formed between the first region 101 and the second region 102, as shown in fig. 5, an insulating material 105 is filled in the groove 104, as shown in fig. 6, the insulating material 105 filled in the groove 104 is etched, and a shallow trench isolation 106 is formed between the first region 101 and the second region 102, as shown in fig. 7.
Specifically, the depth of the recess 104 is greater than the depth of the fin channel 140 to form a shallow trench isolation layer 106 between the first region 101 and the second region 102, isolating the FinFET device formed in both regions.
In practical applications, when the insulating material 105 is filled in the recess 104, the insulating material 105 is also filled in the fin channel 140 and the fin structure 150, and when the insulating material 105 filled in the recess 104 is etched later, the insulating material 105 in the fin channel 140 and the fin structure 150 is etched at the same time, and the specific etching depth may be the depths of the fin channel 140 and the fin structure 150, so that the insulating material 105 in the fin channel 140 and the fin structure 150 is removed entirely, exposing the bottoms of the fin channel 140 and the fin structure 150, and at this time, the remaining insulating material 105 in the recess 104 forms the shallow trench isolation layer 106.
The insulating material 105 may be silicon oxide or the like.
S105, oxidizing the first material 120, and forming an oxide insulating layer 160 in the first region 101, as shown in fig. 8.
In embodiments of the present application, after forming fin via 140 and fin structure 150, first material 120 of first region 101 may be oxidized to form an oxide insulating layer 160 in first region 101, oxide insulating layer 160 being located between second material 130 and semiconductor substrate 100, i.e., second material 130, oxide insulating layer 160 and semiconductor substrate 100 constitute an SOI substrate, fin structure 150 located on the SOI substrate, and subsequently, a FinFET structure based on the SOI substrate may be formed.
In the embodiment of the present application, since the processes for forming the first material 120 and the second material 130 are different, the second material 130 may have a smaller oxidation effect when the first material 120 is oxidized, so that only the first material 120 is oxidized, and oxidation of the second material 130 is reduced or avoided.
S106, doping the second region 102 to form a source 107 and a drain 108, as shown in fig. 9.
In the embodiment of the present application, after the fin channel 140 and the fin structure 150 are formed in the first region 101, the semiconductor substrate 100 of the second region 102 may be doped to form the source 107 and the drain 108 in the second region 102, where the source 107 and the drain 108 form part of the structure of the Planar device.
In the embodiment of the present application, after the fin structure 150 is formed and the first material 120 is oxidized, a portion of the SOI-FinFET structure is already integrated, the source 107 and the drain 108 are formed in the second region 102, a portion of the Planar structure is already integrated, and then a gate oxide layer and a gate may be sequentially formed between the fin structure 150 and the source 107 and the drain 108 in the second region 102, so that a semiconductor device that simultaneously integrates the SOI-FinFET and the Planar structure is obtained.
Therefore, the manufacturing method of the semiconductor device can integrate the manufacturing processes of the SOI-FinFET and the Planar on the semiconductor substrate at the same time, has larger cost advantage, and can meet the low-cost requirement.
The embodiment of the application provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first area and a second area which are adjacent, compared with an SOI substrate, the semiconductor substrate is low in cost, the semiconductor substrate of the first area is etched to form a first opening, a first material and a second material are sequentially filled in the first opening to fill the first opening, the first material can be used for subsequently forming a buried oxide layer in the SOI substrate, the second material after the first material is completely filled reaches at least the first material, fin channels are formed in the first area, namely fin structures of a fin field effect transistor and fin channels between the fin structures are formed in the first area, the first material of the first area is oxidized, an oxidation insulating layer is formed in the first area, namely the buried oxide layer in the SOI substrate is formed, then the second area is doped, and a source electrode and a drain electrode of a planar device are formed. Therefore, according to the embodiment of the application, the first opening is formed on the first area of the semiconductor substrate with lower cost by etching, then the first opening is filled with the first material and the second material, the first material is oxidized subsequently, the SOI substrate is formed in the first area, the second material is etched, the fin structure of the fin field effect transistor is formed in the first area, and the manufacturing cost is reduced on the basis that the fin field effect transistor based on the SOI substrate and the plane device based on the semiconductor substrate are manufactured simultaneously by using the semiconductor substrate.
Based on the method for manufacturing the semiconductor device provided by the embodiment, the embodiment of the application also provides a semiconductor device, and the working principle of the semiconductor device is described in detail below with reference to the accompanying drawings.
Referring to fig. 10, a block diagram of a semiconductor device according to an embodiment of the present application is shown.
The semiconductor device provided in this embodiment includes:
a semiconductor substrate 100, on which the first device 200 and the second device 300 are formed adjacent to each other;
the first device 200 includes an oxide insulating layer 160 and a fin structure 150 covering the oxide insulating layer 160;
the second device 300 includes a source 107 and a drain 108 within the semiconductor substrate 100.
That is, the first device 200 is an SOI-FinFET and the second device 300 is Planar.
Specifically, a shallow trench isolation layer 106 is formed between the first device 200 and the second device 300 for isolating the first device 200 and the second device 300.
When introducing elements of various embodiments of the present application, the articles "a," "an," "the," and "said" are intended to mean that there are one or more of the elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements.
It should be noted that, it will be understood by those skilled in the art that all or part of the above-mentioned method embodiments may be implemented by a computer program to instruct related hardware, where the program may be stored in a computer readable storage medium, and the program may include the above-mentioned method embodiments when executed. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a random-access Memory (Random Access Memory, RAM), or the like.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points. The apparatus embodiments described above are merely illustrative, wherein the units and modules illustrated as separate components may or may not be physically separate. In addition, some or all of the units and modules can be selected according to actual needs to achieve the purpose of the embodiment scheme. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
The foregoing is merely exemplary of the application and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the application and are intended to be comprehended within the scope of the application.
Claims (10)
1. A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate comprising adjacent first and second regions;
etching the semiconductor substrate of the first region to form a first opening;
sequentially filling a first material and a second material in the first opening to fill the first opening;
etching the second material at least to the first material, and forming a fin channel in the first region;
oxidizing the first material to form an oxide insulating layer in the first region;
and doping the second region to form a source electrode and a drain electrode.
2. The method of claim 1, wherein prior to etching the semiconductor substrate of the first region, the method further comprises:
covering a hard mask layer on the surface of the second region;
the etching the semiconductor substrate of the first region to form a first opening includes:
etching the semiconductor substrate of the first area by taking the hard mask layer as a mask to form a first opening;
before etching the second material at least to the first material, the method further comprises:
and removing the hard mask layer.
3. The method of claim 1, wherein sequentially filling the first opening with a first material and a second material comprises:
and sequentially growing a first material and a second material in the first opening.
4. The method of claim 1, wherein the etching the second material at least to the first material, forming a fin via in the first region comprises:
and etching the second material at least to the first material by utilizing a self-aligned double pattern or self-aligned quadruple pattern process, and forming a fin channel in the first region, wherein the fin channel does not penetrate through the first material.
5. The method according to claim 1, wherein the method further comprises:
forming a groove between the first region and the second region;
filling insulating materials in the grooves;
and etching the insulating material filled in the groove to form a shallow trench isolation layer between the first region and the second region.
6. The method of claim 5, wherein a depth of the recess is greater than a depth of the fin channel.
7. The method of any of claims 1-6, wherein the etching the second material at least to the first material, forming a fin via in the first region comprises:
etching the second material at least to the first material, and forming a fin channel and a fin structure in the first region;
the method further comprises the steps of:
and forming a gate oxide layer and a gate sequentially between the fin structure and the source electrode and the drain electrode.
8. The method of any of claims 1-6, wherein the first material is Si.
9. The method of any one of claims 1-6, wherein the first material has a thickness in the range of 0.002-2 microns.
10. A semiconductor device, comprising:
a semiconductor substrate having formed thereon adjacent first and second devices;
the first device includes an oxide insulating layer and a fin structure covering the oxide insulating layer;
the second device includes a source and a drain within the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311442834.3A CN117316960A (en) | 2023-11-01 | 2023-11-01 | Semiconductor device and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311442834.3A CN117316960A (en) | 2023-11-01 | 2023-11-01 | Semiconductor device and manufacturing method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN117316960A true CN117316960A (en) | 2023-12-29 |
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| CN202311442834.3A Pending CN117316960A (en) | 2023-11-01 | 2023-11-01 | Semiconductor device and manufacturing method thereof |
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| Country | Link |
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- 2023-11-01 CN CN202311442834.3A patent/CN117316960A/en active Pending
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