Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
  • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
  • H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
  • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
  • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
  • H10D30/6733—Multi-gate TFTs
  • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile

Definitions

• the present invention relates to semiconductor devices, and more particularly, to a method of making a planar double-gated transistor.
• Double-gated transistors provide both a more effective current drive and low leakage. This has been most easily conceived in a FinFET arrangement where the gates are disposed on the sides of a fin of silicon. FinFET-based circuit design requires a whole a new design technology and FinFETs suffer from line edge roughness at the (110)/(100) interface and is difficult for use in analog applications because of its quantized width increments. Planar double-gated devices do not suffer from these problems but do present other manufacturing difficulties due to one of the gates being below the channel. The solutions tend present manufacturing challenges relating to the beginning stack of materials, gate contact, source/drain contact, and forming the lower gate.
• FIG. l is a cross section along a first plane of a device structure at a stage in processing according to an embodiment of the invention
• FIG. 2 is a cross section along the first plane of the device structure of FIG. 1 at a subsequent stage in processing
• FIG. 3 is a cross section along the first plane of the device structure of FIG. 2 at a subsequent stage in processing
• FIG. 4 is a cross section along the first plane of the device structure of FIG. 3 at a subsequent stage in processing
• FIG. 5 is a cross section along the first plane of the structure of FIG. 4 at a subsequent stage in processing; and FIG. 6 is a cross section along the first plane of the device structure of FIG. 5 at a subsequent stage in processing.
• FIG. 7 is a cross section along a second plane of the device structure of FIG. 6;
• FIG. 8 is cross section along the second plane of the device structure of FIG. 7 at a subsequent state in processing
• FIG. 9 is a cross section along the second plane of the device structure of FIG. 8 at a subsequent stage in process
• FIG. 10 is a cross section along the first plane of the device structure of FIG. 9;
• FIG. 11 is a cross section along the first plane of the structure of FIG. 10 at a subsequent stage in processing
• FIG. 12 is a cross section along the first plane of the structure of FIG. 11 at a subsequent stage in processing
• FIG. 13 is a cross section along the first plane of the structure of FIG. 12 at a subsequent stage in processing.
• FIG. 14 is a cross section along the second plane of the structure of FIG. 13 at a subsequent stage in processing.
• a planar double-gated transistor is achieved with a starting combination of a silicon layer over a silicon germanium layer (SiGe) which in turn is over a thick buried oxide (BOX).
• SiGe silicon germanium layer
• BOX thick buried oxide
• An optional oxide layer is grown over the silicon layer and a silicon nitride layer is provided over the stack.
• the silicon on SiGe on BOX is a combination of layers that is commercially available and the oxide and nitride layers are formed by standard semiconductor processing steps.
• the combination is etched to leave a stack with a width that is a little greater than a desired gate length of the transistor structure to be completed.
• a sidewall insulating layer is formed on the SiGe while exposing the sidewall of the silicon.
• Silicon is epitaxially grown from the exposed silicon sidewall to form in-situ-doped silicon source/drain regions. These are made relatively large to be adjoining the sidewall of the nitride layer.
• the nitride layer is removed selectively leaving the epitaxially grown source/drain regions as a boundary for a cavity above the silicon layer.
• Non -conductive material is formed on the sidewalls of the cavity either by oxide growth or a sidewall spacer process.
• the lower SiGe layer is removed to leave a cavity under the silicon layer.
• the cavities above and below the silicon layer, after gate dielectric formation on both sides of the silicon layer, are both filled with metal to achieve the double- gated transistor.
• the metal formation automatically forms extensions from both above and below the silicon layer that grow together and are continuous with metal that is deposited on the BOX. Thus convenient gate contact points outside the stack are available. This is better understood with reference to the drawings and the following description.
• FIG. 1 Shown in FIG. 1 is a semiconductor device 10 comprising a thick oxide layer 12 that can be conveniently be referenced as BOX 12, a silicon germanium (SiGe) layer 14 on box 12, a silicon layer 16 on SiGe layer 14, an oxide layer 18 on silicon layer 16, and silicon nitride layer 20 on oxide layer 18. It is understood that in practice there would be a supporting structure under BOX 12 such as a thick silicon layer functioning as a substrate.
• BOX 12 is about 1000 Anstroms
• SiGe layer 14 is preferably about 30% silicon and about 500 Angstroms
• silicon layer 16 is monocrystalline and about 200 Angstroms
• oxide layer 18 is about 100 Angstroms
• nitride layer 20 is about 600 Angstroms.
• SiGe layer 14, silicon layer 16, oxide layer 18, and nitride layer 20 have been etched to form a stack having sidewalls useful in forming a double-gated transistor so this stack can thus also be called a pre-transistor stack.
• the stack as shown has a width of about 500 Angstroms, which will be approximately the channel length of a transistor to be formed in the stack.
• semiconductor device 10 Shown in FIG. 2 is semiconductor device 10 after growing oxide layers 21 and 25 on exposed sidewalls of SiGe layer 14 and silicon layer 16. Oxide growth is faster on SiGe layer 22 than on silicon layer 16 so that oxide layer 21 has a SiGe sidewall insulator 22 that is thicker, by about four times, than a silicon sidewall insulator 24.
• oxide layer 25 has a SiGe sidewall insulator 28 that is thicker, by about four times, than a silicon sidewall insulator 26.
• the thickness of SiGe sidewall insulators 22 and 28 is about 250 Angstroms. Because this is a grown oxide process, portions of SiGe layer 14 and silicon layer 16 are consumed in the formation of oxide layers 21 and 25.
• FIG. 3 Shown in FIG. 3 is semiconductor device 10 after an isotropic etch back of oxide layers 21 and 25. This etch is performed sufficiently long to ensure that silicon sidewall insulators 24 and 26 are completely removed to expose the sidewalls of silicon layer 16, but sufficiently short to ensure that SiGe sidewall insulators 22 and 28 are not removed and still cover the sidewalls of SiGe layer 14. In this example, the remaining thickness of SiGe layer is preferably about 150 Angstroms.
• An alternative is to combine the growth and etch back approach shown in FIGs. 2 and 3 with a sidewall spacer process to form sidewall spacers that result in a sidewall insulator that exposes silicon layer 16, or at least most of it, and covers the sidewalls of the SiGe layer 14.
• FIG. 4 Shown in FIG. 4 is semiconductor device 10 after epitaxially growing source/drain regions 30 and 32 from the sidewalls of silicon layer 16. This growth continues until source/drain regions completely cover the sidewalls of nitride layer 20. To ensure this, epitaxial growth continues until source/drain layers 30 and 32 extend above nitride layer 20.
• the epitaxial growth has substantially the same rate in all directions so source drain regions extend laterally outward a little further than the thickness of the combination of oxide layer 18 and nitride layer 20.
• the lateral extent of the source/drain epitaxial region is about 700 Angstroms, which is sufficient for making a contact to it.
• the actual lateral dimension from the stack is even greater due to the extra growth above the top surface of nitride layer 20.
• the desired doping level is achieved by the in situ doping during the epitaxial growth process.
• semiconductor device 10 Shown in FIG. 5 is semiconductor device 10 after a chemical mechanical process step which removes the portion of source/drain regions 30 and 32 above nitride layer 20 to achieve a planar surface for nitride layer 20 and source/drain regions 30 and 32.
• FIG. 6 Shown in FIG. 6 is semiconductor device 10 after removing nitride layer 20 and growing oxide layer 34 on source/drain region 30, oxide layer 36 on source/drain region 32, and oxide layer 38 on the top surface of oxide layer 18.
• Oxide layers 34 and 36 are preferably about 100 Angstroms and oxide layer 38 is much thinner due to being grown over oxide layer 18 which is disposed over silicon layer 16 which is either undoped or lightly doped compared to source/drain regions 30 and 32.
• the region where the nitride is removed is one of the gate locations; the upper one.
• removing nitride layer 20 has the effect of exposing the upper gate location.
• the other gate location is under silicon layer and can be considered the lower gate location.
• a sidewall spacer process to form a sidewall spacer inside the opening for the upper gate location.
• the purpose of the sidewall spacer is to provide a dielectric element between source/drain regions 30 and 32 and the upper portion of the gate. This increases the amount of dielectric between the upper gate and source/drain regions 30 and 32.
• FIG. 7 Shown in FIG. 7 is a cross section taken at 7-7 of FIG. 6.
• This cross section of FIG. 7 can be considered the second cross sectional plane with the first cross sectional plane being the one used for FIGs. 1-6 through semiconductor 10 as shown in FIG. 6.
• This FIG. 7 shows that the stack made up of SiGe layer 14, silicon layer 16, oxide layer 18, and oxide layer 38 continues indefinitely across a semiconductor wafer.
• source/drain regions 30 and 32 traverse the same distance as the stack.
• FIG. 8 Shown in FIG. 8, continuing with the second cross sectional plane, is semiconductor device 10 after removing oxide layers 38 and then 18.
• FIG. 9 continuing with the second cross sectional plane, is semiconductor device 10 after etching through the stack to BOX 12 in selected locations to achieve a plurality of transistors sites; in this example, transistor sites 40, 42, and 44.
• transistor sites 40, 42, and 44 has a selected width as shown in FIG. 9. The width of these sites in this FIG. 9, corresponds to the channel width of the transistor that will be formed at that site.
• FIG. 10 Shown in FIG. 10 is a cross section taken at 10-10 of FIG. 9, which is a return to the first cross sectional plane, through semiconductor 10 as shown in FIG. 9.
• the particular cross section is of transistor site 40 but would be the same for transistor sites 42 and 44 as well.
• Etch chemistry is known that achieves a greater than 50 to 1 selectivity between SiGe and silicon. Cavity 46 may also be called an opening. The etch that results in this opening has the effect of exposing the lower gate location.
• FIG. 12 Shown in FIG. 12, continuing with the first cross sectional plane, is a semiconductor device 10 after formation of gate dielectric 48, preferably a high k dielectric such as a metal oxide, hafnium oxide for example, deposited by atomic layer deposition (ALD).
• ALD atomic layer deposition
• the purpose is to form a gate dielectric so the material is chosen for that purpose.
• FIG. 13 continuing with the first cross sectional plane, is semiconductor device 10 after formation of a metal gate 50 over silicon layer 16 and in cavity 46.
• the deposition initially is preferably by ALD to achieve an effective deposition of metal of a desired work function on insulator.
• a metallic conductor is preferably used although ALD could be continued to complete the formation of the gate electrode.
• Chemical vapor deposition is preferable because it is relatively fast and sufficiently conformal for this purpose.
• a CMP etch back is performed to remove the metal over source/drain regions 30 and 32 near where the nitride was removed.
• a mask is formed over the area where the nitride was removed and the source/drain region near there and also to areas where the gate is to extend outside transistor site 40. With the mask in place, the exposed metal is then removed. This leaves gate metal 50 above and below silicon layer 16 and gate extensions not shown in FIG. 13.
• Semiconductor device 10 as shown in FIG. 13 is a completed transistor.
• FIG. 14 Shown in FIG. 14 is a cross section 14-14, which is a change to the second cross sectional plane, through semiconductor device 10 of FIG. 13 which shows gate metal 50 with a gate extension 52 connected thereto extending outside of transistor 40 for making contact thereto.
• nitride layer 20 may be a different material. It is desirable that it be a layer that is relatively resistant to oxidation. It is undesirable that a layer be formed along the upper transistor location during the formation of layer 21.
• Silicon layer 16 may be a different monocrystalline semiconductor material. Silicon carbon is a possibility. The important characteristic is that it oxidize significantly more slowly than the layer underneath, for example at least four times slower.
• SiGe layer 14 may also be another material. The important characteristic is that it etch selective to the overlying monocrystalline semiconductor layer. The relative etch rate is preferably greater than 50 to 1.
• the preferred metal for metal gate 50 is tantalum nitride but other metals may also be used.
• Exemplary metals include titanium nitride, tantalum carbide, and nickel suicide. Other materials may also be used. It should have a relatively high reflow temperature and not react with the gate dielectric. Oxide layer 18 may not be required. It is to protect silicon layer 16 during the removal of nitride layer 20. If an etchant that does not disturb silicon is used in the removal of nitride layer 20 or an alternative to nitride layer 20, then silicon layer 16 may not be required. Also another material than oxide may be used. Such material should etch selective to nitride layer 20 or its alternative. The silicon layer may have a thickness of approximately 200 to 700 angstroms. The SiGe layer may have a thickness of approximately 80 to 400 angstroms.
• the gate dielectric was described as a high k dielectric but could be another gate dielectric material such as oxide.
• the gate was described as being a metal but may be some other conductor such as a doped semiconductor. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.

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• Insulated Gate Type Field-Effect Transistor (AREA)
• Thin Film Transistor (AREA)

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• 2005
  • 2005-01-31 US US11/047,448 patent/US7202117B2/en not_active Expired - Fee Related
  • 2005-12-14 JP JP2007553098A patent/JP4965462B2/ja not_active Expired - Fee Related
  • 2005-12-14 EP EP05854001A patent/EP1846945A2/en not_active Withdrawn
  • 2005-12-14 CN CNB2005800440725A patent/CN100514547C/zh not_active Expired - Fee Related
  • 2005-12-14 WO PCT/US2005/045202 patent/WO2006083401A2/en not_active Ceased
  • 2005-12-14 KR KR1020077017635A patent/KR20070100777A/ko not_active Withdrawn
• 2006
  • 2006-01-04 TW TW095100395A patent/TWI397128B/zh not_active IP Right Cessation

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