JP4951276B2 - 半導体チップおよび半導体装置 - Google Patents
半導体チップおよび半導体装置 Download PDFInfo
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- JP4951276B2 JP4951276B2 JP2006148399A JP2006148399A JP4951276B2 JP 4951276 B2 JP4951276 B2 JP 4951276B2 JP 2006148399 A JP2006148399 A JP 2006148399A JP 2006148399 A JP2006148399 A JP 2006148399A JP 4951276 B2 JP4951276 B2 JP 4951276B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006148399A JP4951276B2 (ja) | 2006-05-29 | 2006-05-29 | 半導体チップおよび半導体装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006148399A JP4951276B2 (ja) | 2006-05-29 | 2006-05-29 | 半導体チップおよび半導体装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2007318014A JP2007318014A (ja) | 2007-12-06 |
| JP2007318014A5 JP2007318014A5 (enExample) | 2009-07-02 |
| JP4951276B2 true JP4951276B2 (ja) | 2012-06-13 |
Family
ID=38851590
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006148399A Active JP4951276B2 (ja) | 2006-05-29 | 2006-05-29 | 半導体チップおよび半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4951276B2 (enExample) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100719157B1 (ko) * | 1999-12-21 | 2007-05-17 | 소니 가부시끼 가이샤 | 더빙시스템 및 더빙방법 |
| US10020288B2 (en) | 2015-10-06 | 2018-07-10 | Samsung Electronics Co., Ltd. | Semiconductor chips including redistribution interconnections and related semiconductor packages |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5027605B2 (ja) | 2007-09-25 | 2012-09-19 | パナソニック株式会社 | 半導体装置 |
| JP4422753B2 (ja) * | 2007-12-14 | 2010-02-24 | シャープ株式会社 | 半導体装置 |
| JP2009246218A (ja) | 2008-03-31 | 2009-10-22 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
| JP5160295B2 (ja) | 2008-04-30 | 2013-03-13 | ルネサスエレクトロニクス株式会社 | 半導体装置及び検査方法 |
| JP5160498B2 (ja) | 2009-05-20 | 2013-03-13 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP2012151269A (ja) * | 2011-01-19 | 2012-08-09 | Seiko Epson Corp | 半導体装置、及び半導体装置の製造方法 |
| JP6519135B2 (ja) | 2014-09-26 | 2019-05-29 | 日亜化学工業株式会社 | 発光装置及び発光装置用基板 |
| JP6012688B2 (ja) * | 2014-10-24 | 2016-10-25 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| CN106680547A (zh) * | 2015-11-10 | 2017-05-17 | 上海和辉光电有限公司 | 一种测试垫布局结构及电性测试方法 |
| JP6649189B2 (ja) * | 2016-06-27 | 2020-02-19 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP6767789B2 (ja) * | 2016-06-29 | 2020-10-14 | ローム株式会社 | 半導体装置 |
| JP6901902B2 (ja) * | 2017-04-27 | 2021-07-14 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| CN110729252B (zh) * | 2019-10-31 | 2021-12-24 | 中国电子科技集团公司第十三研究所 | 0.4mm节距的陶瓷四边引线扁平外壳 |
| CN114973970A (zh) * | 2022-06-28 | 2022-08-30 | 合肥维信诺科技有限公司 | 显示面板 |
| CN116313859B (zh) * | 2023-05-26 | 2023-09-15 | 青岛泰睿思微电子有限公司 | 悬臂产品的焊线方法 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59127852A (ja) * | 1983-01-12 | 1984-07-23 | Matsushita Electronics Corp | 半導体装置 |
| JP2001264391A (ja) * | 2000-03-17 | 2001-09-26 | Mitsubishi Materials Corp | 電極端子及び該電極端子を有する回路素子 |
| JP2002076075A (ja) * | 2000-08-24 | 2002-03-15 | Nec Corp | 半導体集積回路 |
| JP2002329742A (ja) * | 2001-05-07 | 2002-11-15 | Mitsubishi Electric Corp | 半導体装置 |
| WO2006134643A1 (ja) * | 2005-06-14 | 2006-12-21 | Renesas Technology Corp. | 半導体装置及びその製造方法 |
-
2006
- 2006-05-29 JP JP2006148399A patent/JP4951276B2/ja active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100719157B1 (ko) * | 1999-12-21 | 2007-05-17 | 소니 가부시끼 가이샤 | 더빙시스템 및 더빙방법 |
| US10020288B2 (en) | 2015-10-06 | 2018-07-10 | Samsung Electronics Co., Ltd. | Semiconductor chips including redistribution interconnections and related semiconductor packages |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2007318014A (ja) | 2007-12-06 |
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