WO2016165607A1 - 一种集成电路、引线键合封装芯片及倒装封装芯片 - Google Patents

一种集成电路、引线键合封装芯片及倒装封装芯片 Download PDF

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Publication number
WO2016165607A1
WO2016165607A1 PCT/CN2016/079053 CN2016079053W WO2016165607A1 WO 2016165607 A1 WO2016165607 A1 WO 2016165607A1 CN 2016079053 W CN2016079053 W CN 2016079053W WO 2016165607 A1 WO2016165607 A1 WO 2016165607A1
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Prior art keywords
pad group
pad
power ground
signal
group
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PCT/CN2016/079053
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English (en)
French (fr)
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刘亮
赵南
王晨
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华为技术有限公司
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Publication of WO2016165607A1 publication Critical patent/WO2016165607A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to an integrated circuit, a wire bond package chip, and a flip chip package chip.
  • integrated circuits are developing in the direction of high performance on the one hand, and on the other hand, in the direction of lightness and shortness.
  • integrated circuit methods include wire bond packaging and flip chip packaging.
  • the signal pads 11 are generally designed in the inner row of the bare chip 10, and the power source pads 12 are designed in the outer row of the bare chip 10.
  • the position of the pad is just opposite to the wire bonding package, usually the power ground pad 22 is designed in the inner row of the bare chip 20, and the signal pad 21 is designed on the bare chip. 20 out of the row.
  • Embodiments of the present invention provide an integrated circuit, a wire bond package chip, and a flip chip package.
  • the integrated circuit can meet both package requirements of wire bond package and flip chip package.
  • the technical solution is as follows:
  • an embodiment of the present invention provides an integrated circuit, including:
  • At least one pad group the at least one pad group being fixed on an active surface of the bare chip, each of the at least one pad group including a first signal pad group, a second signal Pad a group, a first power ground pad group, and a second power ground pad group;
  • first signal pad group and the second signal pad group respectively comprise at least one signal pad
  • first power ground pad group and the second power ground pad group respectively comprise at least one Power ground pad
  • the distance between the pad in the first power ground pad group and the first outgoing line side is less than or equal to the distance between the pad in the first signal pad group and the first outgoing line side, the first outgoing line
  • the side is a side of the bare chip through which the first power ground pad group and the first signal pad group are connected at the time of packaging, and the second power ground pad group
  • the distance between the pad and the first outgoing side is greater than or equal to the distance between the pad in the second signal pad group and the first outgoing side.
  • the pads in each of the pad groups are arranged in rows, and each row is parallel to the first outlet side.
  • only the power ground pad or the signal pad is provided in each row.
  • the second signal pad group is between the second power ground pad group and the first signal pad group
  • the first signal pad a group is between the second signal pad group and the first power ground pad group
  • the first power ground pad group is between the first signal pad group and the second power ground pad group, and the second power ground pad group is at the first power ground pad group Between the second signal pad group and the second signal pad group.
  • the first signal pad group is between the second power ground pad group and the second signal pad group
  • the second signal pad is a group is between the first signal pad group and the first power ground pad group
  • the second power ground pad group is between the first signal pad group and the first power ground pad group, and the first power ground pad group is in the second power ground pad group Between the second signal pad group and the second signal pad group.
  • the first signal pad group and the second signal pad group are at the first power ground pad group and the second power ground pad between the groups, at least one of the first group of signal pads is at the same position as at least one of the second group of signal pads; or
  • the first power ground pad group and the second power ground pad group are between the first signal pad group and the second signal pad group, the first power ground pad group At least one of the pads A pad at the same location as at least one of the second set of power ground pads.
  • the signal pad and the power ground pad are simultaneously provided in the same row.
  • the pads in the first signal pad group and the pads in the first power ground pad group are simultaneously provided in one row, the first a distance between the second power ground pad group and the first outgoing line side is greater than a distance between the first power ground pad group and the first outgoing line side;
  • the distance is greater than the distance between the second power ground pad group and the first outgoing side.
  • the pads in the first signal pad group and the pads in the second power ground pad group are simultaneously provided in at least one row; or Having the pads in the second set of signal pads and the pads in the first set of power ground pads simultaneously in at least one row; or, the first signal is simultaneously provided in at least one row a pad in the pad group and a pad in the second power ground pad group, and at least one of the second signal pad group and the first power ground are simultaneously provided in at least one row a pad in a pad group;
  • the distance between the second power ground pad group and the first outgoing side is greater than the distance between the first power ground pad group and the first outgoing side.
  • the pads in the first power ground pad group and the signal pads are simultaneously provided in one row; or the at least one row is simultaneously provided a pad in the first signal pad group and a pad in the second power ground pad group; or, in a row, a pad and a pad in the first power ground pad group are simultaneously provided a signal pad, and a pad in the first signal pad group and a pad in the second power ground pad group are simultaneously provided in at least one row;
  • the distance between the second power ground pad group and the first outgoing side is greater than the distance between the first power ground pad group and the first outgoing side, and at least one of the first signal pad groups
  • the pad is a pad at the same location as at least one of the second set of signal pads.
  • the pads in the first signal pad group and the power ground pad are simultaneously provided in one row; or the at least one row is simultaneously provided a pad in the second signal pad group and a pad in the first power ground pad group; or, in a row, a pad in the first signal pad group and the a power ground pad, and a pad in the second signal pad group and a pad in the first power ground pad group are simultaneously provided in at least one row;
  • the distance between the first signal pad group and the first outgoing line side is greater than the distance between the second signal pad group and the first outgoing line side, and at least one of the first power ground pad groups is soldered
  • the disk is a pad at the same location as at least one of the second power ground pad sets.
  • an embodiment of the present invention further provides a wire bonding package chip, where the wire bonding package chip comprises:
  • An active surface of the bare chip faces away from the substrate, the intermediate layer is disposed between one side of the substrate and the integrated circuit, and the solder ball is disposed on another side of the substrate, a pad in the first power ground pad group in the integrated circuit and a pad in the first signal pad group are bonded to the substrate by the wire bonding, and pass through the trace and metal in the substrate The plane is connected to the solder ball.
  • an embodiment of the present invention further provides a flip-chip package, the flip-chip package comprising:
  • An active surface of the bare chip faces the substrate, the intermediate layer is disposed between one side of the substrate and the integrated circuit, and the solder ball is disposed on another side of the substrate, the middle a through hole is disposed in the layer, the metal bump is disposed in the through hole, and a pad in the second power ground pad group and a pad in the second signal pad group in the integrated circuit pass through
  • the metal bumps are connected to the substrate and connected to the solder balls through traces and metal planes in the substrate.
  • At least one pad group is fixed on an active surface of the bare chip, and each of the at least one pad group includes a first signal pad group, a second signal pad group, and a first power ground pad group And a second power ground pad group, wherein a distance between the pad in the first power ground pad group and the first outgoing line side is less than or equal to a distance between the pad in the first signal pad group and the first outgoing line side, whereby that the pads in the first power ground pad group and the first signal pad group can satisfy the requirements of the wire bonding package, and the pads in the second power ground pad group are greater than the first outgoing side Equal to the distance between the pads in the second signal pad group and the first outgoing line side, so that the pads in the second power ground pad group and the second signal pad group can meet the requirements of flip chip packaging, and thus the above design is adopted.
  • the integrated circuit can be packaged by wire bonding package or flip chip package at the same time, which avoids the need for the pad position of a similarly functioning bare chip in the prior art to be designed twice and twice to meet different requirements.
  • the problem of packaging requirements has been reduced Cycle, saving manufacturing costs.
  • FIG. 1 is a schematic structural view of a wire bonding package chip provided by the present invention.
  • FIG. 2 is a schematic structural view of a flip-chip packaged chip provided by the present invention.
  • FIG. 3 is a schematic structural diagram of an integrated circuit according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a wire bonding package chip according to an embodiment of the present invention.
  • FIG. 5 is a partial enlarged view of the pad group of FIG. 3 according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of another pad group according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of another pad group according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of another pad group according to an embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of another pad group according to an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of another pad group according to an embodiment of the present invention.
  • FIG. 11 is a schematic structural diagram of another pad group according to an embodiment of the present invention.
  • FIG. 12 is a schematic structural diagram of another pad group according to an embodiment of the present invention.
  • FIG. 13 is a schematic structural diagram of another pad group according to an embodiment of the present invention.
  • FIG. 14 is a schematic structural diagram of another pad group according to an embodiment of the present invention.
  • FIG. 15 is a schematic structural diagram of another pad group according to an embodiment of the present invention.
  • 16 is a schematic structural diagram of a wire bonding package chip according to an embodiment of the present invention.
  • FIG. 17 is a schematic structural diagram of a flip-chip packaged chip according to an embodiment of the present invention.
  • the integrated circuit includes:
  • the bare chip 100 and at least one pad group, at least one pad group is fixed on the bare chip 100 On the source side.
  • the active surface refers to the surface of the bare chip having an active area.
  • the bare chip is a semiconductor component completed, the product form before packaging, and becomes an integrated circuit after packaging.
  • the active side of the bare chip may include one or more circuit components such as transistors, memory cells, passive components, and the like.
  • each of the at least one pad group includes a first signal pad group, a second signal pad group, a first power ground pad group, and a second power ground pad group.
  • the first signal pad set and the first power ground pad set are for a wire bond package, and the second signal pad set and the second power ground pad set are for flip chip packaging.
  • the first signal pad group and the second signal pad group respectively comprise at least one signal pad, and the first power ground pad group and the second power ground pad group respectively comprise at least one power ground pad.
  • the pad group 200 includes a first signal pad group 221, a second signal pad group 222, a first power ground pad group 211, and a second power ground pad group 212.
  • the pad group 200A includes a first signal soldering.
  • the disk group 221A, the second signal pad group 222A, the first power ground pad group 211A and the second power ground pad group 212A, and the pad group 200B includes a first signal pad group 221B and a second signal pad group 222B.
  • the first power ground pad group 211A and the second power ground pad group 212B are The first power ground pad group 211A and the second power ground pad group 212B.
  • black squares represent power ground pads
  • white squares represent signal pads
  • dashed boxes represent pad groups (eg, 200, 211, 221, 212, 222). The description will not be repeated later.
  • the distance between the pad in the first power ground pad group and the first outgoing side is less than or equal to the distance between the pad in the first signal pad group and the first outgoing side, and the first outgoing side is the first power ground pad One side of the bare chip through which the group and the first signal pad group are connected at the time of packaging, the first outgoing side corresponds to the first power ground pad group and the first signal pad group, and the second power ground
  • the distance between the pads in the pad group and the first outgoing side is greater than or equal to the distance between the pads in the second signal pad group and the first outgoing side.
  • the distance between the pad in the first power ground pad group 211 and the first outgoing side 110 is smaller than the pad in the first signal pad group 221 and the first outgoing side 110.
  • the distance between the pad in the second power ground pad group 212 and the first outgoing side 110 is greater than the distance between the pad in the second signal pad group 222 and the first outgoing side 110; in the pad group 200A, The distance between the pad in the first power ground pad group 211A and the first outgoing side 110A is equal to the distance between the pad in the first signal pad group 221A and the first outgoing side 110A, and the second power ground pad group 212A Pad and number
  • the distance from the outlet side 110A is greater than the distance between the pad in the second signal pad group 222A and the first outgoing side 110A; in the pad group 200B, the pad in the first power ground pad group 211B and the first outgoing side
  • the distance of 110B is smaller than the distance between the pad in the first signal pad group 221B and the first outgoing side
  • FIG 4 is a schematic view showing the structure of a chip using a wire bonding package, wherein the reference numeral 110 is the first outgoing side.
  • the spacing between any two power ground pads in the second power ground pad group is within the setting range of the electrical specification, and any two of the second signal pad groups.
  • the spacing of the signal pads is within the set range of the electrical specifications.
  • the distance between the two power ground pads or the two signal pads refers to the distance between the two power ground pads or the center of the two signal pads.
  • the above setting range may be greater than or equal to the diameter of the copper pillar in the copper pillar rule, for example, may be 80-200 ⁇ m.
  • the above setting range needs to be determined according to actual needs, and the above content is only an example, and the present invention No restrictions.
  • the shape of the bare chip 100 is generally rectangular, and each side of the rectangle may be provided with a pad group, and each pad group is used for inputting and outputting signals of one module in the bare chip, such as DDR (English) "Double Data Rate”, Chinese “Double Rate Synchronous Dynamic Random Access Memory”) 4 modules, etc.
  • DDR English
  • Double Data Rate Chinese
  • Double Rate Synchronous Dynamic Random Access Memory 4 modules, etc.
  • the shape of the bare chip 100 and the number of pad groups shown in FIG. 3 are by way of example only, and the embodiment of the present invention does not limit the shape of the bare chip 100 and the number of pad groups disposed thereon.
  • the number of pads in the pad group in the integrated circuit shown in FIG. 3 is only an example, and the number of pads can be set according to actual needs.
  • the pads in the first power ground pad group 211 and the first signal pad group 221 are bonded to the substrate 400 through the bonding wires 300, and passed through A trace 401 and a metal plane 402 (shown in cross section) inside the substrate 400 are connected to the solder ball 500.
  • the power path from the pad in the first power ground pad group 211 to the solder ball 500 is minimized, so in the wire bonding package, the first power ground pad group 211 is designed outside.
  • the row that is, is closer to the first outgoing side 110 than the first signal pad group 221, and then connected to the solder ball 500 under the bare chip 100.
  • the wire bonding is avoided, and the first signal pad group 221 is disposed in the inner row, so that the pads in the first signal pad group 221 can be smoothly bonded to the substrate through the wire bonding 300. 400.
  • the width of the trace 401 in the substrate 400 can be increased to form a face, that is, a metal plane 402 (such as a copper surface).
  • the distance between the second power ground pad group in each pad group and the first outgoing line side is greater than or equal to the second signal pad group in the pad group and the first The distance on the outgoing side, that is, the second power ground pad group is designed in the inner row, so that the transmission path between the pad and the solder ball using the flip-chip package power source is the shortest, and the power quality is optimized, wherein the chip structure in the flip-chip package form For details, refer to the description of FIG. 17 later.
  • At least one pad group is fixed on an active surface of the bare chip, and each of the at least one pad group includes a first signal pad group, a second signal pad group, and a first a power ground pad group and a second power ground pad group, wherein a distance between the pads in the first power ground pad group and the first outgoing line side is less than or equal to a pad and a first in the first signal pad group a distance from the line side such that the pads in the first power ground pad group and the first signal pad group can satisfy the requirements of the wire bond package, and the pads in the second power ground pad group and the first The distance on the outgoing side is greater than or equal to the distance between the pads in the second signal pad group and the first outgoing side, such that the pads in the second power ground pad group and the second signal pad group can satisfy the flip-chip package Therefore, the integrated circuit adopting the above design can be packaged by using both the wire bonding package and the flip chip package, thereby avoiding the need for two pad designs of the same function in the prior
  • the pads in each pad group may be arranged in rows, and each row is parallel to the first outgoing line side corresponding to the pad group, which facilitates the design of the pads and circuits;
  • the power ground pad and the signal pad may also adopt other arrangements, which are not limited in the present invention.
  • the pad group 200 on the right side in the integrated circuit of FIG. 3 is taken as an example to describe the setting of the pads in the pad group:
  • FIG. 5 is an enlarged view of the pad group 200 on the right side of the integrated circuit shown in FIG. 3, in which the second signal pad group 222 is in the second power ground pad group 212 and the first Between the signal pad groups 221, the first signal pad group 221 is between the second signal pad group 222 and the first power source ground pad group 211.
  • the second power ground pad group 212 occupies 2 rows
  • the second signal pad group 222 occupies 2 rows
  • the first signal pad group 221 occupies 1 row
  • the first signal pad group 221 occupies 1 row.
  • the number of rows of the pads and the number of rows of the pads in the drawings referred to in the following embodiments are merely examples, and the embodiment of the present invention does not limit this.
  • FIG. 6 is a schematic structural diagram of a pad group 200 in another integrated circuit in which a first power ground pad group 211 is in a first signal pad group 221 and a second power ground pad group. Between 212, the second power ground pad group 212 is between the first power ground pad group 211 and the second signal pad group 222.
  • the first power ground pad group 211, the second power ground pad group 212, the first signal pad group 221, and the second signal pad group 222 are independent of each other.
  • the settings are made and the pads for the wire bond package are independently set between the pads for the flip chip package. For example, in FIG. 5, the areas occupied by the first power ground pad group 211 and the second power ground pad group 212 are separated by a broken line and do not interfere with each other.
  • FIG. 7 is a block diagram showing the structure of a pad group 200 in another integrated circuit in which the first signal pad group 221 is in the second power ground pad group 212 and the second signal pad group 222.
  • the second signal pad group 222 is between the first signal pad group 221 and the first power source ground pad group 211.
  • FIG. 8 is a schematic diagram showing the structure of a pad group 200 in another integrated circuit.
  • the second power ground pad group 212 is in the first signal pad group 221 and the first power ground pad group.
  • the first power ground pad group 211 is between the second power ground pad group 212 and the second signal pad group 222.
  • the first power ground pad group 211, the second power ground pad group 212, the first signal pad group 221, and the second signal pad group 222 are independent of each other. Settings, pads for wire bond packages and pad spacing for flip-chip packages.
  • FIG. 9 is a block diagram showing the structure of a pad group 200 in another integrated circuit in which the first signal pad group 221 and the second signal pad group 222 are in the first power ground pad group. Between the 211 and the second power ground pad group 212, at least one of the first signal pad groups 221 is shared with at least one of the second signal pad groups 222, that is, the first signal pad group 221 At least one of the pads is a pad at the same location as at least one of the second set of signal pads 222. For example, in FIG.
  • the uppermost signal pad may belong to both the first signal pad group 221 and the second signal pad group 222; This signal pad is used when using a wire bond package, which is also used when flip chip packaging is used.
  • first signal pad group 221 and the second signal pad group 222 in the pad group 200 in the integrated circuit provided in FIGS. 5 and 7 are located close to each other, the first signal pad group 221 and the second signal pad group 222 are located.
  • FIG. 10 is a block diagram showing the structure of a pad group 200 in another integrated circuit in which a first power ground pad group 211 and a second power ground pad group 212 are at a first signal pad. Between the group 221 and the second signal pad group 222, at least one of the first power ground pad groups 211 is shared with at least one of the second power ground pad groups 212, that is, the first power ground welding At least one of the pads 211 and at least one of the second power ground pad sets 212 are pads at the same location.
  • the first power ground pad group 211 and the second power ground pad group 212 in the pad group 200 in the integrated circuit provided in FIGS. 6 and 8 are located close to each other, the first power ground pad group 211 and the second power ground The pads in the pad group 212 are not used at the same time, so at least one of the first power ground pad group 211 and the second power ground pad group 212 can be soldered on the basis of the pad group 200 provided in FIG.
  • the discs are shared to provide the integrated circuit provided in FIG. 10 to reduce the complexity of the integrated circuit design while reducing material consumption and processing time.
  • the manner in which the pads are shared may include:
  • all of the pads in the first set of signal pads 221 are shared with the second set of signal pads 222.
  • all of the signal pads are designed to meet the distance requirements of the flip-chip package, and the pads in the first signal pad group 221 are selected therefrom.
  • all of the pads in the second set of signal pads 222 are shared with the first set of signal pads 221.
  • the distance requirements of the flip-chip package are not considered when designing the signal pads, and after the design is completed, the signal pads are spaced apart as the pads in the second signal pad group 222.
  • the two signal pad sharing implementations described above can improve the sharing efficiency of the signal pads, but the above two implementations are by way of example only and are not limiting of the invention.
  • the signal pads or the power source pads in the two pad groups may be shared.
  • the upper pad group 200A and the second power source pad group 212 of the right pad group 200 can be designed to be shared with the center position of the bare chip 100.
  • the power ground pad and the signal pad are simultaneously disposed in the same row, including but not limited to the following specific implementation manners:
  • FIG. 11 is a block diagram showing the structure of a pad group 200 in another integrated circuit similar to the structure of the upper pad group 200A in the integrated circuit shown in FIG. 3, in which the pad group 200 is The pads in the first signal pad group 221 and the pads in the first power ground pad group 211 are simultaneously provided in one row, and the second power ground pad group 212 corresponds to the pad group 200.
  • the distance from the outlet side 110 is greater than the distance between the first power ground pad group 211 and the first outlet side 110. Setting the signal pad and the power ground pad in the same row can save the position of the bare chip surface, thereby reducing the nakedness. Chip area.
  • the pads in the second signal pad group 222 and the pads in the second power ground pad group 212 may be simultaneously provided in one row; or, in a row The pads in the first signal pad group 221 and the pads in the first power ground pad group 211 are simultaneously provided, and the pads in the second signal pad group 222 are simultaneously provided in one row and the first The pads in the second power ground pad group 212.
  • the pads in the second signal pad group 222 and the pads in the second power ground pad group 212 need to meet the distance requirement of the flip chip package, the pads in the second signal pad group 222 and The placement of the pads in the second power ground pad group 212 in the same row does not save the position of the bare chip surface.
  • FIG. 12 is a schematic view showing the structure of a pad group 200 in another integrated circuit in which pads in the first signal pad group 221 and first power ground are simultaneously provided in one row.
  • the pad in the disk group 211, the distance between the second power ground pad group 212 and the first outgoing side 110 corresponding to the pad group 200 is smaller than the distance between the first power ground pad group 211 and the first outgoing line side 110, Setting the signal pad in the same row as the power ground pad can save the position of the bare chip surface and help reduce the bare chip area.
  • the pads in the second signal pad group 222 and the pads in the second power ground pad group 212 may be simultaneously provided in one row; or, in a row The pads in the first signal pad group 221 and the pads in the first power ground pad group 211 are simultaneously provided, and the pads in the second signal pad group 222 are simultaneously provided in one row and the first The pads in the second power ground pad group 212.
  • the pads in the second signal pad group 222 and the pads in the second power ground pad group 212 need to meet the distance requirement of the flip chip package, the pads in the second signal pad group 222 and The placement of the pads in the second power ground pad group 212 in the same row does not save the position of the bare chip surface.
  • the pad group 200 provided in FIGS. 11 and 12 is the pad in the first signal pad group 221 and the first power source pad group 211 in the pad group provided in FIGS. 5 and 6, respectively.
  • the disc design was obtained in the same row.
  • FIG. 13 is a block diagram showing the structure of a pad group 200 in another integrated circuit in which pads in a first signal pad group 221 and a second power source are simultaneously provided in at least one row.
  • the pads in the pad set 212, and the pads in the second set of signal pads 222 and the pads in the first set of power ground pads 211 are simultaneously provided in at least one row.
  • the power ground pad and the signal pad can be disposed in the same row on only one side, for example, the pads in the first signal pad group 221 are simultaneously provided in at least one row. And a pad in the second power ground pad group 212 and a pad in the first power ground pad group 211 are simultaneously provided in at least one row.
  • the pads in the first signal pad group 221 in the same row are spaced apart from the pads in the second power ground pad group 212, and the pads in the second signal pad group 222 in the same row are
  • the pad spacing in the first power ground pad group 211 is set such that the pad in the designed second signal pad group 222 and the pad in the second power ground pad group 212 satisfy the flip chip package.
  • the distance requirements are convenient for design.
  • the distance between the second power ground pad group 212 and the first outgoing side 110 corresponding to the pad group 200 is greater than that of the first power ground pad group 211 and the first outgoing line side 110. distance.
  • Figure 13 is a modification of the structure of the pad group 200 in Figures 7 and 8.
  • FIG. 14 is a schematic structural diagram of a pad group 200 in another integrated circuit in which pads and signal pads in a first power ground pad group 211 are simultaneously disposed in a row.
  • the signal pad may be a pad in the first signal pad group 221, a pad in the second signal pad group 222, or a shared pad of the two.
  • the distance between the second power ground pad group 212 and the first outgoing side 110 corresponding to the pad group 200 is greater than the distance between the first power ground pad group 211 and the first outgoing side 110, in the first signal pad group 221
  • At least one of the pads is a pad at the same location as at least one of the second set of signal pads 222. It is worth noting that it is provided in Figure 14.
  • the signal pads of the same row and the non-same row portions can be simultaneously used, and when the wire bond package is used, only the same row portion can be used. Or a signal pad that is not in the same row.
  • the pads in the first signal pad group 221 and the pads in the second power ground pad group 212 may be simultaneously provided in at least one row; or The pads and signal pads in the first power ground pad group 211 are simultaneously disposed in the row, and the pads in the first signal pad group 221 and the second power ground pad group are simultaneously provided in at least one row. Pad in 212.
  • the pads in the second signal pad group 222 and the pads in the second power ground pad group 212 may be simultaneously provided in one row, or the first power ground welding may be simultaneously provided in one row.
  • the pads and signal pads in the disk group 211, and the pads in the second signal pad group 222 and the pads in the second power ground pad group 212 are simultaneously provided in one row.
  • the pads in the second signal pad group 222 and the pads in the second power ground pad group 212 need to meet the distance requirement of the flip chip package, the pads in the second signal pad group 222 and The placement of the pads in the second power ground pad group 212 in the same row does not save the position of the bare chip surface.
  • FIG. 15 is a schematic structural diagram of a pad group 200 in another integrated circuit in which a first signal pad group 221 and a power ground pad are simultaneously provided in one row, and the power ground is soldered.
  • the disk may be a pad in the first power ground pad group 211, a pad in the second power ground pad group 212, or a shared pad of both.
  • the distance between the first signal pad group 221 and the first outgoing line side 110 corresponding to the pad group 200 is greater than the distance between the second signal pad group 222 and the first outgoing line side 110, and the first power ground pad group 211
  • At least one of the pads is a pad at the same location as at least one of the second set of power ground pads 212.
  • the pad group 200 of the integrated circuit provided in FIG. 15 when the flip chip package is used, the power ground pads of the same row and the non-same row portions can be simultaneously used, and the wire bonding is adopted. When packaging, only the power ground pad of the same row or part of the same row can be used.
  • the pads in the second signal pad group 222 and the pads in the first power ground pad group 211 may be simultaneously provided in at least one row; or The pads in the first signal pad group 221 and the power ground pad are simultaneously disposed in the row, and the pads in the second signal pad group 222 and the first power ground pad group are simultaneously provided in at least one row. Welding in 211 plate.
  • the pads in the second signal pad group 222 and the pads in the second power ground pad group 212 may be simultaneously provided in one row; or, the first signal pads are simultaneously provided in one row.
  • the pads in the group 221 and the power ground pads, and the pads in the second signal pad group 222 and the pads in the second power ground pad group 212 are simultaneously provided in one row.
  • the pads in the second signal pad group 222 and the pads in the second power ground pad group 212 need to meet the distance requirement of the flip chip package, the pads in the second signal pad group 222 and The placement of the pads in the second power ground pad group 212 in the same row does not save the position of the bare chip surface.
  • FIG. 16 is a schematic structural diagram of a wire bonding package chip.
  • the wire bonding package chip includes:
  • the active surface 100a of the bare chip 100 faces away from the substrate 601, the intermediate layer 602 is disposed between one side of the substrate 601 and the integrated circuit 603, and the solder ball 604 is disposed on the other side of the substrate 601, in the integrated circuit 603.
  • the pads in the first power ground pad group 211 and the first signal pad group 221 are bonded to the substrate 601 through the wire 605, and pass through the trace 606 and the metal plane 607 (such as copper surface) in the substrate 601. Connected to the solder ball 604.
  • At least one pad group is fixed on an active surface of the bare chip, and each of the at least one pad group includes a first signal pad group, a second signal pad group, and a first a power ground pad group and a second power ground pad group, wherein a distance between the pads in the first power ground pad group and the first outgoing line side is less than or equal to a pad and a first in the first signal pad group a distance from the line side such that the pads in the first power ground pad group and the first signal pad group can satisfy the requirements of the wire bond package, and the pads in the second power ground pad group and the first The distance on the outgoing side is greater than or equal to the distance between the pads in the second signal pad group and the first outgoing side, such that the pads in the second power ground pad group and the second signal pad group can satisfy the flip-chip package Therefore, the integrated circuit adopting the above design can be packaged by using both wire bonding and flip chip packaging, thereby avoiding the prior art.
  • FIG. 17 is a schematic structural diagram of a flip-chip package chip.
  • the flip-chip package chip includes:
  • the active surface 100a of the bare chip 100 in the integrated circuit 703 faces the substrate 701.
  • the intermediate layer 702 is disposed between one side of the substrate 701 and the integrated circuit 703.
  • the solder ball 704 is disposed on the other side of the substrate 701, and the intermediate layer 702 is disposed.
  • the pads of the second power ground pad group 212 and the second signal pad group 222 in the integrated circuit 703 are connected to the substrate 701 through the metal bumps 705, and pass through the substrate. Traces 706 and metal planes 707 in 701 are connected to solder balls 704.
  • At least one pad group is fixed on an active surface of the bare chip, and each of the at least one pad group includes a first signal pad group, a second signal pad group, and a first a power ground pad group and a second power ground pad group, wherein a distance between the pads in the first power ground pad group and the first outgoing line side is less than or equal to a pad and a first in the first signal pad group a distance from the line side such that the pads in the first power ground pad group and the first signal pad group can satisfy the requirements of the wire bond package, and the pads in the second power ground pad group and the first The distance on the outgoing side is greater than or equal to the distance between the pads in the second signal pad group and the first outgoing side, such that the pads in the second power ground pad group and the second signal pad group can satisfy the flip-chip package Therefore, the integrated circuit adopting the above design can be packaged by using both the wire bonding package and the flip chip package, thereby avoiding the need for two pad designs of the same function in the prior

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Abstract

一种集成电路、引线键合封装芯片及倒装封装芯片，属于半导体技术领域。集成电路包括：裸芯片；至少一个焊盘组，至少一个焊盘组固定在裸芯片的有源面上，至少一个焊盘组中的每个焊盘组包括第一信号焊盘组、第二信号焊盘组、第一电源地焊盘组及第二电源地焊盘组；第一信号焊盘组和第二信号焊盘组分别包括至少一个信号焊盘，第一电源地焊盘组和第二电源地焊盘组分别包括至少一个电源地焊盘；第一电源地焊盘组中的焊盘与第一出线侧的距离小于或等于第一信号焊盘组中的焊盘与第一出线侧的距离，第二电源地焊盘组中的焊盘与第一出线侧的距离大于或等于第二信号焊盘组中的焊盘与第一出线侧的距离。

Description

一种集成电路、引线键合封装芯片及倒装封装芯片
本申请要求于2015年4月17日提交中国专利局、申请号为201510185457.9、发明名称为“一种集成电路、引线键合封装芯片及倒装封装芯片”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体技术领域，特别涉及一种集成电路、引线键合封装芯片及倒装封装芯片。
背景技术
随着电子信息技术的日益发展，集成电路一方面朝着高性能的方向发展，另一方面朝着轻薄短小的方向发展。目前常用的集成电路方式包括引线键合封装和倒装封装两种。
如图1所示，在引线键合封装中，通常将信号焊盘11设计在裸芯片10的内排，电源地焊盘12设计在裸芯片10的外排。如图2所示，在倒装封装中，焊盘的位置则刚好与引线键合封装相反，通常是将电源地焊盘22设计在裸芯片20的内排，信号焊盘21设计在裸芯片20的外排。
在对某一功能的裸芯片进行封装时，由于在不同应用场景中需要的封装方式不同，因此可能需要对一颗功能相同的裸芯片的焊盘位置进行两次设计、两次制造，来满足不同封装要求，增加了开发周期和制造成本。
发明内容
本发明实施例提供了一种集成电路、引线键合封装芯片及倒装封装芯片，该集成电路可以同时满足引线键合封装和倒装封装两种封装要求。所述技术方案如下：
第一方面，本发明实施例提供了一种集成电路，包括：
裸芯片；及
至少一个焊盘组，所述至少一个焊盘组固定在所述裸芯片的有源面上，所述至少一个焊盘组中的每个焊盘组包括第一信号焊盘组、第二信号焊盘 组、第一电源地焊盘组及第二电源地焊盘组；
其中，所述第一信号焊盘组和所述第二信号焊盘组分别包括至少一个信号焊盘，所述第一电源地焊盘组和所述第二电源地焊盘组分别包括至少一个电源地焊盘；
所述第一电源地焊盘组中的焊盘与第一出线侧的距离小于或等于所述第一信号焊盘组中的焊盘与所述第一出线侧的距离，所述第一出线侧为所述第一电源地焊盘组及所述第一信号焊盘组在封装时连接的打线所经过的所述裸芯片的一个侧边，所述第二电源地焊盘组中的焊盘与所述第一出线侧的距离大于或等于所述第二信号焊盘组中的焊盘与所述第一出线侧的距离。
在本发明实施例的一种实现方式中，所述每个焊盘组中的焊盘按排设置，且每一排与所述第一出线侧平行。
在本发明实施例的另一种实现方式中，在每一排中仅设有所述电源地焊盘或所述信号焊盘。
在本发明实施例的另一种实现方式中，所述第二信号焊盘组处于所述第二电源地焊盘组与所述第一信号焊盘组之间，所述第一信号焊盘组处于所述第二信号焊盘组与所述第一电源地焊盘组之间；或者，
所述第一电源地焊盘组处于所述第一信号焊盘组与所述第二电源地焊盘组之间，所述第二电源地焊盘组处于所述第一电源地焊盘组与所述第二信号焊盘组之间。
在本发明实施例的另一种实现方式中，所述第一信号焊盘组处于所述第二电源地焊盘组与所述第二信号焊盘组之间，所述第二信号焊盘组处于所述第一信号焊盘组与所述第一电源地焊盘组之间；或者，
所述第二电源地焊盘组处于所述第一信号焊盘组与所述第一电源地焊盘组之间，所述第一电源地焊盘组处于所述第二电源地焊盘组与所述第二信号焊盘组之间。
在本发明实施例的另一种实现方式中，所述第一信号焊盘组和所述第二信号焊盘组处在所述第一电源地焊盘组与所述第二电源地焊盘组之间，所述第一信号焊盘组中的至少一个焊盘与所述第二信号焊盘组中的至少一个焊盘为同一个位置上的焊盘；或者，
所述第一电源地焊盘组和所述第二电源地焊盘组处在所述第一信号焊盘组与所述第二信号焊盘组之间，所述第一电源地焊盘组中的至少一个焊盘 与所述第二电源地焊盘组中的至少一个焊盘为同一个位置上的焊盘。
在本发明实施例的另一种实现方式中，在同一排中同时设有所述信号焊盘和所述电源地焊盘。
在本发明实施例的另一种实现方式中，在一排中同时设有所述第一信号焊盘组中的焊盘和所述第一电源地焊盘组中的焊盘，所述第二电源地焊盘组与所述第一出线侧的距离大于所述第一电源地焊盘组与所述第一出线侧的距离；或者，
在一排中同时设有所述第一信号焊盘组中的焊盘和所述第一电源地焊盘组中的焊盘，所述第一电源地焊盘组与所述第一出线侧的距离大于所述第二电源地焊盘组与所述第一出线侧的距离。
在本发明实施例的另一种实现方式中，在至少一排中同时设有所述第一信号焊盘组中的焊盘与所述第二电源地焊盘组中的焊盘；或者，在至少一排中同时设有所述第二信号焊盘组中的焊盘与所述第一电源地焊盘组中的焊盘；或者，在至少一排中同时设有所述第一信号焊盘组中的焊盘与所述第二电源地焊盘组中的焊盘，且在至少一排中同时设有所述第二信号焊盘组中的焊盘与所述第一电源地焊盘组中的焊盘；
所述第二电源地焊盘组与所述第一出线侧的距离大于所述第一电源地焊盘组与所述第一出线侧的距离。
在本发明实施例的另一种实现方式中，在一排中同时设有所述第一电源地焊盘组中的焊盘和所述信号焊盘；或者在至少一排中同时设有所述第一信号焊盘组中的焊盘与所述第二电源地焊盘组中的焊盘；或者，在一排中同时设有所述第一电源地焊盘组中的焊盘和所述信号焊盘，且在至少一排中同时设有所述第一信号焊盘组中的焊盘与所述第二电源地焊盘组中的焊盘；
所述第二电源地焊盘组与所述第一出线侧的距离大于所述第一电源地焊盘组与所述第一出线侧的距离，所述第一信号焊盘组中的至少一个焊盘与所述第二信号焊盘组中的至少一个焊盘为同一个位置上的焊盘。
在本发明实施例的另一种实现方式中，在一排中同时设有所述第一信号焊盘组中的焊盘和所述电源地焊盘；或者在至少一排中同时设有所述第二信号焊盘组中的焊盘与所述第一电源地焊盘组中的焊盘；或者，在一排中同时设有所述第一信号焊盘组中的焊盘和所述电源地焊盘，且在至少一排中同时设有所述第二信号焊盘组中的焊盘与所述第一电源地焊盘组中的焊盘；
所述第一信号焊盘组与所述第一出线侧的距离大于所述第二信号焊盘组与所述第一出线侧的距离，所述第一电源地焊盘组中的至少一个焊盘与所述第二电源地焊盘组中的至少一个焊盘为同一个位置上的焊盘。
另一方面，本发明实施例还提供了一种引线键合封装芯片，所述引线键合封装芯片包括：
基板、中间层、如前所述的集成电路、焊球和打线；
所述裸芯片的有源面背向所述基板，所述中间层设于所述基板的一侧与所述集成电路之间，所述焊球设置在所述基板的另一侧，所述集成电路中的第一电源地焊盘组中的焊盘和第一信号焊盘组中的焊盘通过所述打线键合至所述基板中，并通过所述基板内的走线及金属平面与所述焊球连接。
另一方面，本发明实施例还提供了一种倒装封装芯片，所述倒装封装芯片包括：
基板、中间层、如前所述的集成电路、焊球和金属凸块；
所述裸芯片的有源面朝向所述基板，所述中间层设于所述基板的一侧与所述集成电路之间，所述焊球设置在所述基板的另一侧，所述中间层上设有通孔，所述金属凸块设于所述通孔内，所述集成电路中的第二电源地焊盘组中的焊盘和第二信号焊盘组中的焊盘通过所述金属凸块连接至所述基板，并通过所述基板内的走线及金属平面与所述焊球连接。
本发明实施例提供的技术方案带来的有益效果是：
在裸芯片的有源面上固定有至少一个焊盘组，至少一个焊盘组中的每个焊盘组包括第一信号焊盘组、第二信号焊盘组、第一电源地焊盘组及第二电源地焊盘组，其中，第一电源地焊盘组中的焊盘与第一出线侧的距离小于或等于第一信号焊盘组中的焊盘与第一出线侧的距离，从而使得第一电源地焊盘组和第一信号焊盘组中的焊盘可以满足引线键合封装的要求，而第二电源地焊盘组中的焊盘与第一出线侧的距离大于或等于第二信号焊盘组中的焊盘与第一出线侧的距离，使得第二电源地焊盘组和第二信号焊盘组中的焊盘可以满足倒装封装的要求，因此采用上述设计的集成电路可以同时采用引线键合封装、倒装封装两种方式进行封装，避免了现有技术中一颗功能相同的裸芯片的焊盘位置需要经过两次设计、两次制造，来满足不同封装要求的问题，减少了开发周期，节省了制造成本。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明提供的一种引线键合封装芯片的结构示意图；
图2是本发明提供的一种倒装封装芯片的结构示意图；
图3是本发明实施例提供的一种集成电路的结构示意图；
图4是本发明实施例提供的一种引线键合封装芯片的结构示意图；
图5是本发明实施例提供的图3中的焊盘组的局部放大图；
图6是本发明实施例提供的另一种焊盘组的结构示意图；
图7是本发明实施例提供的另一种焊盘组的结构示意图；
图8是本发明实施例提供的另一种焊盘组的结构示意图；
图9是本发明实施例提供的另一种焊盘组的结构示意图；
图10是本发明实施例提供的另一种焊盘组的结构示意图；
图11是本发明实施例提供的另一种焊盘组的结构示意图；
图12是本发明实施例提供的另一种焊盘组的结构示意图；
图13是本发明实施例提供的另一种焊盘组的结构示意图；
图14是本发明实施例提供的另一种焊盘组的结构示意图；
图15是本发明实施例提供的另一种焊盘组的结构示意图；
图16是本发明实施例提供的一种引线键合封装芯片的结构示意图；
图17是本发明实施例提供的一种倒装封装芯片的结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。
图3提供了一种集成电路的结构示意图，在微电子领域中，“裸芯片”、“集成电路”、“单片器件”、“半导体器件”以及“微电子器件”等经常互换使用，本发明适用于所有上述这些器件的封装，参见图3，该集成电路包括：
裸芯片100及至少一个焊盘组，至少一个焊盘组固定在裸芯片100的有 源面上。其中有源面是指裸芯片具有有源区域的面。其中，裸芯片是半导体元器件制造完成，封装之前的产品形式，封装后成为集成电路。裸芯片的有源面可以包括一个或多个电路部件，诸如晶体管、存储器单元、无源部件，等等。
其中，至少一个焊盘组中的每个焊盘组包括第一信号焊盘组、第二信号焊盘组、第一电源地焊盘组及第二电源地焊盘组。第一信号焊盘组和第一电源地焊盘组用于引线键合封装，第二信号焊盘组和第二电源地焊盘组用于倒装封装。其中，第一信号焊盘组和第二信号焊盘组分别包括至少一个信号焊盘，第一电源地焊盘组和第二电源地焊盘组分别包括至少一个电源地焊盘。
如图3所示，在裸芯片100的有源面上固定有三个焊盘组，按照其位置分别为处于右侧的焊盘组200、处于上方的焊盘组200A和处于左侧的焊盘组200B。其中，焊盘组200包括第一信号焊盘组221、第二信号焊盘组222、第一电源地焊盘组211及第二电源地焊盘组212，焊盘组200A包括第一信号焊盘组221A、第二信号焊盘组222A、第一电源地焊盘组211A及第二电源地焊盘组212A，焊盘组200B包括第一信号焊盘组221B、第二信号焊盘组222B、第一电源地焊盘组211A及第二电源地焊盘组212B。在图3及本发明实施例提到的其他附图中，黑色方块代表电源地焊盘，白色方块代表信号焊盘，虚线框代表焊盘组(如200、211、221、212、222)，后文不再重复说明。
第一电源地焊盘组中的焊盘与第一出线侧的距离小于或等于第一信号焊盘组中的焊盘与第一出线侧的距离，第一出线侧为第一电源地焊盘组及第一信号焊盘组在封装时连接的打线所经过的裸芯片的一个侧边，第一出线侧与第一电源地焊盘组及第一信号焊盘组对应，第二电源地焊盘组中的焊盘与第一出线侧的距离大于或等于第二信号焊盘组中的焊盘与第一出线侧的距离。
如图3所示，焊盘组200中，第一电源地焊盘组211中的焊盘与第一出线侧110的距离小于第一信号焊盘组221中的焊盘与第一出线侧110的距离，第二电源地焊盘组212中的焊盘与第一出线侧110的距离大于第二信号焊盘组222中的焊盘与第一出线侧110的距离；焊盘组200A中，第一电源地焊盘组211A中的焊盘与第一出线侧110A的距离等于第一信号焊盘组221A中的焊盘与第一出线侧110A的距离，第二电源地焊盘组212A中的焊盘与第 一出线侧110A的距离大于第二信号焊盘组222A中的焊盘与第一出线侧110A的距离；焊盘组200B中，第一电源地焊盘组211B中的焊盘与第一出线侧110B的距离小于第一信号焊盘组221B中的焊盘与第一出线侧110B的距离，第二电源地焊盘组212B中的焊盘与第一出线侧110B的距离等于第二信号焊盘组222B中的焊盘与第一出线侧110B的距离。
图4提供了一种采用引线键合封装的芯片的结构示意图，其中标号110所示即为第一出线侧。
为了符合电气规范，满足倒装封装的要求，容易知道，第二电源地焊盘组中任意两个电源地焊盘的间距在电器规范的设定范围内，第二信号焊盘组中任意两个信号焊盘的间距在电器规范的设定范围内。
其中，两个电源地焊盘或者两个信号焊盘的间距是指两个电源地焊盘或者两个信号焊盘中心间的距离。上述设定范围可以大于等于copper pillar(铜圆柱焊球)规则中的copper pillar直径，例如可以为80-200μm，当然上述设定范围需要根据实际需要确定，上述内容仅作为举例，本发明对此不做限制。
如图3所示，裸芯片100的形状通常为矩形，矩形的每一侧均可以设置一个焊盘组，每个焊盘组供裸芯片中的一个模块进行信号的输入输出，例如DDR(英文“Double Data Rate”，中文“双倍速率同步动态随机存储器”)4模块等。图3所示裸芯片100的形状和焊盘组的数量仅作为举例，本发明实施例对裸芯片100的形状和其上设置的焊盘组的数量不做限制。
容易知道，图3中所示的集成电路中焊盘组中焊盘的数量仅作为示例，焊盘的数量可以根据实际需要进行设置。
如图4所示，在采用引线键合封装形成的芯片中，第一电源地焊盘组211和第一信号焊盘组221中的焊盘通过打线300键合至基板400中，并通过基板400内部的走线401和金属平面402(图示为其截面)与焊球500连接。为了保证电源电感最小，要使得从第一电源地焊盘组211中的焊盘到焊球500的电源路径最小，所以在引线键合封装中，会将第一电源地焊盘组211设计在外排，即相比于第一信号焊盘组221靠近第一出线侧110，然后与裸芯片100下方的焊球500连接。而为了满足打线规则的要求，避免打线交叉，将第一信号焊盘组221设置在内排，保证第一信号焊盘组221中的焊盘可以顺利的通过打线300键合到基板400上。其中，为了使打线300传输的信号 更好的传输到焊球500中，可以增加基板400内走线401的宽度，使之形成一个面，即金属平面402(如铜皮面)。
另外，图3提供的集成电路中，每个焊盘组中的第二电源地焊盘组与该第一出线侧的距离大于或等于焊盘组中的第二信号焊盘组与该第一出线侧的距离，即将第二电源地焊盘组设计在内排，使得在采用倒装封装电源地焊盘和焊球间传输路径最短，保证电源质量最优，其中倒装封装形式的芯片结构可以具体参见后文对于图17的描述。
本发明实施例中，在裸芯片的有源面上固定有至少一个焊盘组，至少一个焊盘组中的每个焊盘组包括第一信号焊盘组、第二信号焊盘组、第一电源地焊盘组及第二电源地焊盘组，其中，第一电源地焊盘组中的焊盘与第一出线侧的距离小于或等于第一信号焊盘组中的焊盘与第一出线侧的距离，从而使得第一电源地焊盘组和第一信号焊盘组中的焊盘可以满足引线键合封装的要求，而第二电源地焊盘组中的焊盘与第一出线侧的距离大于或等于第二信号焊盘组中的焊盘与第一出线侧的距离，使得第二电源地焊盘组和第二信号焊盘组中的焊盘可以满足倒装封装的要求，因此采用上述设计的集成电路可以同时采用引线键合封装、倒装封装两种方式进行封装，避免了现有技术中一颗功能相同的裸芯片的焊盘位置需要经过两次设计、两次制造，来满足不同封装要求的问题，减少了开发周期，节省了制造成本。
在本发明实施例中，每个焊盘组中的焊盘可以按排设置，且每一排均与该焊盘组对应的第一出线侧平行，便于焊盘及电路的设计；在其他实施例中，电源地焊盘和信号焊盘也可以采用其他排列方式，本发明对此不做限制。
下面对本发明实施例中，以图3中集成电路中处于右侧的焊盘组200为例，对焊盘组内的焊盘的设置进行说明：
在本发明实施例的一种实现方式中，在每一排中仅设有电源地焊盘或信号焊盘，包括但不限于下列几种具体实现方式：
图5是图3所示的集成电路中处于右侧的焊盘组200的放大图，在该焊盘组200中，第二信号焊盘组222处于第二电源地焊盘组212与第一信号焊盘组221之间，第一信号焊盘组221处于第二信号焊盘组222与第一电源地焊盘组211之间。
在图5所示的集成电路中，第二电源地焊盘组212占2排，第二信号焊盘组222占2排，第一信号焊盘组221占1排，第一信号焊盘组221占1排。 当然，这里各个焊盘所占的排数及实施例后文涉及的附图中各个焊盘所占的排数仅为举例，本发明实施例对此不做限制。
图6提供了另一种集成电路中焊盘组200的结构示意图，在该焊盘组200中，第一电源地焊盘组211处于第一信号焊盘组221与第二电源地焊盘组212之间，第二电源地焊盘组212处于第一电源地焊盘组211与第二信号焊盘组222之间。
在图5和图6提供的焊盘组200中，第一电源地焊盘组211、第二电源地焊盘组212、第一信号焊盘组221和第二信号焊盘组222间相互独立设置，且用于引线键合封装的焊盘与用于倒装封装的焊盘之间独立设置。例如在图5中，第一电源地焊盘组211和第二电源地焊盘组212各自所占的区域通过虚线分隔开，互不干扰。
图7提供了另一种集成电路中焊盘组200的结构示意图，在该焊盘组200中，第一信号焊盘组221处于第二电源地焊盘组212与第二信号焊盘组222之间，第二信号焊盘组222处于第一信号焊盘组221与第一电源地焊盘组211之间。
图8提供了另一种集成电路中焊盘组200的结构示意图，在该焊盘组200中，第二电源地焊盘组212处于第一信号焊盘组221与第一电源地焊盘组211之间，第一电源地焊盘组211处于第二电源地焊盘组212与第二信号焊盘组222之间。
在图7和图8提供的焊盘组200中，第一电源地焊盘组211、第二电源地焊盘组212、第一信号焊盘组221和第二信号焊盘组222间相互独立设置，用于引线键合封装的焊盘与用于倒装封装的焊盘间隔设置。
图9提供了另一种集成电路中焊盘组200的结构示意图，在该焊盘组200中，第一信号焊盘组221和第二信号焊盘组222处在第一电源地焊盘组211与第二电源地焊盘组212之间，第一信号焊盘组221中的至少一个焊盘与第二信号焊盘组222中的至少一个焊盘共用，即第一信号焊盘组221中的至少一个焊盘与第二信号焊盘组222中的至少一个焊盘为同一个位置上的焊盘。例如，在图9中，靠近第一出线侧110的一排信号焊盘中，最上方的信号焊盘可以既属于第一信号焊盘组221，又属于第二信号焊盘组222；即当采用引线键合封装时，该信号焊盘被使用，当采用倒装封装时，该信号焊盘亦被使用。
由于图5和图7提供的集成电路中焊盘组200中第一信号焊盘组221与第二信号焊盘组222位置靠近，而第一信号焊盘组221与第二信号焊盘组222中的焊盘不会同时使用，故在图7提供的焊盘组200的基础上可以对第一信号焊盘组221与第二信号焊盘组222中的至少一个焊盘进行共用，从而得到图9提供的集成电路，用以减小集成电路设计复杂度，同时减少材料消耗和加工时间。
图10提供了另一种集成电路中焊盘组200的结构示意图，在该焊盘组200中，第一电源地焊盘组211和第二电源地焊盘组212处在第一信号焊盘组221与第二信号焊盘组222之间，第一电源地焊盘组211中的至少一个焊盘与第二电源地焊盘组212中的至少一个焊盘共用，即第一电源地焊盘组211中的至少一个焊盘与第二电源地焊盘组212中的至少一个焊盘为同一个位置上的焊盘。
由于图6和图8提供的集成电路中焊盘组200中第一电源地焊盘组211与第二电源地焊盘组212位置靠近，而第一电源地焊盘组211与第二电源地焊盘组212中的焊盘不会同时使用，故在图8提供的焊盘组200的基础上可以对第一电源地焊盘组211与第二电源地焊盘组212中的至少一个焊盘进行共用，从而得到图10提供的集成电路，用以减小集成电路设计复杂度，同时减少材料消耗和加工时间。
在图9和和图10提供的焊盘组200中，焊盘共用的方式可以包括：
在一种实现方式中，所有第一信号焊盘组221中的焊盘均与第二信号焊盘组222共用。例如，将所有信号焊盘均设计成满足倒装封装的距离需求的焊盘，第一信号焊盘组221中的焊盘从中选取即可。
在另一种实现方式中，所有第二信号焊盘组222中的焊盘均与第一信号焊盘组221共用。例如，在设计信号焊盘时不考虑倒装封装的距离需求，而在设计完成后，间隔选取信号焊盘作为第二信号焊盘组222中的焊盘。
上述两种信号焊盘共用实现方式可以提高信号焊盘的共用效率，但上述两种实现方式仅作为举例，并不作为本发明的限制。
进一步地，在本发明实施例中，除了可以将同一焊盘组200内的焊盘进行共用外，还可以将两个焊盘组中的信号焊盘或电源地焊盘进行共用。如图3所示，可以将上方的焊盘组200A和右侧的焊盘组200的第二电源地焊盘组212设计到裸芯片100的中心位置进行共用。
在本发明实施例的另一种实现方式中，在同一排中同时设有电源地焊盘和信号焊盘，包括但不限于下列几种具体实现方式：
图11提供了另一种集成电路中焊盘组200的结构示意图，该焊盘组200与图3所示的集成电路中处于上方的焊盘组200A的结构类似，在该焊盘组200中，在一排中同时设有第一信号焊盘组221中的焊盘和第一电源地焊盘组211中的焊盘，第二电源地焊盘组212与该焊盘组200对应的第一出线侧110的距离大于第一电源地焊盘组211与该第一出线侧110的距离，将信号焊盘与电源地焊盘同排设置可以节省裸芯片表面的位置，有利于减小裸芯片面积。
根据图11提供的结构示意图，容易想到，还可以在一排中同时设有第二信号焊盘组222中的焊盘和第二电源地焊盘组212中的焊盘；或者，在一排中同时设有第一信号焊盘组221中的焊盘和第一电源地焊盘组211中的焊盘，且在一排中同时设有第二信号焊盘组222中的焊盘和第二电源地焊盘组212中的焊盘。但由于第二信号焊盘组222中的焊盘和第二电源地焊盘组212中的焊盘均需要满足倒装封装的距离需求，因此将第二信号焊盘组222中的焊盘和第二电源地焊盘组212中的焊盘同排设置并不能节省裸芯片表面的位置。
图12提供了另一种集成电路中焊盘组200的结构示意图，在该焊盘组200中，在一排中同时设有第一信号焊盘组221中的焊盘和第一电源地焊盘组211中的焊盘，第二电源地焊盘组212与该焊盘组200对应的第一出线侧110的距离小于第一电源地焊盘组211与该第一出线侧110的距离，将信号焊盘与电源地焊盘同排设置可以节省裸芯片表面的位置，有利于减小裸芯片面积。
根据图12提供的结构示意图，容易想到，还可以在一排中同时设有第二信号焊盘组222中的焊盘和第二电源地焊盘组212中的焊盘；或者，在一排中同时设有第一信号焊盘组221中的焊盘和第一电源地焊盘组211中的焊盘，且在一排中同时设有第二信号焊盘组222中的焊盘和第二电源地焊盘组212中的焊盘。但由于第二信号焊盘组222中的焊盘和第二电源地焊盘组212中的焊盘均需要满足倒装封装的距离需求，因此将第二信号焊盘组222中的焊盘和第二电源地焊盘组212中的焊盘同排设置并不能节省裸芯片表面的位置。
图11和图12提供的焊盘组200，分别是将图5和图6提供的焊盘组中的第一信号焊盘组221中的焊盘和第一电源地焊盘组211中的焊盘设计在同一排得到的。
容易知道，在一排中同时设置信号焊盘和电源地焊盘的实现方式，特别适用于焊盘数量较少的场景。
图13提供了另一种集成电路中焊盘组200的结构示意图，在该焊盘组200中，在至少一排中同时设有第一信号焊盘组221中的焊盘与第二电源地焊盘组212中的焊盘，且在至少一排中同时设有第二信号焊盘组222中的焊盘与第一电源地焊盘组211中的焊盘。
根据图13提供的结构示意图，容易想到，还可以只在一侧将电源地焊盘与信号焊盘同排设置，例如在至少一排中同时设有第一信号焊盘组221中的焊盘与第二电源地焊盘组212中的焊盘；或者，在至少一排中同时设有第二信号焊盘组222中的焊盘与第一电源地焊盘组211中的焊盘。
将信号焊盘与电源地焊盘同排设置可以节省裸芯片表面的位置，有利于减小裸芯片面积。
优选地，同一排中的第一信号焊盘组221中的焊盘与第二电源地焊盘组212中的焊盘间隔设置，同一排中的第二信号焊盘组222中的焊盘与第一电源地焊盘组211中的焊盘间隔设置，间隔设置可以使得设计出的第二信号焊盘组222中的焊盘和第二电源地焊盘组212中的焊盘满足倒装封装的距离要求，方便设计。
另外，在该焊盘组200中，第二电源地焊盘组212与该焊盘组200对应的第一出线侧110的距离大于第一电源地焊盘组211与该第一出线侧110的距离。
图13是根据图7和图8中焊盘组200的结构变形得到的。
图14提供了另一种集成电路中焊盘组200的结构示意图，在该焊盘组200中，在一排中同时设有第一电源地焊盘组211中的焊盘和信号焊盘，该信号焊盘可以是第一信号焊盘组221中的焊盘，也可以是第二信号焊盘组222中的焊盘，还可以是二者的共用焊盘。第二电源地焊盘组212与该焊盘组200对应的第一出线侧110的距离大于第一电源地焊盘组211与该第一出线侧110的距离，第一信号焊盘组221中的至少一个焊盘与第二信号焊盘组222中的至少一个焊盘为同一个位置上的焊盘。值得说明的是，在图14提供 的集成电路中焊盘组200中，采用倒装封装时，可以同时采用同排设置部分和非同排设置部分的信号焊盘，而在采用引线键合封装时，只能采用同排设置部分或非同排设置部分的信号焊盘。
根据图14提供的结构示意图，容易想到，还可以在至少一排中同时设有第一信号焊盘组221中的焊盘和第二电源地焊盘组212中的焊盘；或者，在一排中同时设有第一电源地焊盘组211中的焊盘和信号焊盘，且在至少一排中同时设有第一信号焊盘组221中的焊盘和第二电源地焊盘组212中的焊盘。
将信号焊盘与电源地焊盘同排设置可以节省裸芯片表面的位置，有利于减小裸芯片面积。
另外，还可以在一排中同时设有第二信号焊盘组222中的焊盘和第二电源地焊盘组212中的焊盘，或者，在一排中同时设有第一电源地焊盘组211中的焊盘和信号焊盘，且在一排中同时设有第二信号焊盘组222中的焊盘和第二电源地焊盘组212中的焊盘。但由于第二信号焊盘组222中的焊盘和第二电源地焊盘组212中的焊盘均需要满足倒装封装的距离需求，因此将第二信号焊盘组222中的焊盘和第二电源地焊盘组212中的焊盘同排设置并不能节省裸芯片表面的位置。
图15提供了另一种集成电路中焊盘组200的结构示意图，在该焊盘组200中，在一排中同时设有第一信号焊盘组221和电源地焊盘，该电源地焊盘可以是第一电源地焊盘组211中的焊盘，也可以是第二电源地焊盘组212中的焊盘，还可以是二者的共用焊盘。第一信号焊盘组221与该焊盘组200对应的第一出线侧110的距离大于第二信号焊盘组222与该第一出线侧110的距离，第一电源地焊盘组211中的至少一个焊盘与第二电源地焊盘组212中的至少一个焊盘为同一个位置上的焊盘。值得说明的是，在图15提供的集成电路中焊盘组200中，采用倒装封装时，可以同时采用同排设置部分和非同排设置部分的电源地焊盘，而在采用引线键合封装时，只能采用同排设置部分或非同排设置部分的电源地焊盘。
根据图15提供的结构示意图，容易想到，还可以在至少一排中同时设有第二信号焊盘组222中的焊盘和第一电源地焊盘组211中的焊盘；或者，在一排中同时设有第一信号焊盘组221中的焊盘和电源地焊盘，且在至少一排中同时设有第二信号焊盘组222中的焊盘和第一电源地焊盘组211中的焊 盘。
将信号焊盘与电源地焊盘同排设置可以节省裸芯片表面的位置，有利于减小裸芯片面积。
另外，还可以在一排中同时设有第二信号焊盘组222中的焊盘和第二电源地焊盘组212中的焊盘；或者，在一排中同时设有第一信号焊盘组221中的焊盘和电源地焊盘，且在一排中同时设有第二信号焊盘组222中的焊盘和第二电源地焊盘组212中的焊盘。但由于第二信号焊盘组222中的焊盘和第二电源地焊盘组212中的焊盘均需要满足倒装封装的距离需求，因此将第二信号焊盘组222中的焊盘和第二电源地焊盘组212中的焊盘同排设置并不能节省裸芯片表面的位置。
图14和图15分别是根据图9和图10中焊盘组200的结构变形得到的。
容易知道，前述图5-图15提供的焊盘组200的结构仅为举例，并不能作为对本发明的限制。
图16提供了一种引线键合封装芯片的结构示意图，参见图16，引线键合封装芯片包括：
基板601、中间层602、如图3～15任一幅所对应的集成电路603、焊球604和打线605；
集成电路603中裸芯片100的有源面100a背向基板601，中间层602设于基板601的一侧与集成电路603之间，焊球604设置在基板601的另一侧，集成电路603中第一电源地焊盘组211和第一信号焊盘组221中的焊盘通过打线605键合至基板601中，并通过基板601内的走线606及金属平面607(如铜皮面)与焊球604连接。
本发明实施例中，在裸芯片的有源面上固定有至少一个焊盘组，至少一个焊盘组中的每个焊盘组包括第一信号焊盘组、第二信号焊盘组、第一电源地焊盘组及第二电源地焊盘组，其中，第一电源地焊盘组中的焊盘与第一出线侧的距离小于或等于第一信号焊盘组中的焊盘与第一出线侧的距离，从而使得第一电源地焊盘组和第一信号焊盘组中的焊盘可以满足引线键合封装的要求，而第二电源地焊盘组中的焊盘与第一出线侧的距离大于或等于第二信号焊盘组中的焊盘与第一出线侧的距离，使得第二电源地焊盘组和第二信号焊盘组中的焊盘可以满足倒装封装的要求，因此采用上述设计的集成电路可以同时采用引线键合封装、倒装封装两种方式进行封装，避免了现有技术 中一颗功能相同的裸芯片的焊盘位置需要经过两次设计、两次制造，来满足不同封装要求的问题，减少了开发周期，节省了制造成本。
图17提供了一种倒装封装芯片的结构示意图，参见图17，倒装封装芯片包括：
基板701、中间层702、如图3～15任一幅所对应的集成电路703、焊球704和金属凸块705(如copper pillar)；
集成电路703中裸芯片100的有源面100a朝向基板701，中间层702设于基板701的一侧与集成电路703之间，焊球704设置在基板701的另一侧，中间层702上设有通孔，金属凸块705设于通孔内，集成电路703中第二电源地焊盘组212和第二信号焊盘组222的焊盘通过金属凸块705连接至基板701，并通过基板701内的走线706及金属平面707与焊球704连接。
本发明实施例中，在裸芯片的有源面上固定有至少一个焊盘组，至少一个焊盘组中的每个焊盘组包括第一信号焊盘组、第二信号焊盘组、第一电源地焊盘组及第二电源地焊盘组，其中，第一电源地焊盘组中的焊盘与第一出线侧的距离小于或等于第一信号焊盘组中的焊盘与第一出线侧的距离，从而使得第一电源地焊盘组和第一信号焊盘组中的焊盘可以满足引线键合封装的要求，而第二电源地焊盘组中的焊盘与第一出线侧的距离大于或等于第二信号焊盘组中的焊盘与第一出线侧的距离，使得第二电源地焊盘组和第二信号焊盘组中的焊盘可以满足倒装封装的要求，因此采用上述设计的集成电路可以同时采用引线键合封装、倒装封装两种方式进行封装，避免了现有技术中一颗功能相同的裸芯片的焊盘位置需要经过两次设计、两次制造，来满足不同封装要求的问题，减少了开发周期，节省了制造成本。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (13)

  1. 一种集成电路，其特征在于，包括：
    裸芯片；及
    至少一个焊盘组，所述至少一个焊盘组固定在所述裸芯片的有源面上，所述至少一个焊盘组中的每个焊盘组包括第一信号焊盘组、第二信号焊盘组、第一电源地焊盘组及第二电源地焊盘组；
    其中，所述第一信号焊盘组和所述第二信号焊盘组分别包括至少一个信号焊盘，所述第一电源地焊盘组和所述第二电源地焊盘组分别包括至少一个电源地焊盘；
    所述第一电源地焊盘组中的焊盘与第一出线侧的距离小于或等于所述第一信号焊盘组中的焊盘与所述第一出线侧的距离，所述第一出线侧为所述第一电源地焊盘组及所述第一信号焊盘组在封装时连接的打线所经过的所述裸芯片的一个侧边，所述第二电源地焊盘组中的焊盘与所述第一出线侧的距离大于或等于所述第二信号焊盘组中的焊盘与所述第一出线侧的距离。
  2. 根据权利要求1所述集成电路，其特征在于，所述每个焊盘组中的焊盘按排设置，且每一排与所述第一出线侧平行。
  3. 根据权利要求2所述集成电路，其特征在于，在每一排中仅设有所述电源地焊盘或所述信号焊盘。
  4. 根据权利要求3所述集成电路，其特征在于，所述第二信号焊盘组处于所述第二电源地焊盘组与所述第一信号焊盘组之间，所述第一信号焊盘组处于所述第二信号焊盘组与所述第一电源地焊盘组之间；或者，
    所述第一电源地焊盘组处于所述第一信号焊盘组与所述第二电源地焊盘组之间，所述第二电源地焊盘组处于所述第一电源地焊盘组与所述第二信号焊盘组之间。
  5. 根据权利要求3所述集成电路，其特征在于，所述第一信号焊盘组处于所述第二电源地焊盘组与所述第二信号焊盘组之间，所述第二信号焊盘组处于所述第一信号焊盘组与所述第一电源地焊盘组之间；或者，
    所述第二电源地焊盘组处于所述第一信号焊盘组与所述第一电源地焊盘组之间，所述第一电源地焊盘组处于所述第二电源地焊盘组与所述第二信号焊盘组之间。
  6. 根据权利要求3所述集成电路，其特征在于，所述第一信号焊盘组 和所述第二信号焊盘组处在所述第一电源地焊盘组与所述第二电源地焊盘组之间，所述第一信号焊盘组中的至少一个焊盘与所述第二信号焊盘组中的至少一个焊盘为同一个位置上的焊盘；或者，
    所述第一电源地焊盘组和所述第二电源地焊盘组处在所述第一信号焊盘组与所述第二信号焊盘组之间，所述第一电源地焊盘组中的至少一个焊盘与所述第二电源地焊盘组中的至少一个焊盘为同一个位置上的焊盘。
  7. 根据权利要求2所述集成电路，其特征在于，在同一排中同时设有所述信号焊盘和所述电源地焊盘。
  8. 根据权利要求7所述集成电路，其特征在于，在一排中同时设有所述第一信号焊盘组中的焊盘和所述第一电源地焊盘组中的焊盘，所述第二电源地焊盘组与所述第一出线侧的距离大于所述第一电源地焊盘组与所述第一出线侧的距离；或者，
    在一排中同时设有所述第一信号焊盘组中的焊盘和所述第一电源地焊盘组中的焊盘，所述第一电源地焊盘组与所述第一出线侧的距离大于所述第二电源地焊盘组与所述第一出线侧的距离。
  9. 根据权利要求7所述集成电路，其特征在于，在至少一排中同时设有所述第一信号焊盘组中的焊盘与所述第二电源地焊盘组中的焊盘；或者，在至少一排中同时设有所述第二信号焊盘组中的焊盘与所述第一电源地焊盘组中的焊盘；或者，在至少一排中同时设有所述第一信号焊盘组中的焊盘与所述第二电源地焊盘组中的焊盘，且在至少一排中同时设有所述第二信号焊盘组中的焊盘与所述第一电源地焊盘组中的焊盘；
    所述第二电源地焊盘组与所述第一出线侧的距离大于所述第一电源地焊盘组与所述第一出线侧的距离。
  10. 根据权利要求7所述集成电路，其特征在于，在一排中同时设有所述第一电源地焊盘组中的焊盘和所述信号焊盘；或者在至少一排中同时设有所述第一信号焊盘组中的焊盘与所述第二电源地焊盘组中的焊盘；或者，在一排中同时设有所述第一电源地焊盘组中的焊盘和所述信号焊盘，且在至少一排中同时设有所述第一信号焊盘组中的焊盘与所述第二电源地焊盘组中的焊盘；
    所述第二电源地焊盘组与所述第一出线侧的距离大于所述第一电源地焊盘组与所述第一出线侧的距离，所述第一信号焊盘组中的至少一个焊盘与 所述第二信号焊盘组中的至少一个焊盘为同一个位置上的焊盘。
  11. 根据权利要求7所述集成电路，其特征在于，在一排中同时设有所述第一信号焊盘组中的焊盘和所述电源地焊盘；或者在至少一排中同时设有所述第二信号焊盘组中的焊盘与所述第一电源地焊盘组中的焊盘；或者，在一排中同时设有所述第一信号焊盘组中的焊盘和所述电源地焊盘，且在至少一排中同时设有所述第二信号焊盘组中的焊盘与所述第一电源地焊盘组中的焊盘；
    所述第一信号焊盘组与所述第一出线侧的距离大于所述第二信号焊盘组与所述第一出线侧的距离，所述第一电源地焊盘组中的至少一个焊盘与所述第二电源地焊盘组中的至少一个焊盘为同一个位置上的焊盘。
  12. 一种引线键合封装芯片，其特征在于，所述引线键合封装芯片包括：
    基板、中间层、如权利要求1-11任一项所述的集成电路、焊球和打线；
    所述裸芯片的有源面背向所述基板，所述中间层设于所述基板的一侧与所述集成电路之间，所述焊球设置在所述基板的另一侧，所述集成电路中的第一电源地焊盘组中的焊盘和第一信号焊盘组中的焊盘通过所述打线键合至所述基板中，并通过所述基板内的走线及金属平面与所述焊球连接。
  13. 一种倒装封装芯片，其特征在于，所述倒装封装芯片包括：
    基板、中间层、如权利要求1-11任一项所述的集成电路、焊球和金属凸块；
    所述裸芯片的有源面朝向所述基板，所述中间层设于所述基板的一侧与所述集成电路之间，所述焊球设置在所述基板的另一侧，所述中间层上设有通孔，所述金属凸块设于所述通孔内，所述集成电路中的第二电源地焊盘组中的焊盘和第二信号焊盘组中的焊盘通过所述金属凸块连接至所述基板，并通过所述基板内的走线及金属平面与所述焊球连接。
PCT/CN2016/079053 2015-04-17 2016-04-12 一种集成电路、引线键合封装芯片及倒装封装芯片 WO2016165607A1 (zh)

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CN109003949A (zh) * 2018-08-01 2018-12-14 灿芯半导体(上海)有限公司 一种键合线封装与倒装封装共用的接口
CN112736053A (zh) * 2019-10-14 2021-04-30 瑞昱半导体股份有限公司 芯片封装模块
WO2021147101A1 (zh) * 2020-01-23 2021-07-29 华为技术有限公司 一种芯片装置和无线通信装置
CN111739807B (zh) * 2020-08-06 2020-11-24 上海肇观电子科技有限公司 布线设计方法、布线结构以及倒装芯片
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