JP4951276B2 - Semiconductor chip and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the manufacturing cost of a semiconductor device, and to achieve an increase in pins. <P>SOLUTION: A plurality of pads 1c with first regions 1d and second regions 1e are formed in a rectangular shape, and the pads 1c have chamfering sections 1f at partial corners while being formed in zigzag arrays. The chamfering sections 1f are fitted while being opposed in the pads 1c on the internal rows and external rows of the zigzag arrays, and the first regions 1d are arranged on the core logic-region side of a semiconductor chip 1. Accordingly, a probe needle is brought into contact with the second regions 1e of the pads 1c, and a test can be conducted by a cantilever system in a wafer test. Package substrates can be shared even in flip-chip connections having different chip sizes, and the cantilever system at a low cost is adopted, thus reducing the manufacturing cost of the semiconductor device. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

The present invention relates to a technique effectively applied to a semiconductor device having a semiconductor chip and semi conductor chips.

  In a semiconductor device in which bonding pads for bonding external connection wires or bumps on a semiconductor chip are arranged in a staggered pattern, test pads for contacting a probe during a wafer test are connected to the bonding pads arranged in a staggered pattern. There is a technique provided in an extra space (see, for example, Patent Document 1).

The electrode rows of the IC chip pads are arranged in a staggered pattern. Each pad is provided with a wide bonding area for bonding and a narrow contact area for electrical test in plan view in different positions so as to form a substantially T-shape. There is a technique in which the contact areas are arranged in the same row and the bonding areas are arranged in a staggered manner with the pads facing each other (see, for example, Patent Document 2).
JP 2002-329742 A (FIG. 1) JP 2001-264391 A (FIG. 1)

  In a semiconductor device such as a BGA (Ball Grid Array), a technique for sharing a package substrate (wiring substrate) for a plurality of types of semiconductor chips such as sizes is known in order to reduce the manufacturing cost. ing. When a package substrate is to be shared, there is a certain degree of freedom in the chip size and bonding pad (surface electrode) coordinates if the semiconductor chip and the package substrate are connected by bonding wires. In other words, if the connection between the semiconductor chip and the package substrate is wire bonding, there is a degree of freedom to change the chip size, bonding pad shape, and bonding pad coordinates within a range that satisfies the bonding rules. Can be shared.

  However, when adopting flip connection in which a semiconductor chip and a package substrate are connected via bump electrodes in order to increase the response speed or to stack a plurality of chips into a single package, an attempt is made to share the package substrate. Then, since the bonding coordinates are fixed, there is no degree of freedom with respect to the chip size. That is, when the connection between the semiconductor chip and the package substrate is a flip connection, it is difficult to share the package substrate if the chip sizes are different.

  Further, as a technique for meeting the demand for increasing the number of pins of a semiconductor device, there is known a technique in which the bonding pads of a semiconductor chip are arranged in a staggered arrangement, as described in Japanese Patent Application Laid-Open No. 2002-329742 and Patent Document 1. 2 (Japanese Patent Laid-Open No. 2001-264391).

  In the assembly process of the semiconductor device, electrical inspection is performed by bringing a probe needle into contact with a bonding pad during a wafer test. The probe test mainly includes a cantilever method (see FIG. 10) in which the probe needle 13 contacts the bonding pad while moving horizontally (see FIG. 10), and a probe up-and-down movement method in which the probe needle 13 moves up and down (FIG. 11). See).

The cantilever method is indispensable for reducing the manufacturing cost because it has the advantages of lower cost and faster test throughput than the probe vertical movement method. However, in the cantilever method, since the probe needle 13 is brought into contact with the bonding pad while moving horizontally during the test, the probe mark 1s (see FIG. 8) is formed on the bonding pad larger than the probe vertical movement method. The As a result, when the bump electrode is to be connected to the probe mark 1s, the probe mark 1s occupies a relatively large area in the area where the bump electrode is in contact, so that a connection failure between the bump electrode and the package substrate occurs. easy. Therefore, it is necessary to connect the bump electrode to a region avoiding the probe mark 1s, and it is necessary to increase the area of the bonding pad.
On the other hand, if the probe vertical movement method is applied, as shown in FIG. 24, since the probe trace 16 formed is smaller than the cantilever method, even if a bump electrode is connected to the region where the probe trace 16 is formed. no problem. Accordingly, if the probe vertical movement method is applied, the bonding pad area can be formed smaller than that of the cantilever method (however, the position of the gold bump 3 is shifted by T). As a result, the size of the semiconductor chip to which the cantilever method is applied becomes larger than the size of the semiconductor chip to which the probe vertical movement method is applied, because the bonding pad area is increased in consideration of the probe trace 1s as described above. . However, even when the cantilever method is applied, if the core logic region of the semiconductor chip is relatively small, the bonding pad area can be absorbed, but if the core logic region is reduced, higher functionality is achieved. And it becomes difficult to cope with high integration.

  That is, if it is attempted to achieve both a reduction in manufacturing cost by using a common package substrate and a staggered arrangement of bonding pads for increasing the number of pins, there is a problem that pad layout in a semiconductor chip is difficult.

  If the core logic area 12b inside the IO cell area 12c is smaller than the chip size, pad layout is possible even when the chips are different as shown in the comparative example of FIG. 21, but with the miniaturization of the semiconductor device, Since the chip size is also small, it is difficult in terms of pad layout to arrange the bonding pads in a staggered manner while maintaining a pad size that allows the cantilever method to be used.

  In the techniques disclosed in Patent Documents 1 and 2, every other pad in the pad arrangement direction is arranged on the side far from the core logic area of the semiconductor chip (outside the staggered arrangement) in the pad arrangement direction. ing. If the bump region of the pad is arranged on the side far from the core logic region, there arises a problem that the lead wiring connected to the pad becomes long and the inductance becomes high. Furthermore, when a wafer test is performed on this pad using a cantilever method, the probe region is closer to the core logic region (front side) than the bump region on the pad. There is a problem that the resistance becomes high due to the deep damage of the marks, and further, the conduction with the bump region is cut off by cutting.

  An object of the present invention is to provide a technique capable of reducing the manufacturing cost of a semiconductor device.

  Another object of the present invention is to provide a technique capable of realizing a multi-pin semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

That is, the present invention includes a main surface, a plurality of pads formed on the main surface, so as to expose each of the plurality of pads, and a protective film formed on the main surface, in a plan view, the It includes a core logic area formed inside the main surface than the plurality of pads, and a plurality of wires which respectively are connected to the plurality of pads, and a back surface opposite to the main surface The peripheral portions of each of the plurality of pads are covered with the protective film, and the planar shape of each of the plurality of pads is a pair of first sides facing each other and a direction intersecting the first side. The exposed surfaces of the plurality of pads exposed from the protective film are first regions to which wires or bumps are connected. When, of the first region along the first side Located in, and a second region to which the probe needle is contacted, in a plan view, the between the first region and the second region, of the pair of the first side protruding portions of the protective film protrudes toward the one from the other are arranged, each of the plurality of wires, before Symbol rather than the second region, is connected to the first realm side It is what.
The present invention also provides a wiring board having an upper surface and a lower surface opposite to the upper surface, a main surface, a plurality of pads formed on the main surface, and the main pads so as to expose each of the plurality of pads. Protective film formed on the surface, core logic region formed on the inner side of the main surface with respect to the plurality of pads in plan view, a plurality of wirings connected to the plurality of pads, respectively, and opposite to the main surface A semiconductor chip mounted on the upper surface of the wiring board, and a resin that seals the semiconductor chip, and each peripheral portion of the plurality of pads is formed of the protective film. The planar shapes of the plurality of pads are a pair of first sides facing each other, and a pair of second sides extending in a direction intersecting the first side and facing each other. A shape having Each exposed surface of the plurality of pads exposed from the protective film is located next to the first region to which the wire or the bump is connected, the first region along the first side, and the probe A second region with which the needle contacts, and in plan view, between the first region and the second region, approaches from one of the pair of the first sides toward the other. The protruding portion of the protective film is arranged, and each of the plurality of wirings is connected not to the second region but to the first region .

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  A plurality of surface electrodes having a first region and a second region are formed in a rectangular shape, the surface electrodes have chamfered portions at some corners and are provided in a staggered arrangement, and the chamfered portions of the surface electrodes are further provided. A probe needle is provided in the second region of the surface electrode in the wafer test by providing the staggered inner row and the outer row opposite to each other and arranging the first region on the core logic region side of the semiconductor chip. The test can be performed in a cantilever system by contacting. As a result, since the surface electrode is formed in a rectangular shape, it is possible to share a package substrate even in flip connection with different chip sizes, and furthermore, a cantilever method that can be used at a low cost in a wafer test can be adopted. Thus, the manufacturing cost of the semiconductor device can be reduced. In addition, since the flip connection and the staggered arrangement of the surface electrodes can be realized, the increase in the number of pins accompanying the increase in the speed of the semiconductor device can be realized.

  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment 1)
1 is a cross-sectional view showing an example of the structure of the semiconductor device according to the first embodiment of the present invention, FIG. 2 is a plan view showing an example of the structure of the semiconductor device shown in FIG. 1, and FIG. 3 is a plan view of the semiconductor device shown in FIG. It is a top view which shows an example of the pad layout of the semiconductor chip used for an assembly. 4 is a plan view showing an example of a structure in which bump electrodes are connected to pads of the semiconductor chip shown in FIG. 3, FIG. 5 is an enlarged partial plan view showing the structure of part A shown in FIG. 4, and FIG. It is a partial expanded sectional view which shows an example of the structure of the cross section cut | disconnected along BB line shown in FIG. 7 is a plan view showing an example of a pad structure of the semiconductor chip shown in FIG. 4, FIG. 8 is a plan view showing an example of a staggered arrangement of pads of the semiconductor chip shown in FIG. 4, and FIG. 9 is shown in FIG. FIG. 10 is a plan view showing an example of a probe mark formed when a cantilever type test is performed on a semiconductor chip. FIG. 10 shows a test state using a cantilever type probe in the assembly of the semiconductor device according to the first embodiment of the present invention. It is a conceptual diagram which shows an example. 11 is a conceptual diagram showing a test state by the probe vertical movement method of the comparative example, and FIG. 23 is a plan view showing the position of the probe mark when the probe test is performed by the probe vertical movement method in the pad arrangement shown in FIG. It is.

  The semiconductor device of the first embodiment has a semiconductor chip 1 flip-connected on a wiring board. In the first embodiment, two semiconductor chips 1 and 2 are stacked as an example of the semiconductor device. A chip stacking type SIP (System In Package) 7 mounted in this manner will be described.

  As shown in FIGS. 1 and 2, the SIP 7 according to the first embodiment includes a first-stage semiconductor chip 1 and a second-stage semiconductor chip (second semiconductor chip) 2 stacked on the first-stage semiconductor chip 1. The first-stage semiconductor chip 1 is flip-connected via a gold bump (bump electrode) 3 on a main surface 5a of a package substrate 5 which is a wiring substrate. On the other hand, the second-stage semiconductor chip 2 is stacked and mounted on the back surface 1b of the first-stage semiconductor chip 1, and is electrically connected to the package substrate 5 by wire bonding.

  That is, in the SIP 7, the first-stage semiconductor chip 1 is mounted face-down on the package substrate 5, and the second-stage semiconductor chip 2 is mounted face-up on the first-stage semiconductor chip 1. . That is, the back surface 2b of the second-stage semiconductor chip 2 is joined to the back surface 1b of the first-stage semiconductor chip 1. Therefore, the main surface 2a of the semiconductor chip 2 faces upward, and a plurality of pads 2c, which are surface electrodes, are provided side by side at the end of a predetermined side of the main surface 2a. Furthermore, one end of a wire 6 is connected to these pads 2 c, and the other end of these wires 6 is electrically connected to an electrode 5 c of the package substrate 5.

  In SIP 7, the flip-connected first-stage semiconductor chip 1 is, for example, a microcomputer chip having a control circuit, while the second-stage semiconductor chip 1 is electrically connected to the package substrate 5 via wires 6. The semiconductor chip 2 is a memory chip having a memory circuit such as an SDRAM (Synchronous Dynamic Random Access Memory).

  Also, solder balls 4 as a plurality of external terminals are provided on the back surface 5b of the package substrate 5 in, for example, a grid pattern, and the semiconductor chips 1 and 2 are electrically connected to the corresponding solder balls 4 respectively. It is connected and transmits signals to the outside.

  The semiconductor chips 1 and 2 and the wire 6 are sealed with, for example, resin.

  The SIP 7 of the first embodiment is assembled by adopting the package substrate 5 that is shared with other chips. That is, in order to reduce the manufacturing cost of the semiconductor device, the package substrate 5 is used in common with other chips having different sizes, such as the core logic region 1g, and the semiconductor chip shown in FIG. It is characterized by the shape and arrangement of a plurality of pads (surface electrodes) 1c provided on one main surface 1a.

  As shown in FIG. 3, a plurality of pads 1c are provided on the peripheral portion of the main surface 1a of the semiconductor chip 1 for flip connection. A core logic region 1g is formed in a further inner region of the IO cell region 1i inside the pad 1c of the semiconductor chip 1, and includes a CPU (Central Processing Unit) 1j, a DSP (Digital Signal Processing) 1k, and a RAM. Circuits such as (Random Access Memory) 1m, PLL (Phase Locked Loop) 1n, and DLL (Delay Locked Loop) 1p are formed. Further, an IO cell region 1i is formed between the core logic region 1g and the pad row outside thereof.

  In the semiconductor chip 1 of the SIP 7 of the first embodiment, a plurality of pads 1c provided on the peripheral edge of the main surface 1a are provided in a staggered arrangement in order to realize a multi-pin configuration. As shown in FIG. 5, each pad 1c has a first region 1d and a second region 1e, and extends in a first direction 8 that intersects the arrangement direction 15 of the pads 1c. The first region 1 d and the second region 1 e are adjacent to each other in the direction along the first direction 8. Further, the first region 1d in each pad 1c is arranged on the core logic region 1g side of the semiconductor chip 1 as shown in FIG. Therefore, the second region 1e in each pad 1c is arranged on the side far from the core logic region 1g of the semiconductor chip 1.

  The first region 1d is a region for connecting the gold bumps 3 as bump electrodes, and the second region 1e is a region for contacting the probe needle 13 in the probe test as shown in FIG.

  Therefore, as shown in FIGS. 4 and 5, the gold bumps 3 are connected to the respective first regions 1d of the pads 1c. Each pad 1c has a peripheral edge covered with a protective film 1q as shown in FIG. 6, and a gold bump 3 is disposed in the opening of the protective film 1q.

  Each pad 1c has a chamfered portion 1f formed at a part of each corner. As shown in FIGS. 5 and 8, the chamfered portion 1 f includes two corner portions of the second region 1 e of the pad 1 c in the staggered array at the four corner portions of each rectangular pad 1 c and the outer row. The pad 1c is formed at two corners of the first region 1d. Accordingly, the chamfered portion 1f is formed so as to be opposed to the pad 1c in the inner row and the outer row in the staggered arrangement.

  In this way, the chamfered portion 1f is formed at a position facing the inner row and the outer row pad 1c of the staggered arrangement so that the pads in the staggered arrangement between the inner row and the outer row pads and the pads in the arrangement direction 15 of the pads 1c. It is possible to arrange them in close proximity, making it possible to realize a large number of pins, and to reduce the size of the semiconductor chip 1 when the number of pins is fixed.

  The chamfered portion 1f of each pad 1c is formed at an angle of θ = 45 ° with respect to the arrangement direction 15 of the pads 1c as shown in FIG. This angle (θ) is based on the inclination angle of the photomask used in the pattern formation process during pad formation.

  As described above, in the SIP 7 according to the first embodiment, it is possible to increase the number of pins by arranging the pads arranged in a staggered pattern in the semiconductor chip 1. For example, as shown in FIG. 8, the pads 1c can be arranged with a narrow pitch (pad pitch A) of 50 μm or less, preferably 40 to 50 μm with respect to the arrangement direction 15 of the pads 1c. At that time, as shown in FIGS. 5 and 9, the wiring 1 h that is electrically connected to the pad 1 c in the outer row is arranged beside the pad 1 c in the inner row in the staggered arrangement. That is, a lead wire 1h that is electrically connected to the pad 1c in the outer row is disposed between adjacent pads in the inner row in the staggered arrangement.

  Since the pad pitch is narrow, the gold bump 3 is preferably a stud bump formed using Au wire. That is, by forming the gold bumps 3 by stud bumps, the gold bumps 3 can be connected to the pads 1c even with respect to the pads 1c arranged at a narrow pitch.

  Next, a semiconductor wafer probe test performed in the assembly of the semiconductor device of the first embodiment shown in FIG. 10 will be described. As shown in FIG. 7, each pad 1c of the semiconductor chip 1 includes a first region 1d and a second region 1e and extends in a first direction 8 that intersects the arrangement direction 15 of the pads 1c. The first region 1d and the second region 1e are formed in a rectangular shape, and the second region 1e is a region located on the far side from the core logic region 1g (see FIG. 4) of the semiconductor chip 1. Therefore, the second region 1e is a region where the probe needle 13 is brought into contact in the probe test as shown in FIG.

  In the wafer test, the probe needle 13 is pressed against the pad 1c to perform the test. The probe test shown in FIG. 10 is a cantilever type in which the probe needle 13 contacts the pad 1c while moving horizontally during the test. It has the advantages of low cost and fast test throughput. Therefore, in the first embodiment, the cantilever method is adopted during the wafer test in order to reduce the manufacturing cost of the SIP 7. In the cantilever method, during the test, the stage 14 is raised to make contact between the semiconductor wafer 11 on the stage 14 and the probe needle 13 attached to the probe card substrate 9. At that time, since the probe needle 13 moves inward as the stage 14 moves up, an elongated probe mark 1s is formed in the second region 1e of the pad 1c as shown in FIGS. The probe mark 1 s is a recess that is cut by the probe needle 13. Therefore, in consideration of the positional deviation of the probe needle 13, it is preferable to form the pad 1c so that the longitudinal direction of the rectangle is as long as possible within the allowable range.

  The probe test of the comparative example shown in FIG. 11 is of the probe vertical movement method (thin film probe method, advanced probe card method) in which the probe needle 13 attached to the probe card substrate 10 moves up and down to contact the pad 1c. In the probe vertical movement method, the contact area of the probe needle 13 is very small, but the cost of the structure of the probe card substrate 10 is high, and the manufacturing cost of the SIP 7 cannot be reduced.

  Therefore, in the semiconductor device of the first embodiment, the pad 1c of the semiconductor chip 1 is divided into the first region 1d for gold bump connection and the second region 1e for contact with the probe needle, and is formed in a rectangular shape. Thus, the cantilever method can be adopted during the probe test in the assembly. As a result, by adopting the cantilever method, the manufacturing cost of the semiconductor device (SIP7) can be reduced, and the test throughput can be improved. Since the test throughput can be improved, the pad arrangement is suitable for mass production.

  Next, an example of detailed dimensions of the pad and the pad layout will be described with reference to FIGS.

  As shown in FIG. 7, the dimensions (M1, M2, M3, M4) of the pads 1c are M1 = 54 μm, M2 = 104.5 μm, M3 = 115 μm, and M4 = 33 μm, respectively. The dimensions of the pad openings (C1, C2, C3, C4) are C1 = 50 μm, C2 = 101.5 μm, C3 = 111 μm, and C4 = 31 μm, respectively. Therefore, since the length (C1) of the opening in the width direction (arrangement direction 15) is 50 μm, the diameter (L) of the gold bump 3 is also 50 μm.

  Also, as shown in FIG. 8, in the pad layout, the distance between each location (A, B, C, D) is A (pad pitch) = 40 μm and B (pitch between gold bumps in the first direction 8), respectively. = 112 μm, C (probe mark pitch in the first direction 8) = 112 μm, D (pitch between chamfered portions) = 2.83 μm.

  That is, the distance (B) between the inner and outer gold bumps of the staggered pad 1c is 112 μm, the diameter (L) of the gold bump 3 is 50 μm, and the longitudinal length (M3) of the pad 1c is second. In consideration of the region 1e, the thickness is 115 μm. Furthermore, by forming a chamfered portion 1f having an inclination angle of 45 ° at the opposite corners of the pads 1c in the inner row and the outer row, the first region 1d and the second region are kept at the same distance and coordinates between the gold bumps. Area 1e can be secured.

  Note that the second region 1e with which the probe needle 13 is brought into contact with the pad 1c is preferably formed as wide as possible in consideration of the positional deviation when the probe needle 13 is brought into contact. As described above, the two corners of the second region 1e of the pad 1c in the outer row of the staggered arrangement are not formed with the chamfered portions 1f.

  According to the semiconductor device (SIP7) of the first embodiment, the plurality of pads 1c having the first region 1d and the second region 1e are formed in a rectangular shape, and the pads 1c are chamfered at some corners. 1f and provided in a zigzag arrangement, and the chamfered portion 1f of the pad 1c is provided opposite to the inner and outer rows of the zigzag arrangement, and the first area 1d is on the core logic area 1g side of the semiconductor chip 1 Has been placed. As a result, in the probe test of the semiconductor wafer 11, the probe needle 13 can be brought into contact with the second region 1e of the pad 1c, and the wafer test can be performed by the cantilever method.

  As a result, the pad 1c having the first region 1d and the second region 1e is formed in a rectangular shape, so that the package substrate 5 can be shared even in flip connection with different chip sizes. By making the flip-connected package substrate 5 common, the development cost of the substrate can be reduced and the mass production cost of the substrate can be suppressed. Furthermore, since the cantilever method with low cost can be adopted in the wafer test, the manufacturing cost of the SIP (semiconductor device) 7 can be reduced.

  Further, if the pads 1c are arranged in a narrow pitch and in a staggered arrangement, it is difficult to simply increase the size of the pad 1c to a rectangle, but the chamfered portions 1f are arranged in the staggered inner row and outer row pads 1c. By forming them at positions facing each other, it is possible to close and arrange between the pads in the inner and outer rows in the staggered arrangement and between the pads in the arrangement direction 15 of the pads 1c.

  As described above, by adopting the pad shape of the first embodiment, it is possible to share the flip-connected package substrate 5 even when the pad size is increased, and realize a staggered arrangement of the pads 1c to achieve a multi-pin configuration. Can be achieved. Further, when the number of pins is fixed, the semiconductor chip 1 can be downsized.

  Further, it is possible to cope with the high speed of the SIP (semiconductor device) 7 by flip connection.

  Here, a description will be given of the results of the inventor's comparative study on each dimension of the pad layout described in the comparative example shown in FIG. 22 (similar to the pad layout of Japanese Patent Application Laid-Open No. 2002-329742).

  In the pad 12a of the comparative example shown in FIG. 22, the probe region 12e in which the probe mark 12g is formed is formed narrower than the bump region 12d to which the gold bump 12f is connected. Further, the bump region 12d and the probe region 12e are alternately arranged on the side farther from the core logic region 12b of the semiconductor chip 12 (outside the staggered arrangement) and the side closer to every other pad 12a with respect to the arrangement direction 15 of the pads 12a. Has been placed.

  The dimensions (M1, M2, M3, M4, M5) in the pad layout shown in the comparative example of FIG. 22 are M1 = 44 μm, M2 = 54 μm, M3 = 54 μm, M4 = 61 μm, and M5 = 115 μm, respectively. . The dimensions of the pad openings (C1, C2, C3, C4, C5) are C1 = 40 μm, C2 = 50 μm, C3 = 61 μm, C4 = 50 μm, and C5 = 111 μm, respectively. Therefore, the minimum dimension of the pad pitch (Q) is Q = 51 μm, and in the SIP 7 of the first embodiment, the pad pitch is a narrow pitch of 50 μm or less, preferably 40 to 50 μm. It turned out to be impossible with the pad layout.

  Further, as in the comparative example of FIG. 22, if there is a pad 12a in which the bump region 12d is arranged on the side far from the core logic region 12b, the lead wiring connected to the pad 12a becomes longer and the inductance becomes higher. The problem occurs.

  On the other hand, in the first embodiment, since the first region 1d (bump region) is arranged on the core logic region 1g side of the semiconductor chip 1 in all the pads 1c, it is connected to the pad 1c. It is possible to prevent the problem that the lead wiring becomes longer and the inductance becomes higher.

  Furthermore, when a wafer test is performed by the cantilever method in the pad layout of the comparative example of FIG. 22, there is a pad 12a formed in the probe area 12e closer to the core logic area 12b (in front) than the bump area 12d. The pad 12a also has a problem that the resistance is increased by the contact of the probe needle 13 by a cantilever method, or the pad 12a is cut and the conduction with the bump region 12d is cut off.

  On the other hand, in the first embodiment, since the first region 1d (bump region) is arranged on the core logic region 1g side of the semiconductor chip 1 in all the pads 1c, the probe needle by the cantilever method is used. Thus, it is possible to prevent a problem that the resistance is increased due to the contact 13 or the pad 1c is cut and the conduction with the first region 1d is cut off.

  Next, FIG. 23 shows a modification of the first embodiment, and shows a case where a probe test is performed by the probe vertical movement method shown in FIG. 11 in the pad arrangement shown in FIG.

  That is, in the pad shape / arrangement shown in FIG. 8, as shown in FIG. 23, it is possible to form a small probe mark 16 by the probe vertical movement method, and the probe test by the probe vertical movement method shown in FIG. Is possible.

(Embodiment 2)
FIG. 12 is a plan view showing an example of the structure of pads in the inner row of the staggered arrangement in the semiconductor chip of the second embodiment of the present invention, and FIG. 13 shows the outer row of the staggered arrangement in the semiconductor chip of the second embodiment of the present invention. FIG. 14 is a plan view showing an example of a staggered arrangement of pads of a semiconductor chip according to the second embodiment of the present invention.

  The second embodiment shows a modification of the pad 1c. 12 shows the shape of the pad 1c in the inner row of the staggered arrangement, FIG. 13 shows the shape of the pad 1c in the outer row, and FIG. 14 shows the pad layout. In each pad 1c, the first region 1d and the first region 1d are shown. A protruding portion 1r that divides the second region 1e is formed in the pad opening from the outer periphery of the pad 1c toward the inside.

  The dimensions of the respective portions (M1, M2, M3, M4) of the pad 1c are M1 = 54 μm, M2 = 104.5 μm, M3 = 115 μm, and M4 = 33 μm, respectively. The dimensions of the pad openings (C1, C2, C3, C4, C5, C6, C7) are C1 = 50 μm, C2 = 101.5 μm, C3 = 111 μm, C4 = 31 μm, C5 = 61 μm, C6 = 5 μm, respectively. , C7 = 5 μm. Therefore, since the length (C1) in the width direction of the opening is 50 μm, the diameter (L) of the gold bump 3 is also 50 μm.

  Further, in the pad layout shown in FIG. 14, the distances between the respective locations (A, B, C, D) are A (pad pitch) = 40 μm and B (pitch between gold bumps in the first direction 8) = 112 μm, respectively. , C (probe mark pitch in the first direction 8) = 112 μm, D (pitch between chamfered portions) = 2.83 μm.

  Since the protruding portion 1r is formed in the pad opening as in the second embodiment, the first region 1d and the second region 1e can be easily distinguished. As a result, when the second region 1e, which is the probe region, is designated to the prober during the wafer test, the protruding portion 1r becomes a mark, so that alignment becomes easy and occurrence of work errors can be suppressed.

(Embodiment 3)
FIG. 15 is a plan view showing an example of the structure of pads in the inner row of the staggered arrangement in the semiconductor chip of the third embodiment of the present invention, and FIG. 16 shows the outer row of the staggered arrangement in the semiconductor chip of the third embodiment of the present invention. FIG. 17 is a plan view showing an example of the pad structure, and FIG. 17 is a plan view showing an example of a staggered arrangement of pads of the semiconductor chip according to the third embodiment of the present invention.

  The third embodiment shows a modification of the pad 1c. 15 shows the shape of the pad 1c in the inner row in the staggered arrangement, FIG. 16 shows the shape of the pad 1c in the outer row, and FIG. 17 shows the pad layout. Among them, in the pad 1c in the inner row, the width (C7) in the width direction (arrangement direction 15) perpendicular to the longitudinal direction (first direction 8) of the second region 1e is equal to the width of the first region 1d ( C1) is formed narrower. Specifically, the width of the first region 1d in the arrangement direction 15 is wider than the width of the pad 1c of the first embodiment in consideration of the positional deviation of the gold bump 3. However, for the second region 1e, the inclination angle of the chamfered portion 1f of the corner portion is determined to be 45 °, and when the positional deviation from the probe needle 13 in the second region 1e is considered, the chamfered portion 1f of the chamfered portion 1f is considered. Since the length in the first direction 8 cannot be increased, the width (C7) of the second region 1e is set to 50 μm, which is the same as the pad 1c of the first embodiment, and is narrower than the width (C1) 55 μm of the first region 1d. Yes.

  The dimensions of the pads 1c (M1, M2, M3, M4, M5, M6) are M1 = 59 μm, M2 = 110.5 μm, M3 = 120 μm, M4 = 29 μm, M5 = 59 μm, and M6 = 25 μm, respectively. is there. The dimensions of the pad openings (C1, C2, C3, C4, C5, C6, C7, C8) are C1 = 55 μm, C2 = 101.5 μm, C3 = 111 μm, C4 = 31 μm, C5 = 61 μm, C6, respectively. = 55 μm, C7 = 50 μm, C8 = 23 μm.

  In the pad layout shown in FIG. 17, the distances between the respective locations (A, B, C, D) are A (pad pitch) = 40 μm and B (pitch between gold bumps in the first direction 8) = 112 μm, respectively. , C (probe mark pitch in the first direction 8) = 112 μm, D (pitch between chamfered portions) = 2.83 μm.

  The bonding area is expanded by setting the length (C1) in the width direction of the pad opening in the first region 1d to 55 μm with respect to the diameter L = 50 μm of the gold bump 3 as in the third embodiment. Therefore, the mass production yield can be improved, and the assembly margin can be secured to improve the ease of assembly.

(Embodiment 4)
18 is a plan view showing an example of the structure of pads in the inner row of the staggered arrangement in the semiconductor chip of the fourth embodiment of the present invention, and FIG. 19 is the outer row of the staggered arrangement in the semiconductor chip of the fourth embodiment of the present invention. FIG. 20 is a plan view showing an example of a staggered arrangement of pads of a semiconductor chip according to the fourth embodiment of the present invention.

  The fourth embodiment shows a modification of the pad 1c. 18 shows the shape of the pad 1c in the inner row of the staggered array, FIG. 19 shows the shape of the pad 1c in the outer row, and FIG. 20 shows the pad layout. Among them, the inner row pad 1c has the same shape as the pad 1c of the third embodiment, but the outer row pad 1c is also wide in the arrangement direction 15 thereof.

  In other words, in the pad 1c in the outer row of the staggered arrangement, the extended portion 1t that increases the area in the width direction (arrangement direction 15) is formed. Since the lead-out wiring is not formed on the side of the pad 1c in the outer row, both the bonding area and the probe area can be widened.

  In the pad 1c in the outer row, the chamfered portions 1f are required at the two corners of the first region 1d so as to face the chamfered portion 1f of the pad 1c in the inner row. The chamfered portion 1f of the first region 1d is formed at a position further from the center from the two corners. Thereby, the extension part 1t can be formed in the pad 1c without changing the pad layout of the inner and outer rows.

  The dimensions of the respective locations (M1, M2, M3, M4, M5, M6, M7) of the pad 1c are M1 = 59 μm, M2 = 110.5 μm, M3 = 120 μm, M4 = 29 μm, M5 = 59 μm, M6 = 25 μm, M7 = 69 μm. The dimensions of the pad openings (C1, C2, C3, C4, C5, C6, C7, C8, C9) are C1 = 55 μm, C2 = 101.5 μm, C3 = 111 μm, C4 = 31 μm, C5 = 61 μm, respectively. C6 = 55 μm, C7 = 50 μm, C8 = 23 μm, and C9 = 65 μm.

  Further, in the pad layout shown in FIG. 20, the distances between the respective locations (A, B, C, D) are A (pad pitch) = 40 μm and B (pitch between the gold bumps in the first direction 8) = 112 μm, respectively. , C (probe mark pitch in the first direction 8) = 112 μm, D (pitch between chamfered portions) = 2.83 μm.

  For the diameter L = 50 μm of the gold bump 3 as in the fourth embodiment, the length (C1) in the width direction (arrangement direction 15) of the pad opening of the first region 1d of the pad 1c in the inner row is set. Further, the extension portion 1t is formed on the pad 1c in the outer row and the length (C9) of the pad opening in the width direction is set to 65 μm, so that both the bonding area and the probe area are provided in the pad 1c in the outer row. Can be widened.

  As a result, the mass production yield can be further improved as compared with the pad layout of the third embodiment, and the assembly margin can be secured and the ease of assembly can be further improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, in the first embodiment, the case where semiconductor chips are stacked in two stages as a SIP (semiconductor device) has been described, but the number of stacked chips in the SIP may be any number. Further, it is not always necessary to stack chips, and any semiconductor device may be used as long as it uses a wiring board that is shared with other chips, and at least one chip is flip-connected on the wiring board.

  The present invention is suitable for an electronic device having a flip chip.

It is sectional drawing which shows an example of the structure of the semiconductor device of Embodiment 1 of this invention. FIG. 2 is a plan view illustrating an example of a structure of the semiconductor device illustrated in FIG. 1. FIG. 2 is a plan view showing an example of a pad layout of a semiconductor chip used for assembling the semiconductor device shown in FIG. 1. FIG. 4 is a plan view showing an example of a structure in which bump electrodes are connected to pads of the semiconductor chip shown in FIG. 3. FIG. 5 is an enlarged partial plan view showing a structure of a portion A shown in FIG. 4. It is a partial expanded sectional view which shows an example of the structure of the cross section cut | disconnected along the BB line shown in FIG. FIG. 5 is a plan view showing an example of a pad structure of the semiconductor chip shown in FIG. 4. FIG. 5 is a plan view showing an example of a staggered arrangement of pads of the semiconductor chip shown in FIG. 4. FIG. 5 is a plan view showing an example of probe marks formed when a cantilever type test is performed on the semiconductor chip shown in FIG. 4. It is a conceptual diagram which shows an example of the test state using the cantilever type probe in the assembly of the semiconductor device of Embodiment 1 of this invention. It is a conceptual diagram which shows the test state by the probe vertical movement system of a comparative example. It is a top view which shows an example of the structure of the pad of the inner side row | line | column of a staggered arrangement in the semiconductor chip of Embodiment 2 of this invention. It is a top view which shows an example of the structure of the pad of the outer side row | line | column of a staggered arrangement in the semiconductor chip of Embodiment 2 of this invention. It is a top view which shows an example of the staggered arrangement of the pad of the semiconductor chip of Embodiment 2 of this invention. It is a top view which shows an example of the structure of the pad of the inner side row | line | column of a staggered arrangement in the semiconductor chip of Embodiment 3 of this invention. It is a top view which shows an example of the structure of the pad of the outer side row | line | column of a staggered arrangement in the semiconductor chip of Embodiment 3 of this invention. It is a top view which shows an example of the staggered arrangement of the pad of the semiconductor chip of Embodiment 3 of this invention. It is a top view which shows an example of the structure of the pad of the inner row | line | column of a staggered arrangement in the semiconductor chip of Embodiment 4 of this invention. It is a top view which shows an example of the structure of the pad of the outer side row | line | column of a staggered arrangement in the semiconductor chip of Embodiment 4 of this invention. It is a top view which shows an example of the staggered arrangement of the pad of the semiconductor chip of Embodiment 4 of this invention. It is a top view which shows the pad layout of the semiconductor chip of two different sizes for aiming at the sharing of the package substrate of a comparative example. It is a top view which shows the pad layout of the semiconductor chip of a comparative example. It is a top view which shows the position of the probe trace at the time of performing a probe test by the probe vertical movement system in the pad arrangement | sequence shown in FIG. It is a comparison figure of the bonding pad at the time of applying the case where a cantilever system is applied, and a probe vertical movement system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor chip 1a Main surface 1b Back surface 1c Pad (surface electrode)
1d 1st area 1e 2nd area 1f Chamfer 1g Core logic area 1h Wiring 1i IO cell area 1j CPU
1k DSP
1m RAM
1n PLL
1p DLL
1q Protective film 1r Protruding part 1s Probe trace 1t Expanding part 2 Semiconductor chip (second semiconductor chip)
2a main surface 2b back surface 2c pad 3 gold bump (bump electrode)
4 Solder balls (external terminals)
5 Package board (wiring board)
5a Main surface 5b Back surface 5c Electrode 6 Wire 7 SIP (Semiconductor device)
8 First direction 9,10 Probe card substrate 11 Semiconductor wafer 12 Semiconductor chip 12a Pad 12b Core logic area 12c IO cell area 12d Bump area 12e Probe area 12f Gold bump 12g Probe trace 13 Probe needle 14 Stage 15 Array direction 16 Probe trace

Claims (4)

And the main surface,
A plurality of pads formed on the main surface;
A protective film formed on the main surface so as to expose each of the plurality of pads;
In plan view, the core logic area formed inside the main surface than the plurality of pads,
A plurality of wires which respectively are connected to the plurality of pads,
A back surface opposite to the main surface;
Including
Each peripheral portion of the plurality of pads is covered with the protective film,
Each of the plurality of pads has a planar shape having a pair of first sides facing each other and a pair of second sides extending in a direction intersecting the first sides and facing each other. ,
Each exposed surface of the plurality of pads exposed from the protective film is positioned next to the first region along the first side to which a wire or bump is connected, and the first region , and A second region with which the probe needle is contacted ,
In the plan view, a protruding portion of the protective film that protrudes from one of the pair of the first sides toward the other is disposed between the first region and the second region. ,
The plurality of respective lines, before Symbol rather than the second region, the semiconductor chip, characterized in that connected to the first realm side. The semiconductor chip according to claim 1 ,
The plurality of pads are formed in a staggered pattern along the side of the main surface. A wiring board having an upper surface and a lower surface opposite to the upper surface;
A main surface, a plurality of pads formed on the main surface, a protective film formed on the main surface so as to expose each of the plurality of pads, and on a more inner side of the main surface than the plurality of pads in plan view A semiconductor chip mounted on the top surface of the wiring board, having a core logic region formed, a plurality of wirings connected to the plurality of pads, and a back surface opposite to the main surface;
A resin for sealing the semiconductor chip;
Including
Each peripheral portion of the plurality of pads is covered with the protective film,
Each of the plurality of pads has a planar shape having a pair of first sides facing each other and a pair of second sides extending in a direction intersecting the first sides and facing each other. ,
Each exposed surface of the plurality of pads exposed from the protective film is positioned next to the first region along the first side to which a wire or bump is connected, and the first region, and A second region with which the probe needle is contacted,
In the plan view, a protruding portion of the protective film that protrudes from one of the pair of the first sides toward the other is disposed between the first region and the second region. ,
Each of the plurality of wirings is connected not to the second region but to the first region. The semiconductor device according to claim 3.
The plurality of pads are formed in a staggered pattern along the side of the main surface.

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