JPWO2006134643A1 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

In the pre-process (wafer process), the first metal film is provided on the interlayer insulating film including the insulating film made of the low-k material, and the first metal film is used. An electrode pad including a hard second metal film is formed, and then, in a wafer inspection process, a probe needle is pressed against the second electrode film of the electrode pad to inspect electric characteristics. Thereby, the reliability of the semiconductor device can be improved.

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a semiconductor device using an insulating film made of a material having a low relative dielectric constant (Low-k material) as an interlayer insulating film in order to reduce inter-wiring capacitance. It is related to effective technology when applied.

  In the manufacture of a semiconductor device, a plurality of chip formation regions each having a plurality of integrated circuits and a plurality of electrode pads are formed on a semiconductor wafer, and then integrated in each chip formation region in a wafer state. A wafer inspection process (probe inspection process) for inspecting the electrical characteristics of the circuit is performed. The wafer inspection process is performed by pressing the tip of the probe needle against an electrode pad electrically connected to the integrated circuit.

  Japanese Patent Laid-Open No. 10-270512 discloses that “measurement caused by an oxide film is performed by applying a probe with the antireflection film (titanium lightride film) formed on the uppermost layer film of the bonding pad. "Technology that prevents an increase in contact resistance between a pad and a probe to be performed and enables accurate measurement".

Further, Japanese Patent Laid-Open No. 2003-86624 discloses that “the electrode on the surface of the semiconductor chip has a layer structure of the die sort electrode pad to which the die sort probe contacts and the wire bond electrode pad to which the bonding wire is connected. A technique that improves the electrical characteristics of the bonding wire and the electrode pad for wire bonding without increasing the area of the pad region is disclosed.
JP-A-10-270512 JP 2003-86624 A

  In manufacturing a semiconductor device, it is mainly classified into a preprocess and a postprocess. The pre-process is also referred to as a wafer process, and is a process of forming a plurality of chip formation regions, each of which is defined by a scribe line, each having an integrated circuit and a plurality of electrode pads on a semiconductor wafer. The post-process is also called an assembly process, and is a process of dividing a semiconductor wafer along a scribe line to form a plurality of semiconductor chips and packaging the semiconductor chips into various forms of packages.

  In the previous process, after forming a plurality of chip formation areas on a semiconductor wafer, the wafer inspection that inspects the electrical characteristics of the integrated circuit formed in each chip formation area and discriminates the quality grade such as non-defective product, defective product, operating frequency, etc. A process (probe inspection process) is performed. In this wafer inspection process, since the tip of the probe needle is pressed against an electrode pad electrically connected to the integrated circuit, an impact at the time of the pressure contact is transmitted to an interlayer insulating film below the electrode pad.

  On the other hand, in an integrated circuit, high integration, multiple functions, and higher speed are being pursued, and in order to achieve miniaturization and higher speed, the inter-wiring capacitance must be reduced.

  Therefore, in order to reduce the inter-wiring capacitance, an insulating film made of a material having a low relative dielectric constant (Low-k material) is being applied to the interlayer insulating film.

  However, since the low-k material has a lower elastic modulus than the conventional insulating material and is weak in impact resistance, when an insulating film made of the low-k material is applied to the interlayer insulating film under the electrode pad, wafer inspection is performed. In the process, a defect such as a crack is likely to occur in the interlayer insulating film due to an impact when the probe needle is pressed against the electrode pad. Such a defect causes a decrease in the reliability of the semiconductor device.

  An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.

  The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  The object is to provide the first conductive film and the first conductive film on the interlayer insulating film including the insulating film made of a low-k material in the previous process (wafer process), and the first conductive film. An electrode pad including a second conductive film harder than the conductive film is formed, and then in a wafer inspection process, a probe needle is pressed against the second electrode film of the electrode pad to inspect the electrical characteristics. Is achieved.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  According to the present invention, the reliability of a semiconductor device can be improved.

1A and 1B are diagrams showing an internal structure of a semiconductor device according to a first embodiment of the present invention (FIG. 1A is a schematic plan view, and FIG. 1B is a schematic cross-sectional view taken along line aa in FIG. 1A). . FIG. 2 is a schematic plan view showing a planar layout of the semiconductor chip of FIG. FIG. 3 is a schematic cross-sectional view showing the internal structure of the semiconductor chip of FIG. FIG. 4 is an enlarged schematic cross-sectional view of a part of FIG. FIG. 5 is a schematic plan view showing a part of a multi-wiring substrate used for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a flowchart showing manufacturing steps of the semiconductor device of the first embodiment. 7 is a schematic plan view showing a state in which a plurality of chip formation regions are formed on a semiconductor wafer in the manufacture of the semiconductor device of Example 1. FIG. FIG. 8 is a schematic plan view of a semiconductor wafer used for manufacturing the semiconductor device of the first embodiment. FIG. 9 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device of Example 1. FIG. 10 is a schematic cross-sectional view showing the manufacturing process (conductive film forming process) of the semiconductor device of Example 1. FIG. 11 is a schematic cross-sectional view showing the manufacturing process (electrode pad forming process) of the semiconductor device of Example 1. FIG. 12 is a schematic cross-sectional view illustrating the manufacturing process (probe inspection process) of the semiconductor device of Example 1. FIG. 13 is a schematic cross-sectional view showing the manufacturing process (protective film forming process) of the semiconductor device of Example 1. FIG. 14 is a schematic cross-sectional view showing the manufacturing process (opening forming process) of the semiconductor device of Example 1. FIG. 15 is a schematic cross-sectional view showing the manufacturing process (protective film forming process) of the semiconductor device of Example 1. FIG. 16 is a schematic cross-sectional view showing the manufacturing process (opening forming process) of the semiconductor device of Example 1. FIG. 17 is a schematic plan view showing the manufacturing process (dicing process) of the semiconductor device of Example 1. FIG. FIG. 18 is a schematic cross-sectional view ((a) is a chip mounting process, and (b) is a wire bonding process) showing the manufacturing process of the semiconductor device of Example 1. FIG. 19 is an enlarged schematic cross-sectional view of a part of FIG. FIG. 20 is a schematic cross-sectional view ((a) is a sealing process, and (b) is a bump forming process) showing the manufacturing process of the semiconductor device of Example 1. FIG. 21 is a schematic cross-sectional view showing the manufacturing process (dicing process) of the semiconductor device of Example 1. FIG. 22 is a flowchart showing manufacturing steps of a semiconductor device that is Embodiment 2 of the present invention. FIG. 23 is a schematic cross-sectional view showing the manufacturing process (opening forming process) of the semiconductor device of Example 2. FIG. 24 is a schematic cross-sectional view showing the manufacturing process (probe inspection process) of the semiconductor device of Example 2. FIG. 25 is a schematic cross-sectional view showing the manufacturing process (conductive film patterning process) of the semiconductor device of Example 2. FIG. 26 is a schematic cross-sectional view showing the internal structure of a semiconductor chip incorporated in a semiconductor device that is Embodiment 3 of the present invention. FIG. 27 is a schematic plan view showing the wiring pattern of FIG. FIG. 28 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device of Example 3. FIG. 29 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device of Example 3. 30 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device of Example 3. FIG. FIG. 31 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device of Example 3. FIG. 32 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device of Example 3. FIG. 33 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device which is a modification of the third embodiment. FIG. 34 is a schematic cross-sectional view showing the internal structure of a semiconductor device that is Embodiment 4 of the present invention. FIG. 35 is a schematic cross-sectional view showing the internal structure of a semiconductor chip incorporated in a semiconductor device that is Embodiment 5 of the present invention. FIG. 36 is a diagram for explaining the effect of the present invention ((a) is a schematic plan view showing a pad arrangement of a conventional semiconductor chip, and (b) is a schematic diagram showing a pad arrangement of a semiconductor chip to which the present invention is applied. Is a plan view). FIG. 37 is a diagram for explaining the effect of the present invention ((a) is a schematic plan view showing a pad arrangement of a conventional semiconductor chip, and (b) is a schematic diagram showing a pad arrangement of a semiconductor chip to which the present invention is applied. Is a plan view). FIG. 38 is a diagram for explaining the effect of the present invention ((a) is a schematic plan view showing a pad layout of a conventional semiconductor chip, and (b) is a schematic diagram showing a pad layout of a semiconductor chip to which the present invention is applied. Is a plan view).

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2a ... Internal circuit formation part, 2b ... Peripheral part, 3 ... Element isolation region, 5 ... Wiring, 6 ... Conductive film, 7 ... Conductive film, 8 ... Conductive film, 9 ... Interlayer insulation film, 10 ... Insulating film (Low-k material film), 11 ... insulating film, 12 ... wiring, 13 ... interlayer insulating film, 14 ... electrode pad, 15 ... wiring, 16 ... protective film, 17 ... opening, 18 ... protective film, 19 ... Opening, 20 ... Semiconductor chip, 21 ... I / O cell, 25 ... Semiconductor wafer, 26 ... Chip formation area, 27 ... Scribe line, 28 ... Probe needle, 30 ... Wiring substrate, 31 ... Electrode pad, 32 ... Electrode pad, 35 ... multi-wiring board (multiple wiring board), 36 ... mold area (sealing area), 37 ... device forming area (product forming area), 41 ... bonding wire, 42, 42a ... resin sealing body, 43 ... solder Bump, 45 ... Semiconductor device 46 ... wiring, 47 ... inspection electrode pads, 51 ... wire, 52 ... inspection electrode pad, 53 ... protective film, 54 ... opening.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments of the invention, those having the same function are given the same reference numerals, and their repeated explanation is omitted.

  In the first embodiment, the present invention is applied to an electrode BGA (Ball Grid Array) type semiconductor device having an electrode pad that serves both as an inspection electrode pad to which a probe needle is pressed and a wire connection electrode pad to which a bonding wire is connected. An applied example will be described.

1 to 21 are diagrams related to a semiconductor device which is Embodiment 1 of the present invention.
1A and 1B are diagrams showing an internal structure of a semiconductor device (FIG. 1A is a schematic plan view, and FIG. 1B is a schematic sectional view taken along line aa in FIG. 1A).
FIG. 2 is a schematic plan view showing a planar layout of the semiconductor chip of FIG.
FIG. 3 is a schematic cross-sectional view showing the internal structure of the semiconductor chip of FIG.
FIG. 4 is a schematic cross-sectional view in which a part of FIG. 3 is enlarged.
FIG. 5 is a schematic plan view showing a part of a multi-wiring substrate used for manufacturing a semiconductor device.
FIG. 6 is a flowchart showing the manufacturing process of the semiconductor device.
FIG. 7 is a schematic plan view showing a state in which a plurality of chip formation regions are formed on a semiconductor wafer.
FIG. 8 is a schematic plan view of a semiconductor wafer used for manufacturing a semiconductor device.
9 to 16 are schematic cross-sectional views showing a wafer process (pre-process) in manufacturing a semiconductor device.
17 to 21 are diagrams showing an assembly process (post-process) in manufacturing a semiconductor device. FIG. 17 is a schematic plan view, and FIGS. 18 to 21 are schematic cross-sectional views.

  As shown in FIGS. 1A and 1B, in the semiconductor device 45 of the first embodiment, the semiconductor chip 20 is mounted on the main surface of the wiring board 30 called an interposer, A BGA type package structure in which a plurality of, for example, ball-shaped solder bumps 43 are arranged as protruding electrodes on the back surface on the opposite side.

  The semiconductor chip 20 has a square shape that intersects the thickness direction, and in the first embodiment, for example, the semiconductor chip 20 has a square shape of 10 mm × 10 mm. The semiconductor chip 20 has a main surface (element forming surface, circuit forming surface) and a back surface located on opposite sides, and the back surface is bonded to the main surface of the wiring board 30 with an adhesive interposed.

  A plurality of electrode pads 14 are arranged on the main surface of the semiconductor chip 20. The plurality of electrode pads 14 are arranged, for example, along each side of the semiconductor chip 20.

  The wiring substrate 30 has a square shape that intersects the thickness direction thereof, and is a square of, for example, 13 mm × 13 mm in the first embodiment. Although not limited to this, the wiring board 30 is formed, for example, so as to cover the core material, the first protective film formed so as to cover the main surface of the core material, and the main surface of the core material. The second protective film is provided. The core material has a configuration in which, for example, a wiring layer (conductive layer) is provided on the main surface and the back surface of a highly elastic resin substrate in which glass fiber is impregnated with epoxy or polyimide resin. The first and second protective films are formed mainly for the purpose of protecting the wiring formed on the wiring layers on the front and back surfaces of the core material. For example, an insulating resin film (solder resist film) is used as the first and second protective films.

  A plurality of electrode pads 31 are arranged on the main surface of the wiring board 30. The plurality of electrode pads 31 are arranged around the semiconductor chip 20 corresponding to the plurality of electrode pads of the semiconductor chip 20.

  A plurality of electrode pads 32 are arranged on the back surface of the wiring board 30. Solder bumps 43 are respectively fixed (electrically and mechanically connected) to the plurality of electrode pads 32.

  The plurality of electrode pads 14 of the semiconductor chip 20 are electrically connected to the plurality of electrode pads 31 of the wiring board 30 through the plurality of bonding wires 41. As the bonding wire 41, for example, an Au wire mainly composed of gold (Au) is used. As a method for connecting the bonding wires 41, for example, a nail head bonding (ball bonding) method using ultrasonic vibration in combination with thermocompression bonding is used.

  The semiconductor chip 20 and the plurality of bonding wires 41 are sealed with a resin sealing body 42 formed on the main surface of the wiring substrate 30. For the purpose of reducing the stress, the resin sealing body 42 is formed of, for example, a biphenyl-based thermosetting resin to which a phenol-based curing agent, silicone rubber, filler (for example, silica) and the like are added.

  The resin sealing body 42 has a rectangular planar shape that intersects the thickness direction, and has the same planar size as the wiring substrate 30 in the first embodiment, for example. As a method for forming the resin sealing body 42, a transfer molding method suitable for mass production is used.

  Here, in the manufacture of the BGA type semiconductor device, a multi-wiring board (multiple-wiring wiring board) having a plurality of product forming areas (device forming areas, product acquiring areas) partitioned by scribe lines is used for each product. The semiconductor chip mounted in the formation area is mounted in each product formation area using an individual transfer molding method that encapsulates the resin in each product formation area or a multi-wiring board that has multiple product formation areas. A batch type transfer molding method in which semiconductor chips are collectively sealed with a single resin sealing body is employed. In the first embodiment, for example, a batch type transfer molding method is employed.

  In the case of the collective transfer molding method, after forming the resin sealing body, the multi-wiring substrate and the resin sealing body are divided into a plurality of small pieces by, for example, dicing. Therefore, the resin sealing body 42 and the wiring board 30 of Example 1 have substantially the same outer size.

  Next, a specific structure of the semiconductor chip 20 will be described with reference to FIGS.

  As shown in FIG. 2, the main surface of the semiconductor chip 20 is provided with an internal circuit forming portion 2a and a peripheral portion 2b surrounding the internal circuit forming portion 2a in a plan view. In the internal circuit forming unit 2a, for example, a microcomputer is mounted as an integrated circuit. Although not shown, the microcomputer is constituted by a plurality of circuit blocks partitioned by the wiring channel region in the internal circuit forming unit 2a, and each circuit block is constituted by, for example, a plurality of MISFETs as transistor elements. In the peripheral portion 2 b, a plurality of electrode pads 14 are arranged along each side of the semiconductor chip 20, and a plurality of input / output cells (I / O cells) 21 are arranged corresponding to the plurality of electrode pads 14. Has been. The plurality of input / output cells 21 are arranged between the plurality of electrode pads 14 and the internal circuit formation portion 2a.

  As shown in FIG. 3, the semiconductor chip 20 mainly includes a semiconductor substrate 1 and a thin film stack 1 a in which a plurality of insulating layers and wiring layers are stacked on the main surface of the semiconductor substrate 1. It has become. In the first embodiment, the thin film stack 1a is not limited to this, but has, for example, a three-layer metal wiring structure.

  An element isolation region 3 for partitioning an active region (active region) in which a transistor element is formed is formed on the main surface of the semiconductor substrate 1, and a plurality of element formation regions partitioned by the element isolation region 3 are formed. For example, a MISFET-Q is formed as a transistor element.

  An interlayer insulating film 4 is provided on the main surface of the semiconductor substrate 1. This interlayer insulating film 4 is mainly for electrically separating the transistor element formed on the semiconductor substrate 1 from the first metal wiring layer.

  A first-layer metal wiring 5 is provided on the interlayer insulating film 4, and an interlayer insulating film 9 is further provided so as to cover the metal wiring 5. The interlayer insulating film 9 is mainly for electrically separating the first layer metal wiring and the second layer metal wiring.

  A second-layer metal wiring 12 is provided on the interlayer insulating film 9, and an interlayer insulating film 13 is further provided so as to cover the metal wiring 12. The interlayer insulating film 13 is for electrically separating the second-layer metal wiring from the third-layer metal wiring.

  An electrode pad 14 formed on the third metal wiring layer is provided on the interlayer insulating film 13, and protective films 16 and 18 are provided so as to cover the third metal wiring layer. It has been.

As shown in FIG. 4, the interlayer insulating film 13 has a multilayer structure (laminated structure) including the insulating film 10 and the insulating film 11 formed on the insulating film 10. The upper insulating film 11 is made of, for example, a P-TEOS silicon oxide film formed by a plasma CVD method using tetraethoxysilane (TEOS: Si (OC ₂ H ₅ ) ₄ ) as a reaction gas. The lower insulating film 10 is a film (for example, SiOF, SiOC) made of a material (Low-k) having a lower dielectric constant than that of the insulating film 11 (for example, P-TEOS silicon oxide film) in order to reduce the capacitance between wirings. ). This Low-k material film has a lower relative dielectric constant than the P-TEOS silicon oxide film, has a low Young's modulus, and is hard and brittle, so it is extremely vulnerable to impact.

  Here, the Young's modulus of the P-TEOS silicon oxide film is about 50 GPa, and the Young's modulus of an insulating film generally called a low-k material is about 10 to 20 GPa.

  Note that the interlayer insulating film 9 also has a multilayer structure including a low-k material film, like the interlayer insulating film 13, in order to reduce the capacitance between wirings.

  The protective film 16 is formed of, for example, a silicon oxide film or a silicon nitride film, or an inorganic insulating film made of a silicon oxide film and a silicon nitride film. The protective film 18 is formed of an organic insulating film such as a polyimide film. The protective film 16 is provided mainly for the purpose of protecting the uppermost wiring layer of the thin film laminate 1a. The protective film 18 is mainly used for the purpose of suppressing damage to the protective film 10 caused by fillers contained in the resin sealing body 42, and improving the adhesion between the semiconductor chip 20 and the resin of the resin sealing body 42. It is provided for the purpose of

  An opening 17 formed by etching the protective film 16 is provided on the electrode pad 14, and an opening 19 formed by etching the protective film 18 is further provided.

  The electrode pad 14 is not limited to this, but includes, for example, a conductive film 7 that is a main conductive material, a conductive film 6 that is provided below the conductive film 7, and a conductive film 8 that is provided above the conductive film 7. It has a multi-layer structure. The conductive films 6 and 8 are formed with a film thickness relatively smaller than that of the conductive film 7. In the first embodiment, the conductive film 7 as the main conductive material is formed with a film thickness of about 600 to 2000 [nm], for example. The lower conductive film 6 is formed with a film thickness of about 30 [nm], for example. The upper conductive film 8 is formed with a film thickness of, for example, about 50 to 100 [nm].

  The conductive film 7 is made of a material that has higher bondability (adhesiveness) with the bonding wire 41 mainly composed of Au than the conductive film 8, and is formed of a conductive film mainly composed of aluminum (Al), for example. The conductive films 6 and 8 are made of a material harder than the conductive film 7, and are formed of, for example, a single layer film of titanium nitride (TiN) or a multilayer film in which titanium (Ti) is stacked on titanium nitride.

  Here, the Vickers hardness of aluminum is approximately 80, the Vickers hardness of titanium is approximately 100 to 150, and the Vickers hardness of titanium nitride is approximately 300.

  Note that the conductive film 6 has a function of suppressing atomic diffusion of the conductive film 7 and a function of improving adhesion with the insulating film. The conductive film 8 has a function similar to that of the conductive film 6 and further has a function of reducing halation during an exposure process for wiring formation.

  As shown in FIG. 1 ((a), (b)), one end side of a bonding wire 41 made of an Au wire is connected to the electrode pad 14. The Au wire has low bondability with respect to a titanium nitride film or a titanium film, but has high bondability with respect to an Al film or an alloy film mainly composed of Al. Therefore, in order to improve the bondability between the bonding wire 41 and the electrode pad 14, the conductive film 8 in the wire connection region of the electrode pad 14 is removed as shown in FIG. 4, and as shown in FIG. One end side of the wire 41 is connected to the conductive film 7 of the electrode pad 14.

  The wiring 12 and the wiring 5 are not limited to this, but have a multilayer structure in which the conductive films 6, 7, and 8 are sequentially stacked from the semiconductor substrate 1 side, for example, like the electrode pad 14.

  Next, a multi-wiring substrate used for manufacturing the semiconductor device 45 will be described with reference to FIG.

  As shown in FIG. 5, the multi-wiring board 35 has a square shape that intersects the thickness direction, and is rectangular in the first embodiment. A mold region (resin sealing region) 36 is provided on the main surface of the multi-wiring substrate 35, and a plurality of product formation regions (device regions) 37 arranged in a plane are provided in the mold region 36, A chip mounting area is provided in each product formation area 37.

  Each product formation region 37 is partitioned by a scribe line 38, and basically has the same configuration and planar shape as the wiring board 30 shown in FIG. The wiring board 30 is formed by dividing the multi-wiring board 35 along the scribe line 38. In the first embodiment, the multi-wiring board 35 is not limited to this. For example, the multi-wiring board 35 has a configuration (9 × 3) in which nine product formation regions 37 arranged in the X direction are arranged in three stages in the Y direction. Yes.

  Next, the manufacture of the semiconductor device 45 of Example 1 will be described with reference to FIGS.

  In manufacturing the semiconductor device 45 according to the first embodiment, as shown in FIG. The pre-process <100> includes a wafer preparation process <101> to an opening formation process <109>, and the post-process <110> includes a wafer fragmentation process <110> to a substrate fragmentation process <116>.

  First, the pre-process <100> will be described. In the pre-process <100>, as shown in FIG. 7, a plurality of chip formation regions 26 partitioned in a matrix by scribe lines 27 are formed on the main surface of the semiconductor wafer 25. In each chip formation region 26, an integrated circuit and a plurality of electrode pads 14 are formed. Each chip formation region 26 is formed mainly by performing the following steps.

  First, the semiconductor wafer 25 shown in FIG. 8 is prepared (wafer preparation step <101> in FIG. 6). As the semiconductor wafer 25, for example, one made of single crystal silicon is used.

  Next, an element isolation region 3 (see FIG. 9) is formed on the main surface of the semiconductor wafer 25, and then, for example, a MISFET-Q (FIG. 9) as a transistor element in an active region (active region) partitioned by the element isolation region 3. (See FIG. 6 for forming elements <102>).

  Next, an interlayer insulating film 4 (see FIG. 9) is formed on the main surface of the semiconductor substrate 1 so as to cover the MISFET-Q, and then the surface of the interlayer insulating film 4 is subjected to, for example, a CMP (Chemical Mechanical Polishing) method. Then, the first-layer metal wiring 5 (see FIG. 9) is formed on the interlayer insulating film 4.

  Next, an interlayer insulating film 9 (see FIG. 9) is formed on the interlayer insulating film 4 so as to cover the metal wiring 5. The interlayer insulating film 9 has a multilayer structure including an insulating film 10 and an insulating film 11 formed on the insulating film 10. The upper insulating film 11 is made of, for example, a P-TEOS silicon oxide film, and the lower insulating film 10 is made of a low-k material film having a lower dielectric constant and a lower Young's modulus than the insulating film 11.

  Next, after planarizing the surface of the interlayer insulating film 9 by, for example, a CMP method, a second-layer metal wiring 12 (see FIG. 9) is formed on the interlayer insulating film 9.

  Next, an interlayer insulating film 13 (see FIG. 9) is formed on the interlayer insulating film 9 so as to cover the metal wiring 12. The interlayer insulating film 13 has a multilayer structure including the insulating film 10 and the insulating film 11 formed on the insulating film 10. The upper insulating film 11 is made of, for example, a P-TEOS silicon oxide film, and the lower insulating film 10 is made of a low-k material film having a lower dielectric constant and a lower Young's modulus than the insulating film 11.

  Next, after planarizing the surface of the interlayer insulating film 13 by, for example, a CMP method, a conductive film 14a is formed on the interlayer insulating film 13 as a third metal wiring layer as shown in FIG. The conductive film 14 a has a multilayer structure including a conductive film 6, a conductive film 7 formed on the conductive film 6, and a conductive film 8 formed on the conductive film 7. The conductive films 6 and 8 are formed with a film thickness relatively smaller than that of the conductive film 7.

  The conductive film 7 is made of a material that has higher bondability (adhesiveness) with the bonding wire 41 mainly composed of Au than the conductive film 8, and is formed of a conductive film mainly composed of aluminum (Al), for example. The conductive films 6 and 8 are made of a material harder than the conductive film 7, and are formed of, for example, a single layer film of titanium nitride (TiN) or a multilayer film in which titanium (Ti) is stacked on titanium nitride. The conductive film 6 has a function of suppressing atomic diffusion of the conductive film 7 and a function of improving adhesion with the insulating film. The conductive film 8 has a function similar to that of the conductive film 6 and further has a function of reducing halation during an exposure process for wiring formation.

  Next, the conductive film 14a is patterned by etching using a photolithography technique to form an electrode pad 14 on the interlayer insulating film 13 as shown in FIG. In this step, although not shown, a third-layer metal wiring is also formed. Through this step, a thin film laminate 1a having a three-layer metal wiring structure is formed on the main surface of the semiconductor substrate 1 (multilayer wiring layer forming step <103> in FIG. 6).

  Next, the electrical characteristics of the integrated circuit formed in each chip formation region 26 are inspected, and wafer inspection is performed to determine characteristic grades such as non-defective products, defective products, and operating frequencies (probe inspection process <104> in FIG. 6). . As shown in FIG. 12, the wafer inspection is performed by pressing the tip of the probe needle 28 against the conductive film 8 of the electrode pad 14. In wafer inspection, it is necessary to make the plurality of probe needles 28 uniformly contact the plurality of electrode pads 14, so that the tips of the probe needles 28 are pressed against the electrode pads 14 so as to strike the electrode pads 14.

  In this step, an impact when the tip of the probe needle 28 is pressed against the electrode pad 14 is transmitted to the interlayer insulating film 13 below the electrode pad 14, but the electrode pad 14 is placed on the conductive film 7 than the conductive film 7. Since the hard conductive film 8 is provided and the tip of the probe needle 28 is pressed against the hard conductive film 8, the impact during pressure contact is absorbed by the soft conductive film 7 than the hard conductive film 8. The impact transmitted to the interlayer insulating film 13 under the electrode pad 14 can be mitigated. Further, since the electrode pad 14 of Example 1 has a structure in which the conductive film 6 harder than the conductive film 7 is provided under the conductive film 7, the electrode pad 14 is transmitted to the interlayer insulating film 13 under the electrode pad 14. Can be further mitigated. As a result, even if a hard and brittle low-k material film is applied to the interlayer insulating film 13 under the electrode pad 14, a crack or the like generated in the interlayer insulating film 13 due to an impact when the probe needle 28 is pressed against the electrode pad 14. Thus, the reliability of the semiconductor device can be improved.

  The probe needle 28 is pressed against the conductive film 8 that is harder than the conductive film 7. Even in this case, the conductive film 8 is scratched by the pressure contact of the probe needle 28 (pressure contact mark), but the conductive film 7 to which the bonding wire is connected is not attached in the bonding process.

  Next, as shown in FIG. 13, a protective film 16 made of, for example, an inorganic insulating film is formed on the interlayer insulating film 13 so as to cover the electrode pads 14 (protective film forming step <105> in FIG. 6). ). In this step, although not shown, the third-layer metal wiring is also covered with the protective film 16.

  Next, the protective film 16 is patterned by etching to form openings 17 on the electrode pads 14 as shown in FIG. 14 (opening forming step <106> in FIG. 6). In this process, the conductive film 8 in the wire connection region of the electrode pad 14 is also removed by etching, and the conductive film 7 without the pressure contact mark due to the pressure contact of the probe needle 28 is exposed (hard film patterning process < 107>).

  Next, as shown in FIG. 15, a protective film 18 made of, for example, an organic insulating film is formed on the protective film 16 so as to cover the electrode pad 14 (protective film forming step <108> in FIG. 6). Thereafter, the protective film 18 is patterned by etching to form an opening 19 on the electrode pad 14 as shown in FIG. 16 (opening forming step <109> in FIG. 6).

  By this step, as shown in FIG. 7, a plurality of chip formation regions 26 each defined by a scribe line 27 and each having an integrated circuit and a plurality of electrode pads 14 are formed on the main surface of the semiconductor wafer 25. Is done.

Next, the post-process <110> will be described.
First, as shown in FIG. 17, the semiconductor wafer 25 subjected to the previous process is divided along the scribe line 27 to form a plurality of semiconductor chips 20 (wafer fragmentation process <111> in FIG. 6). The division of the semiconductor wafer 25 is performed, for example, by dicing the semiconductor wafer 25 along the scribe line 27.

  Next, as shown in FIG. 18A, the semiconductor chip 20 is bonded and fixed to each product formation region 37 of the multi-wiring substrate 35 with an adhesive interposed therebetween (chip mounting step <112> in FIG. 6). The semiconductor chip 20 is bonded and fixed in a state where the back surface of the semiconductor chip 20 faces the main surface of the multi-wiring substrate 35.

  Next, in each product formation region 37, as shown in FIG. 18B, a plurality of electrode pads 14 of the semiconductor chip 20 and a plurality of electrode pads 31 arranged around the semiconductor chip 20 are connected to a plurality of bonding wires. Electrical connection is made at 41 (wire bonding step <113> in FIG. 6). Through this step, the plurality of semiconductor chips 20 are mounted on the main surface of the multi-wiring substrate 35 so as to correspond to the plurality of product formation regions 37.

  Here, the mounting means a state in which the semiconductor chip is bonded and fixed to the substrate, and the connection pad of the substrate and the connection pad of the semiconductor chip are electrically connected. In the first embodiment, the semiconductor chip 20 is bonded and fixed with an adhesive, and the connection pad (electrode pad 31) of the multi-wiring board 35 and the connection pad (electrode pad 14) of the semiconductor chip 20 are connected. Electrical connection is made by bonding wires 41.

  In this step, one end side of the bonding wire 41 is connected to the conductive film 7 of the electrode pad 14 of the semiconductor chip 20 as shown in FIG. 19, and the other end side is connected to the semiconductor chip 20 as shown in FIG. Are connected to electrode pads 31 arranged around the periphery of the substrate.

  Next, using the batch type transfer molding method, the semiconductor chips 20 mounted in the respective product formation regions 37 are bundled on the main surface of the multi-wiring substrate 35 as shown in FIG. Thus, a resin sealing body 42a to be resin-sealed is formed (resin sealing step <114> in FIG. 6).

  Next, as shown in FIG. 20B, a plurality of solder bumps 43 are formed on the back surface opposite to the main surface of the multi-wiring substrate 35 corresponding to each product formation region 37 (bump formation in FIG. 6). Step <115>). The solder bumps 43 are not limited to this, but, for example, a flux material is applied on the electrode pads 32 on the back surface of the multi-wiring board 35, and then solder balls are supplied onto the electrode pads 32, and then the solder balls are melted. Then, it is formed by bonding with the electrode pad 32.

  Next, the flux used in the solder bump formation process is removed by cleaning, and then, for example, a product name, a company name, a product type, and the like are formed on the upper surface of the resin sealing body 42a corresponding to each product formation region 37 of the multi-wiring board 35. An identification mark such as a production lot number is formed using an ink jet marking method, a direct printing method, a laser marking method, or the like.

  Next, as shown in FIG. 21, the multi-wiring substrate 35 and the resin sealing body 42 a are divided into a plurality of small pieces corresponding to each product formation region 27 (small piece forming step <116> in FIG. 6). For example, the dicing blade 44 is bonded to the dicing sheet 44 shown in FIG. 21 along the scribe line 38 of the multi-wiring board 35 with the dicing blade 38. This is done by dicing. Through this step, the semiconductor device 45 shown in FIG. 1 is almost completed.

  As described above, in the first embodiment, the conductive film 7 and the conductive film 7 are provided on the interlayer insulating film 13 including the insulating film 10 made of the low-k material in the previous process (wafer process). In addition, the electrode pad 14 including the conductive film 8 harder than the conductive film 7 is formed, and then, in the wafer inspection process, the probe needle 28 is pressed against the hard conductive film 8 in the electrode pad 14 to inspect the electrical characteristics. Therefore, the impact at the time of pressure contact is absorbed by the soft conductive film 7 than the hard conductive film 8, and the impact transmitted to the interlayer insulating film 13 below the electrode pad 14 can be mitigated. Further, since the electrode pad 14 of Example 1 has a structure in which the conductive film 6 harder than the conductive film 7 is provided under the conductive film 7, the electrode pad 14 is transmitted to the interlayer insulating film 13 under the electrode pad 14. Can be further mitigated. As a result, even if a hard and brittle low-k material film is applied to the interlayer insulating film 13 under the electrode pad 14, a crack or the like generated in the interlayer insulating film 13 due to an impact when the probe needle 28 is pressed against the electrode pad 14. Thus, the reliability of the semiconductor device can be improved.

  The effect of mitigating the impact transmitted to the interlayer insulating film 13 below the electrode pad 14 during probe needle pressure contact is increased by increasing the thickness of the hard conductive films 6 and 8, but the hard conductive films 6 and 8 are increased. If the film thickness is too thick, the etching time becomes long, and the productivity is lowered. On the other hand, if the hard conductive films 6 and 8 are made too thin, the impact mitigating effect is reduced. Therefore, it is desirable to set the film thickness of the hard conductive films 6 and 8 in consideration of productivity and impact mitigation effect. In particular, since the upper conductive film 8 has a great influence on the impact relaxation effect depending on the film thickness setting, the upper limit is preferably about 100 [nm] and the lower limit is preferably about 10 [nm], for example.

  The conductive film 6 has a function of suppressing atomic diffusion of the conductive film 7 and a function of improving adhesion with the insulating film. The conductive film 8 has a function similar to that of the conductive film 6 and further has a function of reducing halation during an exposure process for wiring formation. Therefore, it is desirable to set the film thickness of the conductive films 6 and 8 in consideration of such a function.

  Further, the impact during the pressure contact of the probe needle 28 is absorbed by the conductive film 7 that is softer than the hard conductive film 8. This shock absorbing effect is increased by increasing the film thickness of the conductive film 7. However, if the film thickness is increased too much in the conductive film 7, the etching time becomes longer. Therefore, it is desirable to set the film thickness of the conductive film 7 in consideration of productivity and impact absorption effect.

  In the wafer inspection process, since the tip of the probe needle 28 is pressed against the conductive film 8 of the electrode pad 14 to inspect the electrical characteristics, the conductive film 8 is scratched by the pressure contact of the probe needle 28 (pressure contact mark). Since the press contact mark deteriorates the bondability between the electrode pad 14 and the bonding wire 41, it is necessary that the press contact mark does not exist in the region where the bonding wire 41 is connected. In the first embodiment, the electrode pad for inspection to which the probe needle is pressed and the electrode pad for wire connection to which the bonding wire is connected are used as one electrode pad 14, but the wafer inspection process <104> Later, before the wire bonding step <113>, the conductive film 8 with the pressure contact mark is removed in the hard film patterning step <107>, and then the pressure contact mark is left in the wire bonding step <113>. Since the bonding wire 41 is connected to the non-conductive film 7, when the electrode pad for inspection to which the probe needle is pressed and the electrode pad for wire connection to which the bonding wire is connected are used as one electrode pad 14. In addition, the bondability between the electrode pad 14 and the bonding wire 41 can be improved.

  Conventionally, a first region where a probe needle is pressed and a second region where a bonding wire is connected to one electrode pad are arranged in a plane, and the electrode pad is caused by a pressure contact mark of the probe needle. There is known a technique for suppressing a decrease in bondability between a bonding wire and a bonding wire. In this case, since the area occupied by the electrode pads increases, it is difficult to reduce the size of the semiconductor chip.

  In contrast, in the first embodiment, since the conductive film 8 of the electrode pad 14 is removed after the wafer inspection process, the first region in which the probe needle 28 is pressed against the electrode pad 14 and the bonding wire to the electrode pad 14. The second region connecting 41 can be overlapped in a plane. Therefore, the area of the first region that has been conventionally provided can be eliminated, and the area occupied by the electrode pad 14 can be reduced, so that the semiconductor chip 20 can be reduced in size.

  In the first embodiment, the example in which the wafer inspection process is performed before the protective film 16 is formed has been described. However, in the second embodiment, the wafer inspection process is performed after the protective film 16 is formed. explain.

22 to 25 are diagrams related to a semiconductor device which is Embodiment 2 of the present invention.
FIG. 22 is a flowchart showing a manufacturing process of a semiconductor device;
23 to 25 are schematic cross-sectional views showing the manufacturing process of the semiconductor device.

  As shown in FIG. 11, after the electrode pad 14 is formed on the interlayer insulating film 13, a protective film 16 is formed on the interlayer insulating film 13 so as to cover the electrode pad 14 (protective film forming step < 105>), and thereafter, the protective film 16 is patterned by etching to form an opening 17 on the electrode pad 14 as shown in FIG. 23 (opening forming step <106> in FIG. 22). In this step, the conductive film 8 of the electrode pad 14 is not removed.

  Next, as shown in FIG. 24, the electrical characteristics are inspected by pressing the tip of the probe needle 28 against the conductive film 8 of the electrode pad 14 (probe inspection step <104>).

  Next, the conductive film 8 of the electrode pad 14 is selectively etched to remove the portion of the conductive film 8 to which the bonding wire is connected as shown in FIG. 25 (hard film patterning step <107 of FIG. 22). >).

  Thereafter, the protective film 18 and the bonding opening 19 are formed in the same manner as in the first embodiment, whereby the pre-process is almost completed.

  In the second embodiment, since the wafer inspection process (probe inspection process <104>) is performed after the protective film 16 is formed, the uppermost wiring layer of the thin film stack 1a is contaminated by foreign matters. Therefore, the manufacturing yield of the semiconductor device can be improved.

  In the first embodiment, the example in which the electrode pad for inspection to which the probe needle is pressed and the electrode pad for wire connection to which the bonding wire is connected is used as one electrode pad has been described. An example in which the inspection electrode pad and the wire connection electrode pad are separated will be described.

26 to 32 are diagrams related to the semiconductor device of the third embodiment.
FIG. 26 is a schematic cross-sectional view showing the internal structure of a semiconductor chip incorporated in a semiconductor device;
FIG. 27 is a schematic plan view showing a wiring pattern;
28 to 32 are schematic cross-sectional views showing the manufacturing process of the semiconductor device.

  As shown in FIG. 26, in the semiconductor chip 20 of the third embodiment, an electrode pad 14 and an inspection electrode pad 47 are provided on the interlayer insulating film 13. As shown in FIGS. 26 and 27, the electrode pad 14 and the inspection electrode pad 47 are formed by a part of the third-layer metal wiring 46 provided on the interlayer insulating film 13 and are electrically connected to each other. Has been. The electrode pad 14 is disposed on the peripheral portion 2 b of the semiconductor chip 20, and the inspection electrode pad 47 is disposed on the active region (active region) of the internal circuit forming portion 2 a of the semiconductor chip 20.

  On the inspection electrode pad 47, an opening 17a formed by etching the protective film 16 is provided, and an opening 19a formed by etching the protective film 18 is further provided. The inspection electrode pad 47 has a multilayer structure similar to that of the electrode pad 14.

  Next, the manufacture of the semiconductor device of Example 3 will be described with reference to FIGS.

  As shown in FIG. 10, a conductive film 14a is formed as a third metal wiring layer on the interlayer insulating film 13, and then the conductive film 14a is patterned by etching using a photolithography technique. As shown in FIG. 3, a metal wiring 46 including the electrode pad 14 and the inspection electrode pad 47 is formed on the interlayer insulating film 13.

  Next, a protective film 16 is formed on the interlayer insulating film 13 so as to cover the metal wiring 46, and then the protective film 16 is patterned by etching, and as shown in FIG. Openings 17a are formed on the openings 17 and the inspection electrode pads 47, respectively. In this step, the conductive film 8 of the electrode pad 14 and the inspection electrode pad 47 is not removed.

  Next, as shown in FIG. 30, the tip of the probe needle 28 is pressed against the conductive film 8 of the inspection electrode pad 47 to inspect the electrical characteristics. In this process, as described in the first embodiment, since the impact transmitted to the interlayer insulating film 13 under the test electrode pad 47 can be reduced, the test is performed on the active region where the transistor element is formed. An electrode pad 47 can be disposed.

  Next, the conductive film 8 on the electrode pad 14 is selectively etched to remove the conductive film 8 at the portion to which the bonding wire is connected, as shown in FIG. In this step, the conductive film 8 of the inspection electrode pad 47 may or may not be removed.

  Next, the protective film 18 is formed on the protective film 16 so as to cover the electrode pad 14 and the inspection electrode pad 47, and then the protective film 18 is patterned by etching, as shown in FIG. In addition, an opening 19 is formed on the electrode pad 14 and an opening 19 a is formed on the inspection electrode pad 47. By this process, the previous process is almost completed.

  Thereafter, as shown in FIG. 32, the bonding wire 41 is connected to the conductive film 7 of the electrode pad 14 in the wire bonding step in the subsequent step.

  Thus, even when the inspection electrode pad 47 to which the probe needle 28 is pressed and the wire connection electrode pad (electrode pad 14) to which the bonding wire 41 is connected are separated, an insulating film made of a low-k material is used. An inspection electrode pad 47 including a conductive film 7 and a conductive film 8 provided on the conductive film 7 and harder than the conductive film 7 is formed on the interlayer insulating film 13 including 10. In the inspection process, the probe needle 28 is pressed against the electrode film 8 of the inspection electrode pad 47 to inspect the electrical characteristics, so that the probe needle 28 is pressed under the inspection electrode pad 47 as in the first embodiment. The impact transmitted to the interlayer insulating film 13 can be mitigated.

  In addition, since the impact transmitted to the interlayer insulating film 13 under the test electrode pad 47 can be reduced, the test electrode pad 47 can be disposed on the active region where the transistor is formed. As a result, the semiconductor chip can be reduced in size as compared with the case where the wire connection electrode pad and the inspection electrode pad are arranged along the side of the semiconductor chip.

  In addition, since the inspection electrode pad 47 can be disposed in the internal circuit forming portion 2a of the semiconductor chip 20, the inspection electrode pad 47 can be increased in size without increasing the size of the semiconductor chip 20. The inspection electrode pad 47 and the probe needle 28 can be easily aligned.

  FIG. 33 is a schematic cross-sectional view illustrating a manufacturing process of a semiconductor device which is a modification of the third embodiment.

  In the above-described third embodiment, the example in which the wafer inspection process is performed after the protective film 16 is formed has been described. However, as in the first embodiment, before the protective film 16 is formed, as shown in FIG. A wafer inspection process may be performed.

  FIG. 34 is a schematic cross-sectional view showing the internal structure of a semiconductor device that is Embodiment 4 of the present invention.

  In the above-described third embodiment, the example in which the conductive film 8 of the inspection electrode pad 47 is removed has been described. However, since the bonding wire 41 is connected to the electrode pad 14, as shown in FIG. The conductive film 8 may not be removed.

  FIG. 35 is a schematic cross-sectional view showing the internal structure of a semiconductor chip incorporated in a semiconductor device that is Embodiment 5 of the present invention.

  As shown in FIG. 35, the metal wiring layer on which the electrode pad 14 is formed may be provided with a power supply wiring 15 extending in a ring shape along the side of the semiconductor chip. In such a case, it is difficult to form the electrode pad 14 and the inspection electrode pad 47 in the same wiring layer as in the third embodiment.

  Therefore, when the power supply wiring 15 extends, as shown in FIG. 35, an inspection electrode pad 52 is formed in a metal wiring layer above the electrode pad 14, and the metal wiring 51 is used to connect the electrode pad 14. The test electrode pad 52 is electrically connected.

  In such a structure, after the opening 17 is formed in the protective film 16, the conductive film 7 and the conductive film 8 are sequentially formed on the protective film 16 including the electrode pad 14, and then the conductive films 8 and 7 are sequentially formed. Patterning is performed to form a metal wiring 51 having an inspection electrode pad 52 on one end side and the other end side being electrically connected to the electrode pad 14 through the opening 17, and then on the electrode pad 14 and the metal wiring 51. A protective film 53 made of an inorganic insulating film is formed on the protective film 16 including the upper part, and then the protective film 53 is etched by etching to remove the protective film 53 on the electrode pad 14 and to inspect the inspection electrode. An opening 54 is formed on the pad 52, and then the protective film 18 is formed on the protective film 53 including the electrode pad 14 and the inspection electrode pad 52, and then the protective film 18 is formed by etching. And turn training, opening 19 on the electrode pad 14 is formed by forming an opening 19a on the inspection electrode pads 52.

  As described above, also in the fifth embodiment, the same effect as in the fourth embodiment described above can be obtained.

  36 to 38 are diagrams for explaining the effect of the present invention. 36 to 38, (a) is a schematic plan view showing a pad arrangement of a conventional semiconductor chip, and (b) is a schematic plan view showing a pad arrangement of a semiconductor chip to which the present invention is applied. In the figure, 14m is a first area where the probe needle is pressed, 14n is a second area where the bonding wire is connected, 28a is a probe pressure mark, 41a is a wire connection mark, and 20a is the periphery (periphery of the semiconductor chip 20). ).

  Conventionally, as shown in FIG. 36A, a first region 14m where a probe needle is pressed against one electrode pad 14 and a second region 14n where a bonding wire is connected are divided in a plane. A technique is known that is arranged and suppresses a decrease in bondability between the electrode pad and the bonding wire due to the probe needle pressure contact mark 28a. In this case, since the area occupied by the electrode pad 14 increases, the semiconductor chip 20 is difficult to downsize.

  On the other hand, in the first embodiment, since the conductive film 8 of the electrode pad 14 is removed after the wafer inspection process, the first region 14m in which the probe needle 28 is pressed against the electrode pad 14 and the bonding to the electrode pad 14 are performed. The second region 14n to which the wire 41 is connected can be overlapped in a plane. Therefore, as shown in FIG. 36B, the area of the first region 14m which has been conventionally provided can be deleted and the area occupied by the electrode pad 14 can be reduced, so that the semiconductor chip 20 can be downsized. Can be achieved.

  Further, since the probe needle pressure contact mark 28a does not exist in the first region 14m provided conventionally, wire bonding can be performed at an arbitrary position of the electrode pad 14 as shown in FIG.

  Further, since the probe needle pressure contact mark 28a does not exist in the first region 14m provided conventionally, as shown in FIG. 38B, a plurality of bonding wires are connected to the same pad such as double bonding (one electrode). A plurality of wire connection marks 41a) can be formed on the pad 14.

As mentioned above, the invention made by the present inventor has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

Claims (39)

(A) forming an interlayer insulating film including a first insulating film and a second insulating film harder than the first insulating film on a semiconductor substrate;
(B) An electrode pad including a first conductive film and a second conductive film stacked on the first conductive film and harder than the first conductive film on the interlayer insulating film. Forming, and
(C) a method of inspecting electrical characteristics by bringing a probe needle into contact with the second conductive film of the electrode pad. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the first insulating film is made of a material having a relative dielectric constant lower than that of the second insulating film. In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the first insulating film is made of a material having a lower relative dielectric constant and Young's modulus than the second insulating film. (A) forming an interlayer insulating film including a first insulating film and a second insulating film harder than the first insulating film on a semiconductor substrate;
(B) An electrode pad including a first conductive film and a second conductive film stacked on the first conductive film and harder than the first conductive film on the interlayer insulating film. Forming, and
(C) inspecting electrical characteristics by bringing a probe needle into contact with the second conductive film of the electrode pad;
(D) removing the second conductive film of the electrode pad;
(E) connecting a bonding wire to the first conductive film of the electrode pad. In the manufacturing method of the semiconductor device according to claim 4,
The method of manufacturing a semiconductor device, wherein the first insulating film is made of a material having a relative dielectric constant lower than that of the second insulating film. In the manufacturing method of the semiconductor device according to claim 4,
The method for manufacturing a semiconductor device, wherein the first insulating film is made of a material having a lower relative dielectric constant and Young's modulus than the second insulating film. In the manufacturing method of the semiconductor device according to claim 4,
The method of manufacturing a semiconductor device, wherein the first conductive film is made of a material having higher adhesion to the bonding wire than the second conductive film. In the manufacturing method of the semiconductor device according to claim 4,
The method for manufacturing a semiconductor device, wherein the second conductive film is made of a material having a reflectance lower than that of the first conductive film. In the manufacturing method of the semiconductor device according to claim 4,
The method of manufacturing a semiconductor device, wherein the second conductive film is thinner than the first conductive film. In the manufacturing method of the semiconductor device according to claim 4,
The method of manufacturing a semiconductor device, wherein the electrode pad includes a third conductive film that is harder than the first conductive film in a lower layer of the first conductive film. In the manufacturing method of the semiconductor device according to claim 4,
The first conductive film is made of a material mainly composed of aluminum,
The second conductive film is a single layer film of titanium nitride or a laminated film in which titanium nitride is stacked on titanium.
The method of manufacturing a semiconductor device, wherein the bonding wire is made of a material mainly composed of gold. In the manufacturing method of the semiconductor device according to claim 4,
The method of manufacturing a semiconductor device, wherein the electrode pad is formed by patterning the second and first conductive films using a photolithography technique. In the manufacturing method of the semiconductor device according to claim 4,
After the step (c) and before the step (e), a step of forming a protective film on the interlayer insulating film so as to cover the electrode pad, and etching the protective film to Forming an opening on the electrode pad,
The method of manufacturing a semiconductor device, wherein the step (d) is performed in the opening forming step. In the manufacturing method of the semiconductor device according to claim 4,
After the step (b) and before the step (c), a step of forming a protective film on the interlayer insulating film so as to cover the electrode pad, and etching the protective film to And a step of forming an opening on the electrode pad. In the manufacturing method of the semiconductor device according to claim 4,
The semiconductor substrate has a plurality of regions each defined by a scribe line, and each formed with the interlayer insulating film and the electrode pad,
A step of forming a plurality of semiconductor chips by dividing the semiconductor substrate along the scribe line after the step (d) and before the step (e). A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 4,
The step (e) is a method of electrically connecting the electrode pad and a connection portion disposed around the semiconductor substrate with the bonding wire. (A) forming a plurality of chip formation regions on the semiconductor wafer, each of which is partitioned by a scribe line, and each having an integrated circuit and a plurality of electrode pads;
(B) dividing the semiconductor wafer along the scribe line to form a plurality of semiconductor chips each having the integrated circuit and a plurality of electrode pads;
(C) electrically connecting a plurality of electrode pads of the semiconductor chip and a plurality of connection portions arranged around the semiconductor chip with a plurality of bonding wires;
The step (a)
(A1) forming an interlayer insulating film including a first insulating film and a second insulating film harder than the first insulating film on the semiconductor wafer;
(A2) An electrode pad including a first conductive film and a second conductive film stacked on the first conductive film and harder than the first conductive film on the interlayer insulating film. Forming, and
(A3) inspecting electrical characteristics by bringing a probe needle into contact with the second conductive film of the electrode pad;
(A4) after the step (a3), the step of removing the second conductive film of the electrode pad,
In the step (c), the bonding wire is connected to a second conductive film of the electrode pad. In the manufacturing method of the semiconductor device according to claim 17,
The method of manufacturing a semiconductor device, wherein the first insulating film is made of a material having a relative dielectric constant lower than that of the second insulating film. In the manufacturing method of the semiconductor device according to claim 17,
The method for manufacturing a semiconductor device, wherein the first insulating film is made of a material having a lower relative dielectric constant and Young's modulus than the second insulating film. In the manufacturing method of the semiconductor device according to claim 17,
The method of manufacturing a semiconductor device, wherein the first conductive film is made of a material having higher adhesion to the bonding wire than the second conductive film. In the manufacturing method of the semiconductor device according to claim 17,
The method for manufacturing a semiconductor device, wherein the second conductive film is made of a material having a reflectance lower than that of the first conductive film. (A) forming an interlayer insulating film including a first insulating film and a second insulating film harder than the first insulating film on a semiconductor substrate;
(B) A laminated film including a first conductive film and a second conductive film laminated on the first conductive film and harder than the first conductive film on the interlayer insulating film. Forming, and
(C) patterning the laminated film to form first and second electrode pads electrically connected to each other on the interlayer insulating film;
(D) inspecting electrical characteristics by bringing a probe needle into contact with the second conductive film of the first electrode pad;
(E) removing the second conductive film of the first electrode pad;
(F) connecting a bonding wire to the first conductive film of the first electrode pad. A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 22,
A step of forming a plurality of transistor elements in the first region of the semiconductor substrate before the step (a);
The second electrode pad is formed on the first region of the semiconductor substrate,
The method of manufacturing a semiconductor device, wherein the first electrode pad is formed on a second region around the first region of the semiconductor substrate. In the manufacturing method of the semiconductor device according to claim 22,
The semiconductor substrate has a chip formation region partitioned by a scribe line,
The chip formation region has a first region where a plurality of transistor elements are formed, and a second region disposed around the first region,
The second electrode pad is formed on the first region;
The method of manufacturing a semiconductor device, wherein the first electrode pad is formed on the second region. In the manufacturing method of the semiconductor device according to claim 22,
The method of manufacturing a semiconductor device, wherein the first insulating film is made of a material having a relative dielectric constant lower than that of the second insulating film. In the manufacturing method of the semiconductor device according to claim 22,
The method for manufacturing a semiconductor device, wherein the first insulating film is made of a material having a lower relative dielectric constant and Young's modulus than the second insulating film. In the manufacturing method of the semiconductor device according to claim 22,
The method of manufacturing a semiconductor device, wherein the first conductive film is made of a material having higher adhesion to the bonding wire than the second conductive film. In the manufacturing method of the semiconductor device according to claim 22,
The method for manufacturing a semiconductor device, wherein the second conductive film is made of a material having a reflectance lower than that of the first conductive film. (A) forming a first interlayer insulating film including a first insulating film and a second insulating film harder than the first insulating film on a semiconductor substrate;
(B) forming a first electrode pad on the first interlayer insulating film;
(C) forming a second interlayer insulating film on the first interlayer insulating film;
(D) forming a second electrode pad electrically connected to the first electrode pad on the second interlayer insulating film;
(E) inspecting electrical characteristics by bringing a probe needle into contact with the second electrode pad;
(F) connecting a bonding wire to the first electrode pad;
The second electrode pad includes a first conductive film, and a second conductive film that is stacked on the first conductive film and is harder than the first conductive film,
The step (e) is performed by bringing the probe needle into contact with the second conductive film of the second electrode pad. The method of manufacturing a semiconductor device according to claim 29,
The semiconductor substrate has a chip formation region partitioned by a scribe line,
The chip formation region has a first region where a plurality of transistor elements are formed, and a second region disposed around the first region,
The second electrode pad is formed on the first region;
The method of manufacturing a semiconductor device, wherein the first electrode pad is formed on the second region. The method of manufacturing a semiconductor device according to claim 29,
The method of manufacturing a semiconductor device, wherein the first insulating film is made of a material having a relative dielectric constant lower than that of the second insulating film. The method of manufacturing a semiconductor device according to claim 29,
The method for manufacturing a semiconductor device, wherein the first insulating film is made of a material having a lower relative dielectric constant and Young's modulus than the second insulating film. The method of manufacturing a semiconductor device according to claim 29,
The first electrode pad includes a third conductive film, and a fourth conductive film that is stacked on the third conductive film and has a lower reflectance than the third conductive film,
A step of removing the fourth conductive film before the step (f);
The method of manufacturing a semiconductor device, wherein the bonding wire is connected to a third conductive film of the first electrode pad. A semiconductor chip having first and second electrode pads electrically connected to each other on a main surface;
A bonding wire for electrically connecting the first electrode pad of the semiconductor chip and a connection portion disposed around the semiconductor chip;
The first and second electrode pads are disposed on an interlayer insulating film including a first insulating film and a second insulating film harder than the first insulating film,
The second electrode pad is formed of a stacked film including a first conductive film and a second conductive film that is stacked on the first conductive film and is harder than the first conductive film. A semiconductor device characterized by the above. The semiconductor device according to claim 34, wherein
The semiconductor chip has a first region in which a plurality of transistor elements are formed, and a second region disposed around the first region,
The second electrode pad is disposed on the first region;
The semiconductor device according to claim 1, wherein the first electrode pad is disposed on the second region. The semiconductor device according to claim 34, wherein
The semiconductor device according to claim 2, wherein the second electrode pad is an inspection pad to which a probe needle is pressed when inspecting electrical characteristics. The semiconductor device according to claim 34, wherein
The semiconductor device according to claim 1, wherein the first insulating film is made of a material having a relative dielectric constant and Young's modulus lower than those of the second insulating film. The semiconductor device according to claim 34, wherein
The semiconductor device, wherein the first and second electrode pads are formed in the same layer. The semiconductor device according to claim 34, wherein
The semiconductor device, wherein the second electrode pad is formed in an upper layer than the first electrode pad.

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