JP4850852B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device manufacturing technique.

A semiconductor device incorporated in a small electronic device such as a mobile phone, a portable information processing terminal device, or a portable personal computer is required to be thin, small, and multi-pinned. Suitable semiconductor devices such demands, a semiconductor device is known which is referred for example, CSP (C hip S ize P ackage ) type. In this CSP type semiconductor device, devices having various structures have been proposed and commercialized. One of them is the integration of the wafer process and the package process, and the packaging process is performed in the wafer state. A CSP type semiconductor device (hereinafter referred to as a wafer level CSP type semiconductor device) manufactured by a technique to be completed is also known. This wafer level CSP type semiconductor device is manufactured by performing a package process for each semiconductor chip formed by separating a semiconductor wafer because the planar size of the package is almost the same as the planar size of the semiconductor chip. Compared with a CSP type semiconductor device (referred to as a chip level CSP type semiconductor device), the size and cost can be reduced.

  The wafer level CSP type semiconductor device mainly includes a chip layer corresponding to a semiconductor chip, a rewiring layer (secondary wiring forming layer) provided on the main surface of the chip layer, and a rewiring layer on the rewiring layer. It has a configuration having solder bumps (protruding electrodes) provided as external connection terminals. The chip layer covers a semiconductor substrate, a multilayer wiring layer (primary wiring formation layer) formed by stacking a plurality of insulating layers and wiring layers on the main surface of the semiconductor substrate, and the multilayer wiring layer. Thus, the surface protective film is formed. In the chip layer, an electrode pad (bonding pad) is formed in the uppermost wiring layer in the primary wiring forming layer, and a bonding opening for exposing the electrode pad is formed in the surface protective film. .

  The secondary wiring formation layer rearranges electrode pads having a wider arrangement pitch than the electrode pads of the primary wiring formation layer, corresponding to the arrangement pitch of the electrode pads of the wiring board (mounting board) on which the semiconductor device is mounted. It is a layer (interposer) for. The electrode pad of the secondary wiring formation layer is electrically connected to the electrode pad of the primary wiring formation layer, and the solder bump is electrically and mechanically connected to the electrode pad of the secondary wiring formation layer.

  The wafer level CSP type semiconductor device is disclosed in, for example, Japanese Patent Laid-Open No. 2002-305285 (Patent Document 1).

JP 2002-305285 A

  In the manufacture of a wafer level CSP type semiconductor device, a semiconductor wafer is divided into pieces and divided into semiconductor devices along a scribe line so that each of the integrated circuit, the plurality of first electrode pads, After forming a plurality of semiconductor chips having the plurality of second electrode pads, a burn-in (aging) process is performed. The burn-in process operates a semiconductor device circuit under conditions that are severer than those used by the customer (in a state where a load is applied), and causes defects during use by the customer. In a sense, the defects are accelerated. This is a screening test (to eliminate devices with inherent defects and potential failure factors) in the initial stage before they are generated and shipped to the customer.

  In the burn-in process, a semiconductor device is mounted on the socket, and the electrical connection between the semiconductor device and the burn-in board is performed via the socket. Since the electrical connection between the socket and the semiconductor device is performed by pressing the solder bump of the semiconductor device onto the contact pin of the socket, the scraped part (part) of the solder bump due to rubbing at the time of the press contact or the like is brought into contact pin. Adhere to. In the burn-in process, since a plurality of sockets are repeatedly used, the usage frequency of one socket being repeatedly used per day varies depending on the production amount of the semiconductor device and the number of sockets used. It reaches. That is, scraps of solder bumps accumulate on the contact pins in accordance with the usage frequency of the socket.

  The scraps accumulated on the contact pins are detached from the contact pins and adhere to the mounting surface of the semiconductor device (the surface facing the substrate during mounting) as a foreign matter due to some influence. In addition, scraps of solder bumps due to rubbing or the like at the time of pressure bonding also adhere to the mounting surface of the semiconductor device as foreign matter for some reason.

  The wafer level CSP type semiconductor device is provided with a secondary wiring forming layer (rewiring layer) on the mounting surface side. The secondary wiring forming layer includes an electrode pad and a secondary wiring of the primary wiring forming layer. A plurality of wirings (rewiring) for electrically connecting the electrode pads of the formation layer are formed. The plurality of rewirings are covered with an insulating layer formed on the upper layer, and the insulating layer is formed with a very small thickness of about 2 to 3 [μm], for example. Since the interval between adjacent rewirings is as narrow as about 10 [μm] when the interval between adjacent rewirings is small, when the above-mentioned foreign matter adheres to the mounting surface of the semiconductor device, the insulating layer is pierced to contact the rewiring and adjacent rewiring Cause a malfunction such as short circuit.

  Since it is difficult to avoid adhesion of foreign matters in the burn-in process, it is essential to remove foreign matters in the final stage after the burn-in process. Until now, foreign matter removal has been performed with vacuum tweezers by hand, so the foreign matter removal work time has been enormous (20 hr / K), and workability has been significantly reduced. In addition, it has been a factor in increasing the product cost. Further, since the foreign matter is removed manually, the removal of the foreign matter is likely to vary, which causes a decrease in product yield.

  Also in the manufacture of a wafer level type semiconductor device, a characteristic evaluation test for evaluating electrical characteristics as to whether or not the semiconductor device operates normally is performed in a selection (test) process after the burn-in process. Also in this characteristic evaluation test, the semiconductor device and the performance board (inspection wiring board) are electrically connected through the socket, so that the foreign matter caused by scraped solder bumps on the mounting surface of the semiconductor device also in the sorting process Adhere to.

  In addition, the semiconductor wafer is usually diced by dicing. In the manufacture of a chip level CSP type semiconductor device having a wire bonding process, dicing to separate a semiconductor wafer into a plurality of semiconductor chips is performed in a clean room. Therefore, even in a wafer level CSP type semiconductor device, a plurality of semiconductor wafers are provided. Dicing into individual semiconductor devices is performed in a clean room, but since the process after separation is performed in a non-clean room, in addition to the above-mentioned foreign matter due to solder bump scraping, other foreign matters are also present in the semiconductor device. May adhere to the mounting surface.

  An object of the present invention is to provide a technique capable of reducing the cost of a semiconductor device.

  Another object of the present invention is to provide a technique capable of improving the product yield of a semiconductor device.

  The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
(1) A method of manufacturing a semiconductor device,
Forming a plurality of product formation regions having a circuit and a plurality of first electrode pads on a main surface of a semiconductor wafer;
Rearranging a plurality of second electrode pads having a wider array pitch than the first electrode pads in each of the product formation regions;
A plurality of product formation regions of the semiconductor wafer are singulated to form a plurality of semiconductor devices having the circuit, the plurality of first electrode pads, and the plurality of second electrode pads on a first surface side. And a process of
After the step of separating the plurality of product forming regions into individual pieces, there is a step of removing foreign matters adhering to the first surface of the semiconductor device by cleaning.
(2) In the means (1),
The cleaning step is performed by spraying a plurality of pulverized dry ice onto the first surface of the semiconductor device.
(3) In the means (2),
The pulverized dry ice has a particle size of 0.1 mm to 0.3 mm.
(4) In the means (1),
Further, before the step of dividing the plurality of product formation regions into individual pieces, a step of forming bumps on the second electrode pads in each of the product formation regions is provided.
(5) In the means (1),
The method further includes a step of attaching the semiconductor device to a socket and performing burn-in.
(6) In the means (5),
The step of dividing the plurality of product formation regions into pieces is performed in a clean room,
The burn-in process is performed in a non-clean room.
(7) In the means (1),
Further, the method includes a step of performing a characteristic evaluation test by mounting the semiconductor device on a socket.
(8) In the means (7),
The step of dividing the plurality of product formation regions into pieces is performed in a clean room,
The characteristic selection test is performed in a non-clean room.
(9) In the method for manufacturing a semiconductor device,
A plurality of product formation regions partitioned by a separation region, wherein each of the plurality of product formation regions is disposed on a first surface and a second surface located on opposite sides of each other and on the second surface; Preparing a multi-piece substrate having a plurality of electrode pads;
Mounting a semiconductor chip on each first surface of the plurality of product formation regions;
Forming a resin encapsulant that collectively encapsulates the plurality of semiconductor chips mounted in the plurality of product formation regions;
The resin-encapsulated body and the multi-cavity substrate are divided into a plurality of individual pieces, the wiring substrate comprising the product formation region, the semiconductor chip mounted on the first surface of the wiring substrate, and the semiconductor Forming a plurality of semiconductor devices having a resin sealing body in which a chip is resin-sealed;
And a step of removing foreign matters adhering to the second surface opposite to the first surface of the wiring board by cleaning.
(10) In the means (9),
The cleaning step is performed by spraying a plurality of pulverized dry ice onto the first surface of the semiconductor device.
(11) In the means (10),
The pulverized dry ice has a particle size of 0.1 mm to 0.3 mm.
(12) In the means (9),
Further, before the step of dividing the plurality of product formation regions into individual pieces, a step of forming bumps on the electrode pads on the second surface of each of the product formation regions is provided.
(13) In the means (9),
The method further includes a step of attaching the semiconductor device to a socket and performing burn-in.
(14) In the means (9),
Further, the method includes a step of performing a characteristic evaluation test by mounting the semiconductor device on a socket.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  According to the present invention, the cost of the semiconductor device can be reduced.

  According to the present invention, it is possible to improve the product yield of semiconductor devices.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment of the invention, and the repetitive description thereof is omitted.

(Embodiment 1)
In the first embodiment, an example in which the present invention is applied to a wafer level CSP type semiconductor device will be described.

FIG. 1 is a schematic plan view showing the structure on the mounting surface side of the semiconductor device of Embodiment 1;
FIG. 2 is a schematic cross-sectional view showing a main part of the internal structure of the semiconductor device according to the first embodiment.
FIG. 3 is a schematic plan view of an essential part showing a wiring pattern on the mounting surface side of the semiconductor device of Embodiment 1.
FIG. 4 is a flowchart showing the manufacturing process of the semiconductor device of Embodiment 1.
FIG. 5 is a schematic plan view of a semiconductor wafer used for manufacturing the semiconductor device of Embodiment 1.
6 to 13 are schematic plan views showing the manufacturing process of the semiconductor device of Embodiment 1.
FIG. 14 is a schematic plan view showing a state in which foreign matter has adhered to the mounting surface of the semiconductor device,
FIG. 15 is a diagram showing a schematic configuration of an automatic foreign matter cleaning apparatus used for manufacturing the semiconductor device of Embodiment 1.
FIG. 16 is a schematic diagram for explaining dry ice cleaning,
FIG. 17 is a schematic diagram for explaining air blow cleaning,
FIG. 18 is a schematic diagram for explaining blast cleaning,
FIG. 19 is a schematic diagram for explaining wet cleaning.

  In order to make the drawings easier to see, the solder bumps shown in FIG. 2 are omitted in FIGS.

  As shown in FIGS. 1 and 2, the wafer level CSP type semiconductor device 1 has a rectangular planar shape that intersects the thickness direction. In the first embodiment, for example, 11.0 [mm] × 11. .0 [mm] square. As shown in FIG. 2, the semiconductor device 1 mainly includes a chip layer 1a corresponding to a semiconductor chip, and a rewiring layer (secondary wiring formation) provided on the main surface (circuit formation surface) of the chip layer 1a. Layer) 1b and a plurality of solder bumps (projecting electrodes) 9 provided as external connection terminals on the rewiring layer 1b.

  The chip layer 1a includes a semiconductor substrate 2, a multilayer wiring layer (primary wiring forming layer) 3 formed by stacking a plurality of insulating layers and wiring layers on the main surface of the semiconductor substrate 2, and the multilayer wiring. The surface protective film 5 is formed so as to cover the layer 3. The semiconductor substrate 2 is made of, for example, single crystal silicon, the insulating layer of the primary wiring forming layer 3 is made of, for example, a silicon oxide film, and the wiring layer of the primary wiring forming layer 3 is made of, for example, aluminum (Al) or an aluminum alloy, Alternatively, it is formed of a metal film such as copper (Cu) or a copper alloy. The surface protective film 5 is formed of, for example, a multilayer film in which an inorganic insulating film and an organic insulating film such as a silicon oxide film or a silicon nitride film are stacked.

  On the main surface of the chip layer 1a, for example, a plurality of electrode pads 4 (bonding pads) are formed as connection portions. The plurality of electrode pads 4 are arranged, for example, along each side of the chip layer 1a (semiconductor device 1). Each of the plurality of electrode pads 4 is formed in the uppermost wiring layer of the primary wiring forming layer 3. The uppermost wiring layer of the primary wiring forming layer 3 is covered with a surface protective film 5 formed thereabove, and a bonding opening 5 a that exposes the surface of the electrode pad 4 is formed in the surface protective film 5. ing.

  Each of the plurality of electrode pads 4 has a square shape intersecting with the thickness direction, for example, a square shape of 50 [μm] × 50 [μm]. Each of the plurality of electrode pads 4 is mainly arranged at an arrangement pitch of about 40 to 65 [μm].

  As shown in FIGS. 2 and 3, the secondary wiring formation layer 1 b mainly includes an insulating layer 6 provided on the surface protective film 5 and a plurality of rewirings 7 extending on the insulating layer 6. The plurality of electrode pads 7 a provided on the insulating layer 6 and the insulating layer 8 provided on the insulating layer 6 so as to cover the plurality of rewirings 7 are configured.

  One end sides of the plurality of rewirings 7 are electrically connected to the corresponding electrode pads 4 through the bonding openings 6 a formed in the insulating layer 6 and the bonding openings 5 a formed in the surface protective film 5. The other end side of each of the plurality of rewirings 7 opposite to the one end side is formed integrally with the corresponding electrode pad 7a and electrically connected thereto.

  The plurality of electrode pads 7 a are arranged in a matrix within a region surrounded by the plurality of electrode pads 4. The plurality of electrode pads 7a have a planar shape that intersects the thickness direction, for example, in a circular shape, and in the first embodiment, for example, the diameter has a size of about Φ0.2 [mm]. The plurality of electrode pads 7a are arranged with an arrangement pitch larger than that of the electrode pads 4, and are arranged at an arrangement pitch of, for example, about 0.5 [mm] in the first embodiment.

  A plurality of solder bumps 9 are electrically and mechanically connected to the plurality of electrode pads 7a through bonding openings 8a formed in the insulating layer 8, respectively. The solder bump 9 is made of, for example, a metal material (Pb-free material) having a Sn—Ag—Cu composition.

  The secondary wiring formation layer 1b has an electrode pad 7a having a wider arrangement pitch than the electrode pads 4 of the primary wiring formation layer 3 corresponding to the arrangement pitch of the electrode pads of the wiring board (mounting board) on which the semiconductor device is mounted. It is a layer (interposer) for rearranging.

  In the secondary wiring formation layer 1b, the insulating layers 6 and 8 reduce the concentration of stress generated by the difference in thermal expansion coefficient from the wiring board on the solder bump 9 after the semiconductor device is mounted on the wiring board. It is formed of a material having a lower elastic modulus than that of a silicon nitride film or a silicon oxide film, and further has a thickness greater than that of the surface protective film. In the first embodiment, the insulating layers 6 and 8 are made of, for example, a polyimide resin.

  By using a wiring having a lower resistance, a lower capacity, and a lower impedance than the wiring of the primary wiring forming layer as the rewiring 7 of the secondary wiring forming layer 1b, the arrangement of the electrode pads 7a can be set more freely. . In the first embodiment, the rewiring 7 is formed of, for example, a Cu film having high conductivity, and is preferably formed of a conductive film that is thicker than the wiring of the primary wiring forming layer 3. It is desirable to use an organic insulating film having a lower dielectric constant as compared with the inorganic interlayer insulating film used for the primary wiring forming layer 3 as the insulating layer 8 covering.

  Although not shown, the rewiring 7 is provided with an inspection electrode pad used in the probe inspection process, and the insulating layer 8 is provided with an opening for exposing the surface of the inspection electrode pad. It has been.

  An integrated circuit is formed on the main surface side of the chip layer 1a. This integrated circuit is mainly composed of transistor elements formed on the main surface of the semiconductor substrate and wiring formed on the primary wiring forming layer 3.

  Next, the manufacture of the semiconductor device 1 according to the first embodiment will be described with reference to FIGS.

  In the manufacture of the semiconductor device 1 according to the first embodiment, as shown in FIG. 4, the wafer preparation process <101> to the probe inspection process <106> are referred to as the previous process <100>, and the singulation process <111> to The process up to the shipping process <119> is referred to as a post-process <110>.

  First, as shown in FIG. 5, a semiconductor wafer 10 made of, for example, single crystal silicon is prepared as a semiconductor wafer (wafer preparation step <101> in FIG. 4).

  Next, as shown in FIGS. 6 and 7, a plurality of product formation regions (chip formation regions / device formation regions) 12 having circuits and a plurality of electrode pads 4 on the main surface (circuit formation surface) of the semiconductor wafer 10. Are formed in a matrix (circuit formation step <102> in FIG. 4). The plurality of product formation regions 12 are partitioned by a separation region (scribe region) 11 and are arranged in a state of being separated from each other. The plurality of product formation regions 12 mainly form a primary wiring forming layer (multilayer wiring layer) 3 including transistor elements and electrode pads 4, a surface protective film 5, a bonding opening 5 a and the like on the main surface of the semiconductor wafer 10. Formed by.

  Next, a secondary wiring forming layer (rewiring layer) 1b is formed in each product forming region 12 (rewiring step <103> in FIG. 4).

  Specifically, first, an insulating layer 6 made of, for example, a polyimide resin is formed on the entire surface of the surface protective film 5 by a spin coating method, and then the electrode pad 4 is formed on the insulating layer 6 as shown in FIG. A bonding opening 6a exposing the surface is formed.

Pattern is then formed on the entire surface conductive film as for example, copper (Cu) film on the insulating layer 6 containing the bonding openings 6a in the low-pressure CVD (C hemical V apor D eposition ) or sputtering, and then the copper film The rewiring 7 and the electrode pad 7a are formed as shown in FIG.

  Next, an insulating layer 8 made of, for example, a polyimide resin is formed on the entire surface of the insulating layer 6 including the rewiring 7 by a spin coating method, and then the electrode pad 7a is formed on the insulating layer 8 as shown in FIG. A bonding opening 8a that exposes the surface is formed.

  Next, as shown in FIG. 10, for example, an Au film 9a is formed on the surface of the electrode pad 7a exposed from the bonding opening 8a by a plating method. As a result, the secondary wiring formation layer 1b is formed, and the electrode pads 7a having an arrangement pitch wider than the arrangement pitch of the electrode pads 4a are formed.

  Next, as shown in FIG. 11, solder bumps 9 are formed on the electrode pads 7a in each product formation region 12 of the semiconductor wafer 1 (bump formation step <104> in FIG. 4). The formation of the solder bump 9 is not limited to this. For example, a flux material is applied on the electrode pad 7a, and then a solder ball is supplied onto the electrode pad 7a by a ball supply method, and then the solder ball is infrared reflowed. Melt by the method. The solder bumps 9 may be formed by, for example, providing a solder paste material on the electrode pad 9B by a screen printing method and then melting the solder paste material by an infrared reflow method.

  Next, the flux used in the solder bump formation step <104> is removed by cleaning, and then a test for electrically inspecting the circuit function of each product formation region 12 is performed using a probe card (FIG. 4). Probe inspection <106>). The probe inspection is performed by pressing the probe needle of the probe card against the test electrode pad provided on the rewiring 7 (probe inspection <106>).

Next, as shown in FIGS. 12 and 13, the semiconductor wafer 10 is divided into a plurality of pieces (individualization step <111> in FIG. 4). This division is performed by, for example, dicing the semiconductor wafer 10 along the separation region (scribe region) 11 of the semiconductor wafer 10. In addition, this division is performed in a clean room in an environment where foreign matters of 0.5 [μm] or less are 1000 pieces / cm ³ or less. Through this step, the semiconductor device 1 of the first embodiment shown in FIG. 1 is almost completed.

  Next, the separated semiconductor device 1 is packed in a tray (the jig packing step <112> in FIG. 4), and then the semiconductor device 1 is transported to the marking step in a state of being packed in the tray. For example, identification marks such as a product name, a company name, a product type, and a production lot number are formed on the surface opposite to the mounting surface of the device 1 (the surface facing the substrate during mounting) (marking step <113> in FIG. 4). The identification mark is formed using an inkjet marking method, a direct printing method, a laser marking method, or the like.

  Next, the semiconductor device 1 is transported to a burn-in process while being packed in a tray, and then burn-in is performed on the semiconductor device 1 (burn-in process <114> in FIG. 4). In the burn-in process, the semiconductor device 1 is mounted in a socket, and the semiconductor device 1 and the burn-in board are electrically connected via the socket. The electrical connection between the socket and the semiconductor device 1 is performed by pressing the solder bumps 9 of the semiconductor device 1 against the socket contact pins. Adheres to the contact pins. In the burn-in process, since a plurality of sockets are repeatedly used, the usage frequency of one socket being repeatedly used per day varies depending on the production amount of the semiconductor device and the number of sockets used. It reaches. That is, scraps of the solder bumps 9 are accumulated on the contact pins in accordance with the usage frequency of the socket.

  The scraps accumulated on the contact pins are detached from the contact pins and adhere to the mounting surface of the semiconductor device 1 as foreign matter 28 due to some influence as shown in FIG. Further, the scrap of the solder bump due to rubbing or the like at the time of pressure bonding also adheres to the mounting surface of the semiconductor device 1 as a foreign substance due to some influence. Further, in the wafer level CSP type semiconductor device 1 of the first embodiment, dicing for dividing the semiconductor wafer 10 into a plurality of semiconductor devices 1 is performed in a clean room, but the process after the separation is performed in a non-clean room. Therefore, in addition to the above-described foreign matter due to the removal of the solder bump 9, other foreign matter may adhere to the mounting surface of the semiconductor device 1.

  Next, a characteristic evaluation test for evaluating whether or not the semiconductor device 1 operates normally is performed to select the characteristics of the semiconductor device 1 (selecting step <115> in FIG. 4). Also in this characteristic evaluation test, the semiconductor device 1 is mounted on the socket, and the semiconductor device 1 and the performance board (inspection wiring board) are electrically connected via the socket. Foreign matter due to 10 scraps is attached to the mounting surface of the semiconductor device.

  Next, the foreign matter adhering to the mounting surface of the semiconductor device 1 is removed by cleaning. The removal of foreign matters is performed by dry ice cleaning using an automatic foreign matter cleaning apparatus 20 shown in FIG. The automatic foreign matter cleaning apparatus 20 supplies the liquefied carbon 21 to the pelletizer 22, forms pellet-shaped dry ice 23 with the pelletizer 22, and the pellet-shaped dry ice 23 is crushed by the crusher 24. (Crushed dry ice) 25 is formed, and in the cleaning device 26, the crushed dry ice 25 is sprayed from the nozzle 26a onto the mounting surface of the semiconductor device 1 mounted on the set jig, and the semiconductor device 1 is mounted on the mounting surface. The adhering foreign matter 28 is removed. The foreign matter 28 removed from the mounting surface of the semiconductor device 1 is collected by the dust collection unit 27. The supply of the semiconductor device 1 to the setting jig is sequentially performed from the tray 29a mounted on the loader side. The semiconductor devices 1 subjected to the dry ice cleaning are sequentially stored in the tray 29b on the unloader side.

  Next, as shown in FIG. 4, the final appearance inspection <117> of the semiconductor device 1 is performed, and then the semiconductor device 1 is packed <118>, and then the semiconductor device 1 is shipped as a product <119>.

  Here, the dry ice cleaning will be briefly described with reference to FIG.

The pulverized dry ice 25 sprayed on the product from the nozzle 25a collides with dirt (foreign matter), then deforms, and then vaporizes. Dirt (foreign matter) is peeled off by the impact when the crushed dry ice 25 collides. The removal performance of foreign matters by dry ice cleaning varies depending on the particle size of the pulverized dry ice 25, the ejection pressure from the nozzle 26a, the ejection distance from the nozzle 26a to the object, and the like. According to the study of the present inventor, semiconductor wafers are conditioned on the condition that the particle size of pulverized dry ice is 0.1 mm to 0.3 mm, the ejection pressure is 0.5 to 2.0 kg / cm ² , and the ejection distance is 30 mm. The foreign matter adhering to the mounting surface of the semiconductor device 1 in the subsequent process after the separation into individual pieces could be removed cleanly in the shortest time.

  In the manufacture of the wafer level CSP type semiconductor device 1, foreign substances are removed by various cleaning methods in the wafer process (pre-process), but no foreign substances have been removed by cleaning in the post-process. In particular, there has been no foreign matter removal by cleaning before the final appearance inspection <117>. Foreign matter removal by cleaning can be performed in a short time compared to manual foreign matter removal, and there are few variations in foreign matter removal. Accordingly, the time required for removing the foreign matter can be shortened by removing the foreign matter in the subsequent process by cleaning, so that the cost of the semiconductor device 1 can be reduced. In addition, since there is little variation in foreign matter removal, the product yield of the semiconductor device 1 can be improved.

  In the first embodiment, dry ice cleaning is used as a foreign matter removal in a subsequent process. The pulverized dry ice sublimes after colliding with foreign matter. Accordingly, steps such as a water washing process and a drying process after removing the foreign matter are not required, and thus the cost of the semiconductor device 1 can be further reduced and the product yield can be improved.

  Foreign matter removal by washing in the post-process <110> is performed after the individualization process <111> and before the product shipment process <119>, but after the individualization process <111>. It is preferably performed before the final appearance inspection step <117>, and further after the burn-in step <114> or the selection step <115> using the socket and before the final appearance inspection step <117>. .

In addition to the dry ice cleaning of the first embodiment, as cleaning that can be used for foreign matter removal in a subsequent process, for example, as shown in FIG. 18), air blast cleaning to remove foreign matter (dirt 16) by spraying grain particles 17 such as glass and plastic, as shown in FIG. 18, and chemical solution 18 to product 15 as shown in FIG. And wet cleaning for removing foreign matter (dirt 16). Any of these can be used for removing foreign substances in a subsequent process. However, in the case of air blow cleaning, floating foreign matters can be removed, but it is difficult to remove foreign matters that have pierced the insulating layer 8. In the case of blast cleaning, there is a problem that the surface of the product is scraped off, and since the blast material remains in the details of the product, a water washing treatment is required. Furthermore, wear management of the blast material is necessary. In the case of wet cleaning, the product must be washed with water and dried, and further, contamination control of the chemical solution is required. For this reason, dry ice cleaning is suitable for removing foreign substances in the subsequent process.
(Embodiment 2)
In the second embodiment, an example in which the present invention is applied to a chip level CSP type semiconductor device will be described.

FIG. 20 is a schematic cross-sectional view showing the internal structure of the conductor device according to the second embodiment.
FIG. 21 is a schematic plan view showing the structure on the mounting surface side of the semiconductor device of the second embodiment,
FIG. 22 is a schematic plan view of an essential part showing a wiring pattern on the mounting surface side of the semiconductor device of Embodiment 2.
FIG. 23 is a schematic plan view of a multi-cavity substrate used for manufacturing the semiconductor device of Embodiment 2.
24 is a schematic cross-sectional view of a main part of the multi-cavity substrate of FIG.
FIG. 25 is a flowchart showing a manufacturing process of the semiconductor device of Embodiment 2.
26 to 30 are schematic cross-sectional views showing main parts of the manufacturing process of the semiconductor device according to the second embodiment.

  In order to make the drawing easier to see, the solder bumps shown in FIG. 21 are omitted in FIG.

  As shown in FIGS. 20 and 21, the semiconductor device 30 according to the second embodiment includes a semiconductor chip (semiconductor element) 31 mounted on a main surface (first surface) of a wiring substrate 32 called an interposer. The package structure has a plurality of, for example, ball-shaped solder bumps 36 arranged as protruding electrodes on the back surface (second surface, mounting surface) opposite to the main surface of the substrate 32.

  The semiconductor chip 31 has a square planar shape that intersects the thickness direction, and is square, for example, in the second embodiment. Although not limited to this, the semiconductor chip 31 mainly includes a semiconductor substrate, a plurality of transistor elements formed on the main surface of the semiconductor substrate, a primary wiring formation layer provided on the main surface of the semiconductor substrate, It has a configuration having a surface protective film or the like provided so as to cover the primary wiring forming layer. The primary wiring forming layer is composed of a multilayer wiring layer in which an insulating layer and a wiring layer are stacked in a plurality of stages. The semiconductor substrate is made of, for example, single crystal silicon. The insulating layer of the multilayer wiring layer is formed of, for example, a silicon oxide film. The wiring layer of the multilayer wiring layer is formed of a metal film such as aluminum (Al), aluminum alloy, copper (Cu), or copper alloy. The surface protective film is formed of, for example, a multilayer film in which an inorganic insulating film and an organic insulating film such as a silicon oxide film or a silicon nitride film are stacked.

  The semiconductor chip 31 has a main surface (circuit formation surface, first surface) and a back surface (second surface) located on opposite sides, and an integrated circuit is formed on the main surface side of the semiconductor chip 31. Yes. This integrated circuit is mainly composed of transistor elements formed on the main surface of the semiconductor substrate and wiring formed in the primary wiring forming layer.

  On the main surface of the semiconductor chip 31, for example, a plurality of electrode pads 4 (bonding pads) are formed as connection portions. The plurality of electrode pads 4 are arranged along each side of the semiconductor chip 31, for example.

  The wiring board 32 has a square planar shape intersecting the thickness direction, and is, for example, a square in the second embodiment. The wiring board 32 is not limited to this, but, for example, a core material, a first protective film 32c formed so as to cover the main surface of the core material, and a back surface opposite to the main surface of the core material. And a second protective film 32d formed so as to cover the surface. The core material has a structure having, for example, a wiring layer (conductive layer) on its main surface and back surface. The core material is formed of, for example, a highly elastic resin substrate in which glass fiber is impregnated with epoxy or polyimide resin. Each wiring layer of the core material is formed of, for example, a metal film containing Cu as a main component. The first protective film 32c is formed mainly for the purpose of protecting the wiring formed on the wiring layer on the main surface of the core material, and the second protective film 32d is formed mainly on the wiring layer on the back surface of the core material. It is formed for the purpose of protecting the formed wiring. As the first and second protective films (32c, 32d), for example, insulating resin films are used.

  A chip mounting area (element mounting area) is disposed on the main surface of the wiring substrate 32, and the back surface of the semiconductor chip 31 is bonded and fixed to the chip mounting area with an adhesive 33 interposed therebetween. In addition, on the main surface of the wiring substrate 32, for example, a plurality of electrode pads 32a are arranged as connection portions. In the second embodiment, the plurality of electrode pads 32a are arranged around the semiconductor chip 31 (chip mounting area). A plurality of electrode pads 32b are arranged as connection portions on the back surface of the wiring board 32, and solder bumps 36 are fixed to the plurality of electrode pads 32b, respectively.

  The plurality of electrode pads 4 of the semiconductor chip 31 are electrically connected to the plurality of electrode pads 32a of the wiring board 32, respectively. In the second embodiment, the electrical connection between the electrode pad 4 of the semiconductor chip 31 and the electrode pad 32 a of the wiring substrate 32 is performed by a bonding wire 34. One end of the bonding wire 34 is connected to the electrode pad 4 of the semiconductor chip 31, and the other end of the bonding wire 34 opposite to the one end is connected to the electrode pad 32 a of the wiring substrate 32.

  For example, a gold (Au) wire is used as the bonding wire 34. Further, as a method for connecting the bonding wires 34, for example, a nail head bonding method using ultrasonic vibration in combination with thermocompression bonding is used.

  The semiconductor chip 31, the plurality of bonding wires 34, and the like are sealed with a resin sealing body 35 that is selectively formed on the main surface side of the wiring substrate 32. For the purpose of reducing the stress, the resin sealing body 35 is formed of, for example, a biphenyl-based thermosetting resin to which a phenol-based curing agent, silicone rubber, filler (for example, silica) and the like are added. As a method for forming the resin sealing body 35, a transfer / moding method suitable for mass production is used. The transfer / moding method uses a mold (mold) equipped with a pot, runner, resin injection gate, cavity, etc., and puts thermosetting resin from the pot into the cavity through the runner and resin injection gate. This is a method of forming a resin sealing body by pouring.

  The resin sealing body 35 and the wiring board 32 have substantially the same planar size, and the side surfaces of the resin sealing body 35 and the wiring board 32 are flush with each other. As will be described in detail later, the semiconductor device 30 according to the second embodiment uses a multi-piece substrate (multi-wiring board) having a plurality of product formation regions, and a plurality of product formation regions of the multi-piece substrate. After forming a resin sealing body (collective resin sealing body) for collectively resin-sealing a plurality of mounted semiconductor chips, the multi-chip substrate and the collective resin sealing body are divided into a plurality of pieces. Manufactured by dividing.

  In the wiring board 32, the plurality of electrode pads 32a are electrically connected to the plurality of electrode pads 32b through through-hole wirings. As shown in FIG. 22, the plurality of electrode pads 32b are formed integrally with the corresponding land portion 32h of the through-hole wiring.

  Next, a multi-piece substrate (multi-wiring substrate) 40 used for manufacturing the semiconductor device 30 of the second embodiment will be described with reference to FIGS.

  As shown in FIGS. 23 and 24, the multi-cavity substrate 40 has a square shape that intersects its thickness direction, and is rectangular in the second embodiment. A mold region 41 is provided on the main surface (chip mounting surface) of the multi-cavity substrate 40, and a plurality of product formation regions (device formation regions) 43 are provided in the mold region 41. A chip mounting area 44 is provided in the area 43. In the manufacture of a semiconductor device, a semiconductor chip (31) is mounted in each chip mounting area 44, and a plurality of semiconductor chips (31) mounted in each chip mounting area 44 are collectively placed in a mold area 41. Thus, a resin sealing body (35) for resin sealing is formed.

  Each product formation region 43 is partitioned by a separation region 42 and basically has the same structure and planar shape as the wiring substrate 32 shown in FIG. The wiring substrate 32 is formed by individually dividing a plurality of product formation regions 43 of the multi-cavity substrate 40. In the second embodiment, the multi-cavity substrate 40 is not limited to this, but, for example, a total of 18 products formed in a matrix arrangement (6 × 3) of 6 in the X direction and 3 in the Y direction are formed. The area 43 is configured.

  Next, the manufacture of the semiconductor device 30 according to the second embodiment will be described with reference to FIGS. In the manufacture of the semiconductor device 30 according to the second embodiment, as shown in FIG. 25, the wafer preparation process <201> to the probe inspection process <203> are referred to as a preprocess <200>, and the individualization process <211> to The process up to the shipping process <225> is referred to as a post-process <210>.

  First, as a semiconductor wafer, a semiconductor wafer made of, for example, single crystal silicon is prepared (wafer preparation step <201> in FIG. 25), and then a circuit and a plurality of electrode pads 4 are formed on the main surface (circuit formation surface) of the semiconductor wafer. A plurality of product formation regions (chip formation regions) having a shape are formed in a matrix (circuit formation step <202> in FIG. 25). The plurality of product formation regions are partitioned by a separation region (scribe region) and arranged in a state of being separated from each other. The plurality of product formation regions are mainly formed by forming a primary wiring forming layer (multilayer wiring layer) 3 including transistor elements and electrode pads 4, a surface protective film 5, a bonding opening 5a, and the like on the main surface of the semiconductor wafer. It is formed.

  Next, a test for electrically inspecting the circuit function of each product formation region is performed using a probe card (probe inspection <203> in FIG. 25). The probe inspection is performed by pressing the probe needle of the probe card against the electrode pad 4.

Next, the semiconductor wafer is divided into a plurality of individual pieces (individualization step <211> in FIG. 25). This division is performed by, for example, dicing the semiconductor wafer along the separation region of the semiconductor wafer. In addition, this division is performed in a clean room in an environment where foreign matters of 0.5 [μm] or less are 1000 pieces / cm ³ or less. By this step, the semiconductor chip 31 shown in FIG. 20 is formed.

  Next, the multi-chip substrate 40 shown in FIG. 23 is prepared, and then bonded to each chip mounting region 44 of the plurality of product formation regions 43 on the main surface of the multi-chip substrate 40 as shown in FIG. The semiconductor chip 31 is bonded and fixed via the material 33 (chip mounting step <212> in FIG. 25). The semiconductor chip 31 is bonded and fixed in a state where the back surface of the semiconductor chip 31 faces the main surface of the multi-chip substrate 40.

  Next, in each product formation region 43 on the main surface of the multi-chip substrate 40, as shown in FIG. 27, a plurality of electrode pads 32a in the product formation region 43 and the semiconductor chip 31 mounted in the product formation region 43 are provided. The plurality of electrode pads 4 are electrically connected to each other by a plurality of bonding wires 34 (wire bonding step <213> in FIG. 25). Through this step, the plurality of semiconductor chips 1 are mounted on the main surface of the multi-chip substrate 40.

  Here, the mounting means a state in which the semiconductor chip is bonded and fixed to the substrate, and the electrode pad of the substrate and the electrode pad of the semiconductor chip are electrically connected. In the second embodiment, the semiconductor chip 31 is bonded and fixed by the adhesive 33, and the electrical connection between the electrode pad 32 a in the product formation region 43 of the multi-chip substrate 40 and the electrode pad 4 of the semiconductor chip 31 is performed. The connection is made by a bonding wire 34.

  Next, a plurality of semiconductor chips 31 mounted on the main surface of the multi-chip substrate 40 are collectively sealed with resin, and as shown in FIG. 35 is formed (resin sealing step <214> in FIG. 25). The resin sealing body 35 is formed in the mold region (41) on the main surface of the multi-cavity substrate 40 so as to cover the plurality of product formation regions 43. The semiconductor chip 31 and the bonding wires 34 in each product formation region 43 are formed. Are sealed with a single resin sealing body 35. The resin sealing body 35 uses a molding die having a cavity that collectively covers a plurality of product forming regions 43 of the multi-cavity substrate 40, and injects a thermosetting resin into the cavity of the molding die. It is formed by a batch type transfer molding method.

  Next, as shown in FIG. 29, a plurality of solder bumps 36 are formed corresponding to each product formation region 43 on the back surface opposite to the main surface of the multi-cavity substrate 40 (bump formation process in FIG. 25 < 215>). For the solder bump 36, for example, a flux material is applied on the electrode pad 32b on the back surface of the multi-chip substrate 40, and then a solder ball is supplied onto the electrode pad 32b by a ball supply method, and then the solder ball is melted. Formed by bonding with the electrode pad 32b.

  Next, the flux used in the solder bump forming process is removed by cleaning (flux cleaning process <216> in FIG. 25), and then the resin sealing body corresponding to each product formation region 43 of the multi-chip substrate 40. For example, identification marks such as product name, company name, product type, and production lot number are formed on the upper surface of the film 35 using an ink jet marking method, a direct printing method, a laser marking method, or the like (marking step <217> in FIG. 25).

  Next, as shown in FIG. 30, the multi-piece substrate 40 and the resin sealing body 35 are divided into a plurality of pieces (individualization step <218> in FIG. 25). This division is performed by, for example, dicing the multi-chip substrate 40 and the resin sealing body 35 along the separation region 42 of the multi-chip substrate 40. By this step, the semiconductor device 30 of the second embodiment shown in FIG. 20 is almost completed.

  Next, the separated semiconductor device 30 is packed in a tray (a jig packing step <219> in FIG. 25), and then the semiconductor device 30 is transported to a burn-in process in a state of being packed in the tray. Burn-in is performed on the apparatus 30 (burn-in process <220> in FIG. 5). In the burn-in process, the semiconductor device 30 is mounted on the socket, and the semiconductor device 30 and the burn-in board are electrically connected through the socket. The electrical connection between the socket and the semiconductor device 30 is performed by pressing the solder bumps 36 of the semiconductor device 30 against the contact pins of the socket. Adheres to the contact pins. In the burn-in process, since a plurality of sockets are repeatedly used, the usage frequency of one socket being repeatedly used per day varies depending on the production amount of the semiconductor device and the number of sockets used. It reaches. That is, scraps of the solder bumps 36 are accumulated on the contact pins in accordance with the usage frequency of the socket.

  The scraps accumulated on the contact pins are detached from the contact pins and adhere to the mounting surface of the semiconductor device 30 (surface facing the substrate at the time of mounting) as foreign matter due to some influence. Further, the scrap of the solder bump due to rubbing or the like at the time of pressure bonding also adheres to the mounting surface of the semiconductor device 30 as a foreign substance due to some influence. Further, in the chip level CSP type semiconductor device 30 of the second embodiment, dicing for dividing a semiconductor wafer into a plurality of semiconductor chips 31 is performed in a clean room, but the process after the separation is performed in a non-clean room. Therefore, in addition to the foreign matter due to the scraping of the solder bump 36, other foreign matter may adhere to the mounting surface of the semiconductor device 30 in some cases.

  Next, a characteristic evaluation test for evaluating whether or not the semiconductor device 30 operates normally is performed to select the characteristics of the semiconductor device 1 (selection step <221> in FIG. 25). Also in this characteristic evaluation test, the semiconductor device 30 is mounted on the socket, and the semiconductor device 30 and the performance board (inspection wiring board) are electrically connected via the socket. Foreign matter due to 36 scraps is attached to the mounting surface of the semiconductor device.

  Next, the foreign matter adhering to the mounting surface of the semiconductor device 30 is removed by cleaning. The removal of foreign matters is performed by dry ice cleaning using an automatic foreign matter cleaning apparatus 20 shown in FIG.

  Next, as shown in FIG. 25, a final appearance inspection <223> of the semiconductor device 30 is performed, and then the semiconductor device 30 is packed <224>, and then the semiconductor device 30 is shipped as a product <225>.

  As described above, also in the manufacture of the chip level CSP type semiconductor device 30 of the second embodiment, the same effects as those of the first embodiment can be obtained by performing the foreign substance removal in the subsequent process by cleaning.

  Although the invention made by the present inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. Of course.

  For example, in manufacturing a resin-encapsulated semiconductor device, a multi-chip substrate having a plurality of product formation regions is used, and individual semiconductor chips mounted in each product formation region are resin-sealed for each product formation region. Adopted transfer molding method and batch transfer molding method that uses a multi-piece substrate with multiple product formation areas and encapsulates the semiconductor chips mounted in each product formation area in a batch. Has been. In the second embodiment, the semiconductor device manufactured by the batch transfer molding method has been described. However, the present invention can also be applied to a semiconductor device manufactured by the individual transfer molding method.

  In the second embodiment, the semiconductor device having a plurality of solder bumps on the back side of the wiring board has been described. However, in the present invention, the solder bumps on the back side of the wiring board are omitted, and electrode pads of the wiring board are used. The present invention can also be applied to an LGA (Lahd Grid Array) type semiconductor device used as an external connection terminal.

  In the first embodiment, the semiconductor device having a plurality of solder bumps on the secondary wiring formation layer has been described. However, the present invention omits the solder bumps on the secondary wiring formation layer and forms the secondary wiring. The present invention can also be applied to an LGA type semiconductor device using the electrode pad of the layer as an external connection terminal.

  In the second embodiment, the semiconductor device having one semiconductor chip on the main surface of the wiring board has been described. However, the present invention provides an MCP (Multi Chip Package) having a plurality of semiconductor chips on the main surface of the wiring board.・ Chip package type semiconductor device.

1 is a schematic plan view showing a structure on a mounting surface side of a semiconductor device that is Embodiment 1 of the present invention; It is principal part typical sectional drawing which shows the internal structure of the semiconductor device which is Embodiment 1 of this invention. It is a principal part schematic top view which shows the wiring pattern by the side of the mounting surface of the semiconductor device which is Embodiment 1 of this invention. It is a flowchart which shows the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. It is a typical top view of the semiconductor wafer used for manufacture of the semiconductor device which is Embodiment 1 of the present invention. It is a schematic plan view which shows the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. It is principal part typical sectional drawing which shows the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. FIG. 8 is a schematic cross-sectional view of the relevant part showing the manufacturing process of a semiconductor device following FIG. 7; FIG. 9 is a schematic cross-sectional view of the relevant part showing the manufacturing process of a semiconductor device following FIG. 8; FIG. 10 is a schematic cross-sectional view of the relevant part showing the manufacturing process of a semiconductor device following FIG. 9; FIG. 11 is a schematic cross-sectional view of the relevant part showing the manufacturing process of a semiconductor device following FIG. 10; FIG. 12 is a schematic cross-sectional view of the relevant part showing the manufacturing process of a semiconductor device following FIG. 11; FIG. 9 is a schematic cross-sectional view of the relevant part showing the manufacturing process of a semiconductor device following FIG. 8; It is a typical top view which shows the state which the foreign material adhered to the mounting surface of the semiconductor device. It is a figure which shows schematic structure of the automatic foreign material cleaning apparatus used for manufacture of the semiconductor device which is Embodiment 1 of this invention. It is a schematic diagram for demonstrating dry ice washing | cleaning. It is a schematic diagram for demonstrating air blow cleaning. It is a schematic diagram for demonstrating blast washing | cleaning. It is a schematic diagram for demonstrating wet cleaning. It is typical sectional drawing which shows the internal structure of the semiconductor device which is Embodiment 2 of this invention. It is a typical top view which shows the structure by the side of the mounting surface of the semiconductor device which is Embodiment 2 of this invention. It is a principal part schematic top view which shows the wiring pattern by the side of the mounting surface of the semiconductor device which is Embodiment 2 of this invention. It is a schematic plan view of a multi-cavity substrate used for manufacturing a semiconductor device which is Embodiment 2 of the present invention. It is principal part typical sectional drawing which shows the manufacturing process of the semiconductor device which is Embodiment 2 of this invention. It is a flowchart which shows the manufacturing process of the semiconductor device which is Embodiment 2 of this invention. FIG. 26 is a main part schematic cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 25; FIG. 27 is a main part schematic cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 26; FIG. 28 is a main part schematic cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 27; FIG. 29 is a main part schematic cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 28; FIG. 30 is a main part schematic cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 29;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 1a ... Chip layer, 1b ... Secondary wiring formation layer, 2 ... Semiconductor substrate, 3 ... Primary wiring formation layer (multilayer wiring layer), 4 ... Electrode pad (bonding pad), 5 ... Surface protection film 5a ... bonding opening, 6 ... insulating layer, 6a ... bonding opening, 7 ... rewiring, 7a ... electrode pad (bump land), 8 ... insulating layer, 8a ... bonding opening, 9 ... solder bump,
DESCRIPTION OF SYMBOLS 10 ... Semiconductor wafer, 11 ... Separation area (scribe area), 12 ... Product formation area (device formation area),
DESCRIPTION OF SYMBOLS 20 ... Automatic foreign material washing apparatus, 21 ... Liquefied carbon, 22 ... Pelletizer, 23 ... Pellet form dry ice, 24 ... Pulverizer, 25 ... Pulverized dry ice, 26 ... Cleaning apparatus, 26a ... Nozzle, 27 ... Dust collection unit, 28 ... Foreign matter, 29a, 29b ... Tray,
DESCRIPTION OF SYMBOLS 30 ... Semiconductor device, 31 ... Semiconductor chip, 32 ... Wiring board (interposer), 32a, 32b ... Electrode pad, 32c, 32d ... Protective film, 32h ... Land part of through-hole wiring, 33 ... Adhesive, 34 ... Bonding wire 35 ... Resin sealing body, 36 ... Solder bump,
40 ... Multi-cavity substrate, 41 ... Mold area, 42 ... Separation area, 43 ... Product formation area (device formation area), 44 ... Chip mounting area

Claims (5)

(A) having a plurality of product formation regions partitioned by separation regions, wherein each of the plurality of product formation regions is a first surface and a second surface located on opposite sides of each other, and the second surface Preparing a multi-cavity wiring board having a plurality of electrode pads arranged in
(B) mounting a semiconductor chip on each first surface of the plurality of product formation regions;
A step of the multiple of the semiconductor chip and tree Aburafutome, forming the first surface to the resin sealing body of the multi-piece wiring substrate (c) is mounted on the plurality of product forming region,
(D) to said plurality of said plurality of electrode pads of each of the product forming region, a step of respectively forming a plurality of bump electrodes,
(E) after the step (d) is divided into a plurality of pieces of pre-Symbol matrix substrate before each SL product formation region, and a wiring substrate that is divided into the product forming region, the wiring substrate Forming a plurality of semiconductor packages having the semiconductor chip mounted on the first surface, a resin sealing body sealing the semiconductor chip , and the plurality of bump electrodes formed on the second surface. Process,
(F) After the step (e), the method includes a step of spraying and cleaning a plurality of crushed dry ice on the second surface of the wiring board of the semiconductor package. . In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the pulverized dry ice has a particle size of 0.1 mm to 0.3 mm. In the manufacturing method of the semiconductor device according to claim 1,
The semiconductor further comprising a step of burning in the semiconductor package between the step (e) and the step (f), and a step of selectively testing the burned-in semiconductor package after the burn-in step. Device manufacturing method. In the manufacturing method of the semiconductor device according to claim 3,
The semiconductor chip is a semiconductor chip formed by dialog single semiconductor wafer in a clean room,
A method of manufacturing a semiconductor device, wherein a burn-in process applied to the semiconductor package is performed in a non-clean room. In the manufacturing method of the semiconductor device according to claim 1,
Wiring is formed on the second surface of the wiring board,
A method of manufacturing a semiconductor device, wherein a protective film is formed on the second surface of the wiring board so as to expose each of the plurality of electrode pads and cover the wiring .

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